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FPGA Neopixel Device
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FPGA Neopixel Device
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====================
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====================
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I was really impressed with the Adafruit Neopixel demo. The rainbow effect looks so nice :).
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I was really impressed with the Adafruit Neopixel demo. The rainbow effect looks so nice :).
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It cost me around 5 minutes to setup the environment for the Adafruit Neopixel.
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It cost me around 5 minutes to setup the environment for the Adafruit Neopixel.
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While studying the Adafruit Neopixel implementation and the datasheet of the ws2812,
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While studying the Adafruit Neopixel implementation and the datasheet of the ws2812,
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some things immediately stood out: Assembly for each soc, disabling interrupts to get the
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some things immediately stood out: Assembly for each soc, disabling interrupts to get the
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right timings for each soc shape, etc.
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right timings for each soc shape, etc.
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Now I have a reason to buy an oscilloscope to the see the output of the 1-wire.
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Now I have a reason to buy an oscilloscope to the see the output of the 1-wire.
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I experiemented with my own assembly implementation counting the machinecode cycles of
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I experiemented with my own assembly implementation counting the machinecode cycles of
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ATmega328 to setup ws2812 leds over one wire. The protocol has heavy time constraints +-150ns and the the data of
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ATmega328 to setup ws2812 leds over one wire. The protocol has heavy time constraints +-150ns and the the data of
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leds has to transmit one after another (https://cdn-shop.adafruit.com/datasheets/WS2812.pdf).
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leds has to transmit one after another (https://cdn-shop.adafruit.com/datasheets/WS2812.pdf).
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Here is an example of a 36 foot long neopixel strip https://www.youtube.com/watch?v=I-lR19_kigs.
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Here is an example of a 36 foot long neopixel strip https://www.youtube.com/watch?v=I-lR19_kigs.
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The conclusion is that it makes no sense for me, since it is not portable.
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The conclusion is that it makes no sense for me, since it is not portable.
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To disable interrupts in impeded environments with sensitive application is not ideal.
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To disable interrupts in impeded environments with sensitive application is not ideal.
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There are some exceptions, such as the Rasperry Pi which has a real-time implementation
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There are some exceptions, such as the Rasperry Pi which has a real-time implementation
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by using PWM with supported DMA (https://learn.adafruit.com/neopixels-on-raspberry-pi/overview).
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by using PWM with supported DMA (https://learn.adafruit.com/neopixels-on-raspberry-pi/overview).
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Keeping timings conditions on a ATmega328 is feasible but on a CORTEX-A without HW-Support
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Keeping timings conditions on a ATmega328 is feasible but on a CORTEX-A without HW-Support
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running a sensitive application with caches, disabling interrupts is a bit extreme.
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running a sensitive application with caches, disabling interrupts is a bit extreme.
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So I started my FPGA hobby project and dove right into FPGA programing and verilog.
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So I started my FPGA hobby project and dove right into FPGA programing and verilog.
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My approach is using a SPI to collect 24-RGBs-Strips-Data and a SYNC from a impeded SoC.
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My approach is using a SPI to collect 24-RGBs-Strips-Data and a SYNC from a impeded SoC.
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Another approach I came up with is to reuse the Adafruit-Neopixel-Library.
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Another approach I came up with is to reuse the Adafruit-Neopixel-Library.
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I attached my FPGA_NeoPixel.h file. Technically it inherits from Adafruit_NeoPixel and overwrites
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I attached my FPGA_NeoPixel.h file. Technically it inherits from Adafruit_NeoPixel and overwrites
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the void show() with SPI-Code so you are able to use the methods from Adafruit_Neopixel to set
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the void show() with SPI-Code so you are able to use the methods from Adafruit_Neopixel to set
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leds or calculate color spaces. I have tested it on an Arduiono-Nano but it is easy to
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leds or calculate color spaces. I have tested it on an Arduiono-Nano but it is easy to
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port the Libs to other SoCs. The only things that matter are the SPI and Neopixel managment.
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port the Libs to other SoCs. The only things that matter are the SPI and Neopixel managment.
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The implementation is based on an iceFun (ice40-hx8k, https://www.robot-electronics.co.uk/icefun.html). It is easy to port it to another FPGA,
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The implementation is based on an iceFun (ice40-hx8k, https://www.robot-electronics.co.uk/icefun.html). It is easy to port it to another FPGA,
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you only have to specify the frequency and pins. The current implementation is using a 16K-Fifo (ice40-hk8),
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you only have to specify the frequency and pins. The current implementation is using a 1024-Fifo (ice40-hk8),
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maybe you can even try to control an 16k strip with it ;)
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maybe you can even try to control an 1024 strip with it. The possibility to control over 5K with ice40-hx8 (128k/24 ~ 5.3k)
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A short video shows the result https://www.youtube.com/watch?v=bKlIKz7Y1Lk of my implementation.
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is given. You have only to modify the ADDRESS_LINE parameter of ram_sync in ws2812_ctl.v
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A short video shows the result https://www.youtube.com/watch?v=IhsmrSM3q_E of my implementation.
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A FPGA has many I/Os just extend it to many 1-wire-outputs to handle more strips in parallel.
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A FPGA has many I/Os just extend it to many 1-wire-outputs to handle more strips in parallel.
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I will make my fpga project available on github and if you find the time to take a
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I will make my fpga project available on github and if you find the time to take a
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look and tinker with it, I would be grateful for any feedback.
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look and tinker with it, I would be grateful for any feedback.
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Some background why I started this project.
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Some background why I started this project.
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I searched for an open source command based verilog compiler and I found
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I searched for an open source command based verilog compiler and I found
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Icarus Verilog (http://iverilog.icarus.com/) + gtkwave from Stephen Williams.
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Icarus Verilog (http://iverilog.icarus.com/) + gtkwave from Stephen Williams.
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In this context I found verilator which is awesome. (https://www.veripool.org/)
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In this context I found verilator which is awesome. (https://www.veripool.org/)
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Probably by accident I found the icestorm project by Mr.
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Probably by accident I found the icestorm project by Mr.
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Cliffword and I was so impressed by yosys and arachne-pnr/nextpnr because Synthesis is a domain
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Cliffword and I was so impressed by yosys and arachne-pnr/nextpnr because Synthesis is a domain
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of some companies like synopsis, cadence, mentor graphics with very expensiv license costs.
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of some companies like synopsis, cadence, mentor graphics with very expensiv license costs.
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In my opinion Mr. Cliffword changed the rules in circuit design (http://opencircuitdesign.com/).
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In my opinion Mr. Cliffword changed the rules in circuit design (http://opencircuitdesign.com/).
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I am very greatful to him. Now we have compilers for programming languages,
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I am very greatful to him. Now we have compilers for programming languages,
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operating systems and circuit design tools FOSS like - it is so amazing.
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operating systems and circuit design tools FOSS like - it is so amazing.
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