# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V-compliant)
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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V-compliant)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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## Table of Content
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## Table of Content
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* [Introduction](#Introduction)
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* [Introduction](#Introduction)
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* [Features](#Features)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Performance](#Performance)
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* [Top Entity](#Top-Entity)
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* [Top Entity](#Top-Entity)
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* [**Getting Started**](#Getting-Started)
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* [**Getting Started**](#Getting-Started)
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* [Contribute](#Contribute)
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* [Contribute](#Contribute)
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* [Legal](#Legal)
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* [Legal](#Legal)
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## Introduction
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## Introduction
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The **NEORV32 processor** is a customizable full-scale mikrocontroller-like processor system based on the RISC-V-compliant
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The **NEORV32 processor** is a customizable full-scale mikrocontroller-like processor system based on the RISC-V-compliant
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`rv32i` NEORV32 CPU with optional `M`, `E`, `C` and `U`, `Zicsr` and `Zifencei` extensions and optional physical memory protection (PMP).
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`rv32i` NEORV32 CPU with optional `M`, `E`, `C` and `U`, `Zicsr` and `Zifencei` extensions and optional physical memory protection (PMP).
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The CPU was built from scratch and is compliant to the *Unprivileged ISA Specification Version 2.2* and a subset of the *Privileged Architecture
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The CPU was built from scratch and is compliant to the *Unprivileged ISA Specification Version 2.2* and a subset of the *Privileged Architecture
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Specification Version 1.12-draft*.
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Specification Version 1.12-draft*.
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The **processor** is intended as auxiliary processor within a larger SoC designs or as stand-alone
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The **processor** is intended as auxiliary processor within a larger SoC designs or as stand-alone
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custom microcontroller. Its top entity can be directly synthesized for any FPGA without modifications and
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custom microcontroller. Its top entity can be directly synthesized for any FPGA without modifications and
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provides a full-scale RISC-V based microcontroller with common peripherals like GPIO, serial interfaces for
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provides a full-scale RISC-V based microcontroller with common peripherals like GPIO, serial interfaces for
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UART, I²C and SPI, timers, external bus interface and embedded memories. All optional features beyond the
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UART, I²C and SPI, timers, external bus interface and embedded memories. All optional features beyond the
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base CPU can be enabled and configured via VHDL generics.
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base CPU can be enabled and configured via VHDL generics.
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Alternatively, you can use the **NEORV32 CPU** as stand-alone central processing unit and build your own microcontroller
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Alternatively, you can use the **NEORV32 CPU** as stand-alone central processing unit and build your own microcontroller
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or processor system around it.
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or processor system around it.
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This project comes with a complete software ecosystem that features core libraries for high-level
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This project comes with a complete software ecosystem that features core libraries for high-level
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usage of the provided functions and peripherals, application makefiles, a runtime environment and
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usage of the provided functions and peripherals, application makefiles, a runtime environment and
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several example programs. All software source files provide a doxygen-based documentary.
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several example programs. All software source files provide a doxygen-based documentary.
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The project is intended to work "out of the box". Just synthesize the test setup from this project,
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The project is intended to work "out of the box". Just synthesize the test setup from this project,
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upload it to your FPGA board of choice and start playing with the NEORV32. If you do not want to
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upload it to your FPGA board of choice and start playing with the NEORV32. If you do not want to
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[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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[compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Key Features
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### Key Features
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `rv32Zifencei` and PMP (physical memory protection) extensions
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `rv32Zifencei` and PMP (physical memory protection) extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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- Small hardware footprint and high operating frequency
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- Highly configurable CPU and processor setup
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- Highly configurable CPU and processor setup
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### Design Principles
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### Design Principles
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* From zero to main(): Completely open source and documented.
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* From zero to main(): Completely open source and documented.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Easy to use – working out of the box.
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* Easy to use – working out of the box.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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### Status
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| Project component | CI status | Note |
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| Project component | CI status | Note |
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|:--------------------------------------------------------------------------------|:----------|:---------|
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|:--------------------------------------------------------------------------------|:----------|:---------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) |
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
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| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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### Non RISC-V-Compliant Issues
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### Non RISC-V-Compliant Issues
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* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
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* No exception is triggered for the `E` CPU extension when using registers above `x15` (*needs fixing*)
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* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
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* `misa` CSR is read-only - no dynamic enabling/disabling of implemented CPU extensions during runtime
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* `mcause` CSR is read-only
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* `mcause` CSR is read-only
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The physical memory protection (**PMP**) only supports `NAPOT` mode and only up to 8 regions
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* The physical memory protection (**PMP**) only supports `NAPOT` mode and only up to 8 regions
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### Custom CPU Extensions
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### Custom CPU Extensions
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The custom extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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The custom extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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### To-Do / Wish List
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### To-Do / Wish List
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- Add AXI(-Lite) bridges
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- Add AXI(-Lite) bridges
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Option to use DSP-based multiplier in `M` extension (would be so much faster)
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- Synthesis results for more platforms
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- Synthesis results for more platforms
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- Port Dhrystone benchmark
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Implement atomic operations (`A` extension) and floating-point operations (`F` extension)
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Maybe port an RTOS (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr), [freeRTOS](https://www.freertos.org) or [RIOT](https://www.riot-os.org))
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- Make a 64-bit branch someday
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- Make a 64-bit branch someday
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## Features
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## Features
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### Processor Features
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### Processor Features
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Highly customizable processor configuration:
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Highly customizable processor configuration:
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional internal bootloader with UART console and automatic SPI flash boot option
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- Optional internal bootloader with UART console and automatic SPI flash boot option
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- Optional machine system timer (MTIME), RISC-V-compliant
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- Optional machine system timer (MTIME), RISC-V-compliant
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- Optional universal asynchronous receiver and transmitter (UART)
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- Optional universal asynchronous receiver and transmitter (UART)
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- Optional 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
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- Optional 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
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- Optional two wire serial interface controller (TWI), compatible to the I²C standard
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- Optional two wire serial interface controller (TWI), compatible to the I²C standard
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- Optional general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
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- Optional general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
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- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- Optional watchdog timer (WDT)
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- Optional watchdog timer (WDT)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- Optional GARO-based true random number generator (TRNG)
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- Optional GARO-based true random number generator (TRNG)
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- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
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- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
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- System configuration information memory to check hardware configuration by software (SYSINFO)
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- System configuration information memory to check hardware configuration by software (SYSINFO)
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### CPU Features
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### CPU Features
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The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the
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The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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**General**:
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**General**:
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* Modified Harvard architecture (separate CPU interfaces for data and instructions; single processor-bus via bus switch)
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* Modified Harvard architecture (separate CPU interfaces for data and instructions; single processor-bus via bus switch)
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* No hardware support of unaligned accesses - they will trigger an exception
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* No hardware support of unaligned accesses - they will trigger an exception
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* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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**RV32I base instruction set** (`I` extension):
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**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* System instructions: `ECALL` `EBREAK` `FENCE`
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* System instructions: `ECALL` `EBREAK` `FENCE`
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**Compressed instructions** (`C` extension):
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**Compressed instructions** (`C` extension):
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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**Embedded CPU version** (`E` extension):
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**Embedded CPU version** (`E` extension):
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* Reduced register file (only the 16 lowest registers)
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* Reduced register file (only the 16 lowest registers)
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**Integer multiplication and division hardware** (`M` extension):
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**Integer multiplication and division hardware** (`M` extension):
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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**Privileged architecture / CSR access** (`Zicsr` extension):
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**Privileged architecture / CSR access** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `MRET` `WFI`
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* System instructions: `MRET` `WFI`
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* Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
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* Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid`
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` `marchid` `mimpid` `mhartid`
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* Supported exceptions and interrupts:
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* Supported exceptions and interrupts:
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* Misaligned instruction address
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* Misaligned instruction address
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* Instruction access fault
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* Instruction access fault
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* Illegal instruction
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* Illegal instruction
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* Breakpoint (via `ebreak` instruction)
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* Breakpoint (via `ebreak` instruction)
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* Load address misaligned
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* Load address misaligned
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* Load access fault
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* Load access fault
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* Store address misaligned
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* Store address misaligned
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* Store access fault
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* Store access fault
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* Environment call from M-mode (via `ecall` instruction)
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* Environment call from M-mode (via `ecall` instruction)
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* Machine timer interrupt `mti` (via processor's MTIME unit)
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* Machine timer interrupt `mti` (via processor's MTIME unit)
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* Machine software interrupt `msi` (via external signal)
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* Machine software interrupt `msi` (via external signal)
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* Machine external interrupt `mei` (via external signal)
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* Machine external interrupt `mei` (via external signal)
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* Four fast interrupt requests (custom extension)
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* Four fast interrupt requests (custom extension)
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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* System instructions: `FENCEI`
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* System instructions: `FENCE.I`
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**Physical memory protection** (`PMP`, requires `Zicsr` extension):
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**Physical memory protection** (`PMP`, requires `Zicsr` extension):
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* Additional machine CSRs: `pmpcfgx` `pmpaddrx`
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* Additional machine CSRs: `pmpcfgx` `pmpaddrx`
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## FPGA Implementation Results
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## FPGA Implementation Results
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the CPU's generics is assumed (no PMP). No constraints were used at all.
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of the CPU's generics is assumed (no PMP). No constraints were used at all.
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### CPU
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### CPU
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|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
|
|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
|
| `rv32i` | 1122 | 481 | 2048 | 0 | 110 MHz |
|
| `rv32i` | 1122 | 481 | 2048 | 0 | 110 MHz |
|
| `rv32i` + `Zicsr` + `Zifencei` | 1891 | 819 | 2048 | 0 | 100 MHz |
|
| `rv32i` + `Zicsr` + `Zifencei` | 1891 | 819 | 2048 | 0 | 100 MHz |
|
| `rv32im` + `Zicsr` + `Zifencei` | 2496 | 1067 | 2048 | 0 | 100 MHz |
|
| `rv32im` + `Zicsr` + `Zifencei` | 2496 | 1067 | 2048 | 0 | 100 MHz |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 2734 | 1066 | 2048 | 0 | 100 MHz |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 2734 | 1066 | 2048 | 0 | 100 MHz |
|
| `rv32emc` + `Zicsr` + `Zifencei` | 2722 | 1066 | 1024 | 0 | 100 MHz |
|
| `rv32emc` + `Zicsr` + `Zifencei` | 2722 | 1066 | 1024 | 0 | 100 MHz |
|
|
|
### Processor-Internal Peripherals and Memories
|
### Processor-Internal Peripherals and Memories
|
|
|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
|
| BOOT ROM | Bootloader ROM (4kB) | 4 | 1 | 32 768 | 0 |
|
| BOOT ROM | Bootloader ROM (4kB) | 4 | 1 | 32 768 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
|
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
|
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
|
| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
|
| GPIO | General purpose input/output ports | 40 | 33 | 0 | 0 |
|
| GPIO | General purpose input/output ports | 40 | 33 | 0 | 0 |
|
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
|
| MTIME | Machine system timer | 266 | 166 | 0 | 0 |
|
| MTIME | Machine system timer | 266 | 166 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
|
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
|
| SPI | Serial peripheral interface | 198 | 125 | 0 | 0 |
|
| SPI | Serial peripheral interface | 198 | 125 | 0 | 0 |
|
| SYSINFO | System configuration information memory | 10 | 9 | 0 | 0 |
|
| SYSINFO | System configuration information memory | 10 | 9 | 0 | 0 |
|
| TRNG | True random number generator | 105 | 93 | 0 | 0 |
|
| TRNG | True random number generator | 105 | 93 | 0 | 0 |
|
| TWI | Two-wire interface | 75 | 44 | 0 | 0 |
|
| TWI | Two-wire interface | 75 | 44 | 0 | 0 |
|
| UART | Universal asynchronous receiver/transmitter | 153 | 108 | 0 | 0 |
|
| UART | Universal asynchronous receiver/transmitter | 153 | 108 | 0 | 0 |
|
| WDT | Watchdog timer | 59 | 45 | 0 | 0 |
|
| WDT | Watchdog timer | 59 | 45 | 0 | 0 |
|
|
|
|
|
### Exemplary FPGA Setups
|
### Exemplary FPGA Setups
|
|
|
Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
|
Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*,
|
no external memory interface, no PMP and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
no external memory interface, no PMP and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
to FPGA pins - except for the Wishbone bus and the interrupt signals.
|
to FPGA pins - except for the Wishbone bus and the interrupt signals.
|
|
|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
| Vendor | FPGA | Board | Toolchain | Impl. strategy |CPU | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
| Vendor | FPGA | Board | Toolchain | Impl. strategy |CPU | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|---------------:|
|
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:---------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|---------------:|
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `Zicsr` + `Zifencei` | 3934 (18%) | 1799 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz |
|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `Zicsr` + `Zifencei` | 3934 (18%) | 1799 (8%) | 0 (0%) | 231424 (38%) | - | - | 100 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32ic` + `Zicsr` + `Zifencei` | 4895 (92%) | 1636 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.875 MHz |
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | timing | `rv32ic` + `Zicsr` + `Zifencei` | 4895 (92%) | 1636 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.875 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `Zicsr` + `Zifencei` | 2432 (12%) | 1852 (4%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `Zicsr` + `Zifencei` | 2432 (12%) | 1852 (4%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
|
|
**Notes**
|
**Notes**
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).
|
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
|
|
## Performance
|
## Performance
|
|
|
### CoreMark Benchmark
|
### CoreMark Benchmark
|
|
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
|
|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
~~~
|
~~~
|
**Configuration**
|
**Configuration**
|
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
|
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0
|
Compiler: RISCV32-GCC 10.1.0
|
Peripherals: UART for printing the results
|
Peripherals: UART for printing the results
|
~~~
|
~~~
|
|
|
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
|:---------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
|:---------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
| `rv32i` + `Zicsr` + `Zifencei` | 21 600 bytes | `-O2` | 27.02 | 0.2702 |
|
| `rv32i` + `Zicsr` + `Zifencei` | 21 600 bytes | `-O2` | 27.02 | 0.2702 |
|
| `rv32im` + `Zicsr` + `Zifencei` | 20 976 bytes | `-O2` | 57.14 | 0.5714 |
|
| `rv32im` + `Zicsr` + `Zifencei` | 20 976 bytes | `-O2` | 57.14 | 0.5714 |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 16 348 bytes | `-O2` | 57.14 | 0.5714 |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 16 348 bytes | `-O2` | 57.14 | 0.5714 |
|
|
|
|
|
### Instruction Cycles
|
### Instruction Cycles
|
|
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
CPU extensions.
|
CPU extensions.
|
|
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
`M` extension use a bit-serial approach and require several cycles for completion.
|
`M` extension use a bit-serial approach and require several cycles for completion.
|
|
|
The following table shows the performance results for successfully running 2000 CoreMark
|
The following table shows the performance results for successfully running 2000 CoreMark
|
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
|
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
|
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O2`.
|
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O2`.
|
|
|
Results generated for hardware version: `1.3.0.0`
|
Results generated for hardware version: `1.3.0.0`
|
|
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
|
|:---------------------------------|----------------------:|----------------------:|:-----------:|
|
|:---------------------------------|----------------------:|----------------------:|:-----------:|
|
| `rv32i` + `Zicsr` + `Zifencei` | 7 433 933 906 | 1 494 298 800 | 4.97 |
|
| `rv32i` + `Zicsr` + `Zifencei` | 7 433 933 906 | 1 494 298 800 | 4.97 |
|
| `rv32im` + `Zicsr` + `Zifencei` | 3 589 861 906 | 628 281 454 | 5.71 |
|
| `rv32im` + `Zicsr` + `Zifencei` | 3 589 861 906 | 628 281 454 | 5.71 |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 3 587 131 226 | 628 282 016 | 5.70 |
|
| `rv32imc` + `Zicsr` + `Zifencei` | 3 587 131 226 | 628 282 016 | 5.70 |
|
|
|
|
|
|
|
## Top Entities
|
## Top Entities
|
|
|
The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
|
The top entity of the **processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
(except for the TWI signals, which are of type *std_logic*).
|
(except for the TWI signals, which are of type *std_logic*).
|
|
|
The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
|
The top entity of the **CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
|
All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
|
All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
|
|
|
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
|
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
|
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
|
Alternative top entities can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
|
|
|
### Processor
|
### Processor
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_top is
|
entity neorv32_top is
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Memory configuration: Instruction memory --
|
-- Memory configuration: Instruction memory --
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
-- Memory configuration: Data memory --
|
-- Memory configuration: Data memory --
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
-- Memory configuration: External memory interface --
|
-- Memory configuration: External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- Wishbone bus interface (available if MEM_EXT_USE = true) --
|
-- Wishbone bus interface (available if MEM_EXT_USE = true) --
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- GPIO (available if IO_GPIO_USE = true) --
|
-- GPIO (available if IO_GPIO_USE = true) --
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
-- UART (available if IO_UART_USE = true) --
|
-- UART (available if IO_UART_USE = true) --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
-- SPI (available if IO_SPI_USE = true) --
|
-- SPI (available if IO_SPI_USE = true) --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- TWI (available if IO_TWI_USE = true) --
|
-- TWI (available if IO_TWI_USE = true) --
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
-- PWM (available if IO_PWM_USE = true) --
|
-- PWM (available if IO_PWM_USE = true) --
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
-- Interrupts --
|
-- Interrupts --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
);
|
);
|
end neorv32_top;
|
end neorv32_top;
|
```
|
```
|
|
|
### CPU
|
### CPU
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_cpu is
|
entity neorv32_cpu is
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_USE : boolean := false; -- implement PMP?
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Bus Interface --
|
-- Bus Interface --
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- instruction bus interface --
|
-- instruction bus interface --
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
-- data bus interface --
|
-- data bus interface --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
|
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
|
);
|
);
|
end neorv32_cpu;
|
end neorv32_cpu;
|
```
|
```
|
|
|
|
|
|
|
## Getting Started
|
## Getting Started
|
|
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
|
|
[ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
|
[ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
|
|
|
|
|
### Toolchain
|
### Toolchain
|
|
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
|
|
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
|
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain.
|
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain.
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
Make sure to use the `ilp32` or `ilp32e` ABI.
|
|
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
|
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
|
|
|
|
### Dowload the NEORV32 and Create a Hardware Project
|
### Dowload the NEORV32 and Create a Hardware Project
|
|
|
Get the sources of the NEORV32 Processor project. You can either download a [release](https://github.com/stnolting/neorv32/releases)
|
Get the sources of the NEORV32 Processor project. You can either download a [release](https://github.com/stnolting/neorv32/releases)
|
or get the most recent version of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip) or using `git clone` (suggested for easy project updates via `git pull`):
|
or get the most recent version of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip) or using `git clone` (suggested for easy project updates via `git pull`):
|
|
|
$ git clone https://github.com/stnolting/neorv32.git
|
$ git clone https://github.com/stnolting/neorv32.git
|
|
|
Create a new project with your FPGA design tool of choice and add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
Create a new project with your FPGA design tool of choice and add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
folder to this project. Make sure to add them to a **new library** called `neorv32`.
|
folder to this project. Make sure to add them to a **new library** called `neorv32`.
|
|
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART, clock, reset and some GPIO output sginals are
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART, clock, reset and some GPIO output sginals are
|
propagated (basically, its a FPGA "hello world" example):
|
propagated (basically, its a FPGA "hello world" example):
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_test_setup is
|
entity neorv32_test_setup is
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- GPIO --
|
-- GPIO --
|
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
|
-- UART --
|
-- UART --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_rxd_i : in std_ulogic := '0' -- UART receive data
|
uart_rxd_i : in std_ulogic := '0' -- UART receive data
|
);
|
);
|
end neorv32_test_setup;
|
end neorv32_test_setup;
|
```
|
```
|
|
|
|
|
### Compiling and Uploading One of the Example Projects
|
### Compiling and Uploading One of the Example Projects
|
|
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
|
`sw/example/blink_led` and run:
|
`sw/example/blink_led` and run:
|
|
|
neorv32/sw/example/blink_led$ make check
|
neorv32/sw/example/blink_led$ make check
|
|
|
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
|
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
|
executable `neorv32_exe.bin` in the same folder.
|
executable `neorv32_exe.bin` in the same folder.
|
|
|
neorv32/sw/example/blink_led$ make clean_all compile
|
neorv32/sw/example/blink_led$ make clean_all compile
|
|
|
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
|
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
|
uses the following default UART configuration:
|
uses the following default UART configuration:
|
|
|
- 19200 Baud
|
- 19200 Baud
|
- 8 data bits
|
- 8 data bits
|
- 1 stop bit
|
- 1 stop bit
|
- No parity bits
|
- No parity bits
|
- No transmission / flow control protocol (raw bytes only)
|
- No transmission / flow control protocol (raw bytes only)
|
- Newline on `\r\n` (carriage return & newline)
|
- Newline on `\r\n` (carriage return & newline)
|
|
|
Use the bootloader console to upload the `neorv32_exe.bin` file and run your application image.
|
Use the bootloader console to upload the `neorv32_exe.bin` file and run your application image.
|
|
|
```
|
```
|
<< NEORV32 Bootloader >>
|
<< NEORV32 Bootloader >>
|
|
|
BLDV: Jul 6 2020
|
BLDV: Jul 6 2020
|
HWV: 1.0.1.0
|
HWV: 1.0.1.0
|
CLK: 0x0134FD90 Hz
|
CLK: 0x0134FD90 Hz
|
USER: 0x0001CE40
|
USER: 0x0001CE40
|
MISA: 0x42801104
|
MISA: 0x42801104
|
CONF: 0x03FF0035
|
CONF: 0x03FF0035
|
IMEM: 0x00010000 bytes @ 0x00000000
|
IMEM: 0x00010000 bytes @ 0x00000000
|
DMEM: 0x00010000 bytes @ 0x80000000
|
DMEM: 0x00010000 bytes @ 0x80000000
|
|
|
Autoboot in 8s. Press key to abort.
|
Autoboot in 8s. Press key to abort.
|
Aborted.
|
Aborted.
|
|
|
Available CMDs:
|
Available CMDs:
|
h: Help
|
h: Help
|
r: Restart
|
r: Restart
|
u: Upload
|
u: Upload
|
s: Store to flash
|
s: Store to flash
|
l: Load from flash
|
l: Load from flash
|
e: Execute
|
e: Execute
|
CMD:> u
|
CMD:> u
|
Awaiting neorv32_exe.bin... OK
|
Awaiting neorv32_exe.bin... OK
|
CMD:> e
|
CMD:> e
|
Booting...
|
Booting...
|
|
|
Blinking LED demo program
|
Blinking LED demo program
|
```
|
```
|
|
|
Going further: Take a look at the _Let's Get It Started!_ chapter of the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
Going further: Take a look at the _Let's Get It Started!_ chapter of the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
|
|
|
|
## Contribute
|
## Contribute
|
|
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
|
to open a [new issue](https://github.com/stnolting/neorv32/issues).
|
to open a [new issue](https://github.com/stnolting/neorv32/issues).
|
|
|
If you want to get involved you can also directly drop me a line (mailto:stnolting@gmail.com).
|
If you want to get involved you can also directly drop me a line (mailto:stnolting@gmail.com).
|
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
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Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
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## Legal
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## Legal
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This project is released under the BSD 3-Clause license. No copyright infringement intended.
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This project is released under the BSD 3-Clause license. No copyright infringement intended.
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Other implied or used projects might have different licensing - see their documentation to get more information.
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Other implied or used projects might have different licensing - see their documentation to get more information.
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#### Citation
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#### Citation
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If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
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If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
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> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
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> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
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#### BSD 3-Clause License
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#### BSD 3-Clause License
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Copyright (c) 2020, Stephan Nolting. All rights reserved.
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Copyright (c) 2020, Stephan Nolting. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are
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Redistribution and use in source and binary forms, with or without modification, are
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permitted provided that the following conditions are met:
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permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this list of
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1. Redistributions of source code must retain the above copyright notice, this list of
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conditions and the following disclaimer.
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conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice, this list of
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2. Redistributions in binary form must reproduce the above copyright notice, this list of
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conditions and the following disclaimer in the documentation and/or other materials
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conditions and the following disclaimer in the documentation and/or other materials
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provided with the distribution.
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provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors may be used to
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3. Neither the name of the copyright holder nor the names of its contributors may be used to
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endorse or promote products derived from this software without specific prior written
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endorse or promote products derived from this software without specific prior written
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permission.
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permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
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OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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OF THE POSSIBILITY OF SUCH DAMAGE.
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OF THE POSSIBILITY OF SUCH DAMAGE.
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#### Limitation of Liability for External Links
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#### Limitation of Liability for External Links
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Our website contains links to the websites of third parties („external links“). As the
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Our website contains links to the websites of third parties („external links“). As the
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content of these websites is not under our control, we cannot assume any liability for
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content of these websites is not under our control, we cannot assume any liability for
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such external content. In all cases, the provider of information of the linked websites
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such external content. In all cases, the provider of information of the linked websites
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is liable for the content and accuracy of the information provided. At the point in time
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is liable for the content and accuracy of the information provided. At the point in time
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when the links were placed, no infringements of the law were recognisable to us. As soon
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when the links were placed, no infringements of the law were recognisable to us. As soon
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as an infringement of the law becomes known to us, we will immediately remove the
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as an infringement of the law becomes known to us, we will immediately remove the
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link in question.
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link in question.
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#### Proprietary Notice
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#### Proprietary Notice
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"Windows" is a trademark of Microsoft Corporation.
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"Windows" is a trademark of Microsoft Corporation.
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"Artix" and "Vivado" are trademarks of Xilinx Inc.
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"Artix" and "Vivado" are trademarks of Xilinx Inc.
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"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
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"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
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"Artix" and "Vivado" are trademarks of Xilinx, Inc.
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"Artix" and "Vivado" are trademarks of Xilinx, Inc.
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"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
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"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
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"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
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"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
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## Acknowledgement
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## Acknowledgement
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart:
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
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Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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Made with :coffee: in Hannover, Germany.
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Made with :coffee: in Hannover, Germany.
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