[![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32)
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[![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32)
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[![Documentation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Documentation/master?longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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[![Documentation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Documentation/master?longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation)
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\
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\
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[![riscv-arch-test](https://img.shields.io/github/workflow/status/stnolting/neorv32/riscv-arch-test/master?longCache=true&style=flat-square&label=riscv-arch-test&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[![riscv-arch-test](https://img.shields.io/github/workflow/status/stnolting/neorv32/riscv-arch-test/master?longCache=true&style=flat-square&label=riscv-arch-test&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3Ariscv-arch-test)
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[![Processor](https://img.shields.io/github/workflow/status/stnolting/neorv32/Processor/master?longCache=true&style=flat-square&label=Processor&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[![Processor](https://img.shields.io/github/workflow/status/stnolting/neorv32/Processor/master?longCache=true&style=flat-square&label=Processor&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor)
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[![Implementation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Implementation/master?longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[![Implementation](https://img.shields.io/github/workflow/status/stnolting/neorv32/Implementation/master?longCache=true&style=flat-square&label=Implementation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AImplementation)
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[![Windows](https://img.shields.io/github/workflow/status/stnolting/neorv32/Windows/master?longCache=true&style=flat-square&label=Windows&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
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[![Windows](https://img.shields.io/github/workflow/status/stnolting/neorv32/Windows/master?longCache=true&style=flat-square&label=Windows&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AWindows)
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[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32)
|
[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo_dark.png)](https://github.com/stnolting/neorv32)
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|
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# The NEORV32 RISC-V Processor
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# The NEORV32 RISC-V Processor
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|
|
[![license](https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![license](https://img.shields.io/github/license/stnolting/neorv32?longCache=true&style=flat-square)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
|
[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
|
[![DOI](https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg)](https://doi.org/10.5281/zenodo.5018888)
|
[![DOI](https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg)](https://doi.org/10.5281/zenodo.5018888)
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[![datasheet (pdf)](https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[![datasheet (pdf)](https://img.shields.io/badge/data%20sheet-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://github.com/stnolting/neorv32/releases/tag/nightly)
|
[![datasheet (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square)](https://stnolting.github.io/neorv32)
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[![datasheet (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square)](https://stnolting.github.io/neorv32)
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[![userguide (pdf)](https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[![userguide (pdf)](https://img.shields.io/badge/user%20guide-PDF-ffbd00?longCache=true&style=flat-square&logo=asciidoctor)](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[![userguide (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square)](https://stnolting.github.io/neorv32/ug)
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[![userguide (html)](https://img.shields.io/badge/-HTML-ffbd00?longCache=true&style=flat-square)](https://stnolting.github.io/neorv32/ug)
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[![doxygen](https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&style=flat-square&logo=Doxygen)](https://stnolting.github.io/neorv32/sw/files.html)
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[![doxygen](https://img.shields.io/badge/doxygen-HTML-ffbd00?longCache=true&style=flat-square&logo=Doxygen)](https://stnolting.github.io/neorv32/sw/files.html)
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1. [Overview](#1-Overview)
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1. [Overview](#1-Overview)
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1. [Key Features](#Project-Key-Features)
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1. [Key Features](#Project-Key-Features)
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2. [Processor/SoC Features](#2-NEORV32-Processor-Features)
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2. [Processor/SoC Features](#2-NEORV32-Processor-Features)
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1. [FPGA Implementation Results](#FPGA-Implementation-Results---Processor)
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1. [FPGA Implementation Results](#FPGA-Implementation-Results---Processor)
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3. [CPU Features](#3-NEORV32-CPU-Features)
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3. [CPU Features](#3-NEORV32-CPU-Features)
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1. [Available ISA Extensions](#Available-ISA-Extensions)
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1. [Available ISA Extensions](#Available-ISA-Extensions)
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2. [FPGA Implementation Results](#FPGA-Implementation-Results---CPU)
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2. [FPGA Implementation Results](#FPGA-Implementation-Results---CPU)
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3. [Performance](#Performance)
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3. [Performance](#Performance)
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4. [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
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4. [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
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5. [**Getting Started**](#5-Getting-Started) :rocket:
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5. [**Getting Started**](#5-Getting-Started) :rocket:
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## 1. Overview
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## 1. Overview
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|
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU.
|
The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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custom / customizable microcontroller.
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custom / customizable microcontroller.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
|
|
are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
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|
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:information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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|
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:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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The *doxygen*-based documentation of the *software framework* is also available online
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The *doxygen*-based documentation of the *software framework* is also available online
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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|
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between *official* releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
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:package: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary setups targeting
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various FPGA boards and toolchains to get you started. Several example programs (including a FreeRTOS port) to be run on your setup
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various FPGA boards and toolchains to get you started. Several example programs (including a FreeRTOS port) to be run on your setup
|
can be found in [`sw/example`](https://github.com/stnolting/neorv32/tree/master/sw/example).
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can be found in [`sw/example`](https://github.com/stnolting/neorv32/tree/master/sw/example).
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:kite: Upstream [**Zephyr RTOS**](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) support.
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:kite: Upstream [**Zephyr RTOS**](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) support.
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
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:spiral_notepad: Check out the [project boards](https://github.com/stnolting/neorv32/projects) for a list of current **ideas**,
|
**TODOs**, features being **planned** and **work-in-progress**.
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**TODOs**, features being **planned** and **work-in-progress**.
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:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
|
:bulb: Feel free to open a [new issue](https://github.com/stnolting/neorv32/issues) or start a
|
[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
|
[new discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
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not working as expected.
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not working as expected.
|
Check out how to contribute in [`CONTRIBUTE.md`](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md).
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Check out how to contribute in [`CONTRIBUTE.md`](https://github.com/stnolting/neorv32/blob/master/CONTRIBUTING.md).
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:rocket: Check out the [quick links below](#Getting-Started) or directly jump to the
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:rocket: Check out the [quick links below](#Getting-Started) or directly jump to the
|
[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
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[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started
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setting up your NEORV32 setup!
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setting up your NEORV32 setup!
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### Project Key Features
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### Project Key Features
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- [x] all-in-one: [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework & Tooling](#Software-Framework-and-Tooling)
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- [x] all-in-one: [CPU](#NEORV32-CPU-Features) plus [Processor/SoC](#NEORV32-Processor-Features) plus [Software Framework & Tooling](#Software-Framework-and-Tooling)
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- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- [x] fully synchronous design, no latches, no gated clocks
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- [x] fully synchronous design, no latches, no gated clocks
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- [x] be as small as possible while being as RISC-V-compliant as possible – but with a reasonable size-performance trade-off:
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- [x] be as small as possible while being as RISC-V-compliant as possible – but with a reasonable size-performance trade-off:
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the processor (CPU _including_ privileged architecture) fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz
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the processor (CPU _including_ privileged architecture) fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz
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- [x] from zero to `printf("hello world!");` - completely open source and documented
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- [x] from zero to `printf("hello world!");` - completely open source and documented
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- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 2. NEORV32 Processor Features
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## 2. NEORV32 Processor Features
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|
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The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
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The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
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provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
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provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
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to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
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to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
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In-depth detailed information regarding the processor/SoC can be found in the :books:
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In-depth detailed information regarding the processor/SoC can be found in the :books:
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[online documentation - _"NEORV32 Processors (SoC)"_](https://stnolting.github.io/neorv32/#_neorv32_processor_soc).
|
[online documentation - _"NEORV32 Processors (SoC)"_](https://stnolting.github.io/neorv32/#_neorv32_processor_soc).
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**Memory**
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**Memory**
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|
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* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
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* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
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[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
|
[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
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cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
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cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
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* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface
|
* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface
|
* supports boot via UART or from external SPI flash
|
* supports boot via UART or from external SPI flash
|
|
|
**Timers**
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**Timers**
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|
|
* machine system timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
|
* machine system timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
|
* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
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* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
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|
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**IO**
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**IO**
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|
|
* standard serial interfaces
|
* standard serial interfaces
|
([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),
|
([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),
|
[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi),
|
[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi),
|
[TWI / I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi))
|
[TWI / I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi))
|
* general purpose [GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio) and
|
* general purpose [GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio) and
|
[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
|
[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
|
* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly drive _NeoPixel(TM)_ LEDs
|
* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly drive _NeoPixel(TM)_ LEDs
|
|
|
**SoC Connectivity and Integration**
|
**SoC Connectivity and Integration**
|
|
|
* 32-bit external bus interface, Wishbone b4 compatible
|
* 32-bit external bus interface, Wishbone b4 compatible
|
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
|
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
|
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
|
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd) for AXI4-Lite master interface
|
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM master interface
|
* [wrapper](https://github.com/stnolting/neorv32/blob/master/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd) for Avalon-MM master interface
|
* 32-bit stream link interface with up to 8 independent RX and TX links
|
* 32-bit stream link interface with up to 8 independent RX and TX links
|
([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
|
([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
|
* AXI4-Stream compatible
|
* AXI4-Stream compatible
|
* external interrupt controller with up to 32 channels
|
* external interrupt controller with up to 32 channels
|
([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
|
([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
for tightly-coupled custom co-processor extensions
|
for tightly-coupled custom co-processor extensions
|
|
|
**Advanced**
|
**Advanced**
|
|
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) via JTGA - implementing
|
the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
|
the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
|
and compatible with *OpenOCD* and *gdb*
|
and compatible with *OpenOCD* and *gdb*
|
|
* bus keeper to monitor processor-internal bus transactions ([BUSKEEPER](https://stnolting.github.io/neorv32/#_internal_bus_monitor_buskeeper))
|
|
|
:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**.
|
:information_source: It is recommended to use the processor setup even if you want to **use the CPU in stand-alone mode**.
|
Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that
|
Just disable all optional processor-internal modules via the according generics and you will get a "CPU wrapper" that
|
provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use
|
provides a minimal CPU environment and an external memory interface (like AXI4). This minimal setup allows to further use
|
the default bootloader and software framework. From this base you can start building your own processor system.
|
the default bootloader and software framework. From this base you can start building your own processor system.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### FPGA Implementation Results - Processor
|
### FPGA Implementation Results - Processor
|
|
|
The hardware resources used by a specific processor setup is defined by the implemented CPU extensions
|
The hardware resources used by a specific processor setup is defined by the implemented CPU extensions
|
([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
|
([see below](#FPGA-Implementation-Results---CPU)), the configuration of the peripheral modules and some "glue logic".
|
Section [_"FPGA Implementation Results - Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules)
|
Section [_"FPGA Implementation Results - Processor Modules"_](https://stnolting.github.io/neorv32/#_processor_modules)
|
of the online datasheet shows the resource utilization of each optional processor module to allow an
|
of the online datasheet shows the resource utilization of each optional processor module to allow an
|
estimation of the actual setup's hardware requirements.
|
estimation of the actual setup's hardware requirements.
|
|
|
:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
|
:information_source: The [`setups`](https://github.com/stnolting/neorv32/tree/master/setups) folder provides exemplary FPGA
|
setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
|
setups targeting various FPGA boards and toolchains. These setups also provide resource utilization reports for different
|
SoC configurations
|
SoC configurations
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## 3. NEORV32 CPU Features
|
## 3. NEORV32 CPU Features
|
|
|
:books: In-depth detailed information regarding the CPU can be found in the
|
:books: In-depth detailed information regarding the CPU can be found in the
|
[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
[online documentation - _"NEORV32 Central Processing Unit"_](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu).
|
|
|
The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
|
The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
|
implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the
|
implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
|
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
|
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
|
(see [`sim/README`](sim/README.md)).
|
(see [`sim/README`](sim/README.md)).
|
|
|
The core implements a little-endian Von-Neumann architecture using two pipeline stages, where each stage can operate in a multi-cycle processing
|
The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
|
scheme. The CPU supports three privilege levels (`machine` and optional `user` and `debug_mode`), the three standard RISC-V machine
|
However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction execution) can work independently to increase performance.
|
|
Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
|
interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
|
interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
|
It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
|
It also supports **all** standard RISC-V exceptions (instruction/load/store misaligned address & bus access fault, illegal
|
instruction, breakpoint, environment calls). See :books: [_"Full Virtualization"_](https://stnolting.github.io/neorv32/#_full_virtualization)
|
instruction, breakpoint, environment calls).
|
for more information.
|
|
|
|
|
|
### Available ISA Extensions
|
### Available ISA Extensions
|
|
|
Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
|
Currently, the following _optional_ RISC-V-compatible ISA extensions are implemented (linked to the according
|
documentation section). Note that the `X` extension is always enabled.
|
documentation section). Note that the `X` extension is always enabled.
|
|
|
**RV32
|
**RV32
|
[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
|
[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
|
[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
|
[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
|
[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
|
[[`A`](https://stnolting.github.io/neorv32/#_a_atomic_memory_access)]
|
|
[[`B`](https://stnolting.github.io/neorv32/#_b_bit_manipulation_operations)]
|
[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
|
[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
|
[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
|
[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
|
[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
|
[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
|
[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
|
[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
|
[[`Zbb`](https://stnolting.github.io/neorv32/#_zbb_basic_bit_manipulation_operations)]
|
|
[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
|
[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
|
[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
|
[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
|
|
[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
|
|
[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
|
[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
|
[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
|
[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
|
[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
|
[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
|
[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
|
[[`HPM`](https://stnolting.github.io/neorv32/#_hpm_hardware_performance_monitors)]
|
|
[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
|
[[`DEBUG`](https://stnolting.github.io/neorv32/#_cpu_debug_mode)]**
|
|
|
:warning: The `Zbb`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
|
:warning: The `B`, `Zfinx` and `Zmmul` RISC-V extensions are frozen but not officially ratified yet. Hence, there is no
|
upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic_ libraries for these extensions.
|
upstream gcc support. To circumvent this, the NEORV32 software framework provides _intrinsic_ libraries for these extensions.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### FPGA Implementation Results - CPU
|
### FPGA Implementation Results - CPU
|
|
|
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
|
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
|
using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing information is derived
|
using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing information is derived
|
from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
|
from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
|
|
|
Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|
|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
|
|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
|
| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
|
| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
|
|
|
:information_source: An incremental list of CPU extension's hardware utilization can found in
|
:information_source: An incremental list of CPU extension's hardware utilization can found in
|
[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
|
[online documentation - _"FPGA Implementation Results - CPU"_](https://stnolting.github.io/neorv32/#_cpu).
|
|
|
:information_source: The CPU provides options to further reduce the footprint (for example by constraining
|
:information_source: The CPU provides options to further reduce the footprint (for example by constraining
|
the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
|
the CPU-internal counters). See the [online data](https://stnolting.github.io/neorv32) sheet for more information.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### Performance
|
### Performance
|
|
|
The NEORV32 CPU is based on a two-stages pipelined architecture. Since both stage use a multi-cycle processing scheme,
|
The NEORV32 CPU is based on a two-stages pipelined architecture. Since both stage use a multi-cycle processing scheme,
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
|
each instruction requires several clock cycles to execute (2 cycles for ALU operations, up to 40 cycles for divisions).
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
|
available CPU extensions.
|
available CPU extensions.
|
|
|
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
|
The following table shows the performance results (relative CoreMark score and average cycles per instruction) for
|
_exemplary_ CPU configuration running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
|
_exemplary_ CPU configuration running 2000 iterations of the [CoreMark CPU benchmark](https://www.eembc.org/coremark).
|
The source files are available in [`sw/example/coremark`](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
|
The source files are available in [`sw/example/coremark`](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark).
|
|
|
:information_source: A _simple_ port of the **Dhrystone** benchmark is also available:
|
:information_source: A _simple_ port of the **Dhrystone** benchmark is also available:
|
[`sw/example/dhrystone`](https://github.com/stnolting/neorv32/blob/master/sw/example/dhrystone)
|
[`sw/example/dhrystone`](https://github.com/stnolting/neorv32/blob/master/sw/example/dhrystone)
|
|
|
~~~
|
~~~
|
**CoreMark Setup**
|
**CoreMark Setup**
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
Compiler flags: default, see makefile; optimization -O3
|
Compiler flags: default, see makefile; optimization -O3
|
~~~
|
~~~
|
|
|
Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
Results generated for hardware version [`1.5.7.10`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
|
|
| CPU Configuration | CoreMark Score | CoreMarks/MHz | Average CPI |
|
| CPU Configuration | CoreMark Score | CoreMarks/MHz | Average CPI |
|
|:-----------------------------------------------|:--------------:|:-------------:|:-----------:|
|
|:------------------------------------------------|:--------------:|:-------------:|:-----------:|
|
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
|
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
|
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
|
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
|
| _performance_(`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
|
| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
|
|
|
:information_source: More information regarding the CPU performance can be found in the
|
:information_source: More information regarding the CPU performance can be found in the
|
[online documentation - _"CPU Performance"_](https://stnolting.github.io/neorv32/#_cpu_performance).
|
[online documentation - _"CPU Performance"_](https://stnolting.github.io/neorv32/#_cpu_performance).
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## 4. Software Framework and Tooling
|
## 4. Software Framework and Tooling
|
|
|
:books: In-depth detailed information regarding the software framework can be found in the
|
:books: In-depth detailed information regarding the software framework can be found in the
|
[online documentation - _"Software Framework"_](https://stnolting.github.io/neorv32/#_software_framework).
|
[online documentation - _"Software Framework"_](https://stnolting.github.io/neorv32/#_software_framework).
|
|
|
* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
|
* [core libraries](https://github.com/stnolting/neorv32/tree/master/sw/lib) for high-level usage of the provided functions and peripherals
|
* application compilation based on GNU makefiles
|
* application compilation based on GNU makefiles
|
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
|
* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
|
* bootloader with UART interface console
|
* bootloader with UART interface console
|
* runtime environment for handling traps
|
* runtime environment for handling traps
|
* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including
|
* several [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) to get started including
|
[CoreMark](https://github.com/stnolting/neorv32/tree/master/sw/example/coremark),
|
[CoreMark](https://github.com/stnolting/neorv32/tree/master/sw/example/coremark),
|
[FreeRTOS](https://github.com/stnolting/neorv32/tree/master/sw/example/demo_freeRTOS) and
|
[FreeRTOS](https://github.com/stnolting/neorv32/tree/master/sw/example/demo_freeRTOS) and
|
[Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life)
|
[Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life)
|
* `doxygen`-based documentation, available on :books: [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
|
* `doxygen`-based documentation, available on :books: [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
|
* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be
|
* supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be
|
developed and debugged with open source tooling
|
developed and debugged with open source tooling
|
* [continuous integration](https://github.com/stnolting/neorv32/actions) :octocat: is available for:
|
* [continuous integration](https://github.com/stnolting/neorv32/actions) :octocat: is available for:
|
* allowing users to see the expected execution/output of the tools
|
* allowing users to see the expected execution/output of the tools
|
* ensuring specification compliance
|
* ensuring specification compliance
|
* catching regressions
|
* catching regressions
|
* providing ready-to-use and up-to-date bitstreams and documentation
|
* providing ready-to-use and up-to-date bitstreams and documentation
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## 5. Getting Started
|
## 5. Getting Started
|
|
|
This overview provides some *quick links* to the most important sections of the
|
This overview provides some *quick links* to the most important sections of the
|
[online Data Sheet](https://stnolting.github.io/neorv32) and the
|
[online Data Sheet](https://stnolting.github.io/neorv32) and the
|
[online User Guide](https://stnolting.github.io/neorv32/ug).
|
[online User Guide](https://stnolting.github.io/neorv32/ug).
|
|
|
### :electric_plug: Hardware Overview
|
### :electric_plug: Hardware Overview
|
|
|
* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why, how come, what for
|
* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why, how come, what for
|
|
|
* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
|
* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
|
* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
|
* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
|
* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
|
* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
|
* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configuration
|
* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configuration
|
* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
|
* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - available IO/peripheral modules and memories
|
* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
|
* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - online & in-system debugging of the processor via JTAG
|
|
|
* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU
|
* [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the CPU
|
* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
|
* [RISC-V compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs. and what is not
|
|
* [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - hardware execution safety
|
* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
|
* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available RISC-V ISA extensions
|
* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
|
* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
|
* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
|
* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
|
|
|
### :floppy_disk: Software Overview
|
### :floppy_disk: Software Overview
|
|
|
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
|
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
|
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation
|
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - `doxygen`-based documentation
|
* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable
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* [Application Makefiles](https://stnolting.github.io/neorv32/#_application_makefile) - turning your application into an executable
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* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
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* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
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### :rocket: User Guides (see full [User Guide](https://stnolting.github.io/neorv32/ug/))
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### :rocket: User Guides (see full [User Guide](https://stnolting.github.io/neorv32/ug/))
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* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_toolchain_setup) - install and setup RISC-V gcc
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* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_toolchain_setup) - install and setup RISC-V gcc
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* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
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* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 EDA project
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* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
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* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
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* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
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* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
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* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
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* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
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* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
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* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
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* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware
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* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware
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* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
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* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
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* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
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* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
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### :copyright: Legal
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### :copyright: Legal
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* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, proprietary notice, ...
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* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, proprietary notice, ...
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* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information (DOI)
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* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information (DOI)
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* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint (:de:)
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* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint (:de:)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## Acknowledgements
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## Acknowledgements
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**A big shoutout to all [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
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**A big shoutout to all [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project! :heart:**
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
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Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
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Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
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--------
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--------
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Made with :coffee: in Hanover, Germany :eu:
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Made with :coffee: in Hanover, Germany :eu:
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