# [The NEORV32 Processor](https://github.com/stnolting/neorv32)
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# [The NEORV32 Processor](https://github.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://travis-ci.com/stnolting/neorv32)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/issues)
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[](https://github.com/stnolting/neorv32/issues)
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[](https://github.com/stnolting/neorv32/pulls)
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[](https://github.com/stnolting/neorv32/pulls)
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[](https://github.com/stnolting/neorv32/commits/master)
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[](https://github.com/stnolting/neorv32/commits/master)
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## Table of Content
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## Table of Content
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* [Introduction](#Introduction)
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* [Introduction](#Introduction)
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* [Features](#Features)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Performance](#Performance)
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* [Top Entity](#Top-Entity)
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* [Top Entity](#Top-Entity)
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* [**Getting Started**](#Getting-Started)
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* [**Getting Started**](#Getting-Started)
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* [Contact](#Contact)
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* [Contact](#Contact)
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* [Legal](#Legal)
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* [Legal](#Legal)
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## Introduction
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## Introduction
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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provided functions and peripherals, application makefiles and example programs. All software source files
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provided functions and peripherals, application makefiles and example programs. All software source files
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provide a doxygen-based documentary.
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provide a doxygen-based documentary.
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The project is intended to work "out of the box". Just synthesize the test setup from this project, upload
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The project is intended to work "out of the box". Just synthesize the test setup from this project, upload
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it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain)
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it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain)
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by yourself, you can also download [pre-compiled toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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by yourself, you can also download [pre-compiled toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Design Principles
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### Design Principles
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* From zero to main(): Completely open source and documented.
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* From zero to main(): Completely open source and documented.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Easy to use – working out of the box.
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* Easy to use – working out of the box.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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### Status
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr` *RISC-V compliance tests*.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
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#### Limitations to be fixed
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* No exception is triggered in `E`-mode when using registers above `x15` yet
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#### To-Do / Wish List
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension)
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- Implement `Zifence` extension
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- Implement co-processor for single-precision floating-point operations (`F` extension)
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- Implement user mode (`U` extension)
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- Make a 64-bit branch
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- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
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[RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test):
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[](https://travis-ci.com/stnolting/neorv32_riscv_compliance)
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## Features
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## Features
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### Processor Features
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### Processor Features
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M` and `Zicsr` extensions
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- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M` and `Zicsr` extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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- Small hardware footprint and high operating frequency
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- Customizable processor configuration
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- Highly customizable processor configuration
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional processor-internal data and instruction memories (DMEM/IMEM)
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- Optional internal bootloader with UART console and automatic SPI flash boot option
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- _Optional_ internal bootloader with UART console and automatic SPI flash boot option
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- Optional machine system timer (MTIME), RISC-V-compliant
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- _Optional_ machine system timer (MTIME), RISC-V-compliant
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- Optional universal asynchronous receiver and transmitter (UART)
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- _Optional_ universal asynchronous receiver and transmitter (UART)
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- Optional 8/16/24/32-bit serial peripheral interface master (SPI) with 8 dedicated chip select lines
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- _Optional_ 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
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- Optional two wire serial interface master (TWI), compatible to the I²C standard
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- _Optional_ two wire serial interface controller (TWI), compatible to the I²C standard
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- Optional general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
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- _Optional_ general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
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- Optional 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- _Optional_ 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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- Optional watchdog timer (WDT)
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- _Optional_ watchdog timer (WDT)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- _Optional_ PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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- Optional GARO-based true random number generator (TRNG)
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- _Optional_ GARO-based true random number generator (TRNG)
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- Optional core-local interrupt controller with 8 channels (CLIC)
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- _Optional_ core-local interrupt controller with 8 channels (CLIC)
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- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output)
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- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output)
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### CPU Features
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### CPU Features
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The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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**RV32I base instruction set** (`I` extension):
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**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Branches instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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**Compressed instructions** (`C` extension):
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**Compressed instructions** (`C` extension):
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* Branches instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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* Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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**Embedded CPU version** (`E` extension):
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**Embedded CPU version** (`E` extension):
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* Reduced register file (only the 16 lowest registers)
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* Reduced register file (only the 16 lowest registers)
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* No performance counter CSRs
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* No performance counter CSRs
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**Integer multiplication and division hardware** (`M` extension):
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**Integer multiplication and division hardware** (`M` extension):
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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**Privileged architecture** (`Zicsr` extension):
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**Privileged architecture** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `ECALL` `EBREAK` `MRET` `WFI`
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* System instructions: `ECALL` `EBREAK` `MRET` `WFI`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mtinst` `mimpid` `mhartid`
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* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid`
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* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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* Supported exceptions and interrupts:
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* Supported exceptions and interrupts:
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* Misaligned instruction address
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* Misaligned instruction address
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* Instruction access fault
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* Instruction access fault
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* Illegal instruction
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* Illegal instruction
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* Breakpoint (via `ebreak` instruction)
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* Breakpoint (via `ebreak` instruction)
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* Load address misaligned
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* Load address misaligned
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* Load access fault
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* Load access fault
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* Store address misaligned
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* Store address misaligned
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* Store access fault
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* Store access fault
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* Environment call from M-mode (via `ecall` instruction)
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* Environment call from M-mode (via `ecall` instruction)
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* Machine software instrrupt
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* Machine software instrrupt
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* Machine timer interrupt (via `MTIME` unit)
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* Machine timer interrupt (via `MTIME` unit)
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* Machine external interrupt (via `CLIC` unit)
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* Machine external interrupt (via `CLIC` unit)
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**General**:
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**General**:
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* No hardware support of unaligned accesses - they will trigger and exception
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* No hardware support of unaligned accesses - they will trigger and exception
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution
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More information including a detailed list of the available CSRs can be found in
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More information including a detailed list of the available CSRs can be found in
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### To-Do / Wish List
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- No exception is triggered in `E`-mode when using reg >x15 yet
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension)
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- Implement `Zifence` extension
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- Implement co-processor for single-precision floating-point operations (`F` extension)
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- Implement user mode (`U` extension)
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- Make a 64-bit branch
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- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
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## FPGA Implementation Results
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## FPGA Implementation Results
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the processor's generics is assumed. No constraints were used.
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of the processor's generics is assumed. No constraints were used.
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Results generated for hardware version: `1.0.0.0`
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Results generated for hardware version: `1.0.0.0`
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### CPU
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### CPU
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
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|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:|
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|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:|
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| `rv32i` | 1027 | 474 | 2048 | 0 (0%) | 111 MHz |
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| `rv32i` | 1027 | 474 | 2048 | 0 (0%) | 111 MHz |
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| `rv32i` + `Zicsr` | 1721 | 868 | 2048 | 0 (0%) | 104 MHz |
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| `rv32i` + `Zicsr` | 1721 | 868 | 2048 | 0 (0%) | 104 MHz |
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| `rv32im` + `Zicsr` | 2298 | 1115 | 2048 | 0 (0%) | 103 MHz |
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| `rv32im` + `Zicsr` | 2298 | 1115 | 2048 | 0 (0%) | 103 MHz |
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| `rv32imc` + `Zicsr` | 2557 | 1138 | 2048 | 0 (0%) | 103 MHz |
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| `rv32imc` + `Zicsr` | 2557 | 1138 | 2048 | 0 (0%) | 103 MHz |
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| `rv32emc` + `Zicsr` | 2342 | 1005 | 1024 | 0 (0%) | 100 MHz |
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| `rv32emc` + `Zicsr` | 2342 | 1005 | 1024 | 0 (0%) | 100 MHz |
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### Processor-Internal Peripherals and Memories
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### Processor-Internal Peripherals and Memories
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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| Module | Description | LEs | FFs | Memory bits | DSPs |
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|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
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| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 |
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| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
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| DEVNULL | Dummy device | 3 | 1 | 0 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
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| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 |
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| GPIO | General purpose input/output ports | 38 | 33 | 0 | 0 |
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| GPIO | General purpose input/output ports | 38 | 33 | 0 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
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| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 |
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| MTIME | Machine system timer | 270 | 167 | 0 | 0 |
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| MTIME | Machine system timer | 270 | 167 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 |
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| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 |
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| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 |
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| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 |
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| TRNG | True random number generator | 104 | 93 | 0 | 0 |
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| TRNG | True random number generator | 104 | 93 | 0 | 0 |
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| TWI | Two-wire interface | 78 | 44 | 0 | 0 |
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| TWI | Two-wire interface | 78 | 44 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 |
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| WDT | Watchdog timer | 57 | 45 | 0 | 0 |
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| WDT | Watchdog timer | 57 | 45 | 0 | 0 |
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### CPU + Peripheral
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### CPU + Peripheral
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The following table shows the implementation results for an _Intel Cyclone IV EP4CE22F17C6N_ FPGA.
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The following table shows the implementation results for an _Intel Cyclone IV EP4CE22F17C6N_ FPGA.
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The design was synthesized using Intel Quartus Prime Lite 19.1 (“balanced implementation”).
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The design was synthesized using Intel Quartus Prime Lite 19.1 (“balanced implementation”).
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IMEM uses 16kB and DMEM uses 8kB memory space.
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IMEM uses 16kB and DMEM uses 8kB memory space.
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| CPU Configuration | LEs | REGs | DSPs | Memory Bits | f_max |
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| CPU Configuration | LEs | REGs | DSPs | Memory Bits | f_max |
|
|:--------------------|:----------:|:---------:|:------:|:------------:|:-------:|
|
|:--------------------|:----------:|:---------:|:------:|:------------:|:-------:|
|
| `rv32imc` + `Zicsr` | 3724 (17%) | 1899 (9%) | 0 (0%) | 231424 (38%) | 103 MHz |
|
| `rv32imc` + `Zicsr` | 3724 (17%) | 1899 (9%) | 0 (0%) | 231424 (38%) | 103 MHz |
|
|
|
|
|
### Lattice iCE40 UltraPlus 5k
|
### Lattice iCE40 UltraPlus 5k
|
|
|
The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
|
The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
|
The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
|
The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
|
instruction and data memories (each 64kB) based on SPRAM primitives. The FPGA-specific memory components can be found in the
|
instruction and data memories (each 64kB) based on SPRAM primitives. The FPGA-specific memory components can be found in the
|
[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
|
[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
|
|
|
Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency
|
Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency
|
is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz.
|
is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz.
|
|
|
| CPU Configuration | LUTs | REGs | DSPs | SPRAM | EBR | f |
|
| CPU Configuration | LUTs | REGs | DSPs | SPRAM | EBR | f |
|
|:--------------------|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
|
|:--------------------|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
|
| `rv32imc` + `Zicsr` | 4985 (94%) | 1982 (38%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
|
| `rv32imc` + `Zicsr` | 4985 (94%) | 1982 (38%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
|
|
|
|
|
## Performance
|
## Performance
|
|
|
### CoreMark Benchmark
|
### CoreMark Benchmark
|
|
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
|
|
Results generated for hardware version: `1.0.0.0`
|
Results generated for hardware version: `1.0.0.0`
|
|
|
~~~
|
~~~
|
**Configuration**
|
**Configuration**
|
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock
|
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
CPU extensions: `rv32i` or `rv32im` or `rv32imc`
|
CPU extensions: `rv32i` or `rv32im` or `rv32imc`
|
Used peripherals: MTIME for time measurement, UART for printing the results
|
Used peripherals: MTIME for time measurement, UART for printing the results
|
~~~
|
~~~
|
|
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ |
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ |
|
|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:|
|
|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:|
|
| `rv32i` | `-Os` | 18 044 bytes | 21.98 | 0.21 |
|
| `rv32i` | `-Os` | 18 044 bytes | 21.98 | 0.21 |
|
| `rv32i` | `-O2` | 20 388 bytes | 25 | 0.25 |
|
| `rv32i` | `-O2` | 20 388 bytes | 25 | 0.25 |
|
| `rv32im` | `-Os` | 16 980 bytes | 40 | 0.40 |
|
| `rv32im` | `-Os` | 16 980 bytes | 40 | 0.40 |
|
| `rv32im` | `-O2` | 19 436 bytes | 51.28 | 0.51 |
|
| `rv32im` | `-O2` | 19 436 bytes | 51.28 | 0.51 |
|
| `rv32imc` | `-Os` | 13 076 bytes | 39.22 | 0.39 |
|
| `rv32imc` | `-Os` | 13 076 bytes | 39.22 | 0.39 |
|
| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 |
|
| `rv32imc` | `-O2` | 15 208 bytes | 50 | 0.50 |
|
|
|
|
|
### Instruction Cycles
|
### Instruction Cycles
|
|
|
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of several
|
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of several
|
consecutive micro operations. Hence, each instruction requires several clock cycles to execute. The average CPI
|
consecutive micro operations. Hence, each instruction requires several clock cycles to execute. The average CPI
|
(cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
(cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
CPU extensions.
|
CPU extensions.
|
|
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
`M` extension use a bit-serial approach and require several cycles for completion.
|
`M` extension use a bit-serial approach and require several cycles for completion.
|
|
|
The following table shows the performance results for successfully running 2000 CoreMark
|
The following table shows the performance results for successfully running 2000 CoreMark
|
iterations. The average CPI is computed by dividing the total number of required clock cycles (all of CoreMark
|
iterations. The average CPI is computed by dividing the total number of required clock cycles (all of CoreMark
|
– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
|
– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
|
were generated using optimization `-O2`.
|
were generated using optimization `-O2`.
|
|
|
| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI |
|
| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI |
|
|:------------------------|----------------------:|----------------------:|:-----------:|
|
|:------------------------|----------------------:|----------------------:|:-----------:|
|
| `rv32i` | 19 355 607 369 | 2 995 064 579 | 6.5 |
|
| `rv32i` | 19 355 607 369 | 2 995 064 579 | 6.5 |
|
| `rv32im` | 5 809 384 583 | 867 377 291 | 6.7 |
|
| `rv32im` | 5 809 384 583 | 867 377 291 | 6.7 |
|
| `rv32imc` | 5 560 220 723 | 825 898 407 | 6.7 |
|
| `rv32imc` | 5 560 220 723 | 825 898 407 | 6.7 |
|
|
|
|
|
|
|
## Top Entity
|
## Top Entity
|
|
|
The top entity of the processor is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
|
The top entity of the processor is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
(except for the TWI signals, which are of type *std_logic*).
|
(except for the TWI signals, which are of type *std_logic*).
|
|
|
Use the generics to configure the processor according to your needs. Each generics is initilized with the default configuration.
|
Use the generics to configure the processor according to your needs. Each generics is initilized with the default configuration.
|
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
```vhdl
|
```vhdl
|
entity neorv32_top is
|
entity neorv32_top is
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
-- Memory configuration: Instruction memory --
|
-- Memory configuration: Instruction memory --
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
-- Memory configuration: Data memory --
|
-- Memory configuration: Data memory --
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
-- Memory configuration: External memory interface --
|
-- Memory configuration: External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout (>=1)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout (>=1)
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- Wishbone bus interface (available if MEM_EXT_USE = true) --
|
-- Wishbone bus interface (available if MEM_EXT_USE = true) --
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
-- GPIO (available if IO_GPIO_USE = true) --
|
-- GPIO (available if IO_GPIO_USE = true) --
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
-- UART (available if IO_UART_USE = true) --
|
-- UART (available if IO_UART_USE = true) --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
-- SPI (available if IO_SPI_USE = true) --
|
-- SPI (available if IO_SPI_USE = true) --
|
spi_sck_o : out std_ulogic; -- serial clock line
|
spi_sck_o : out std_ulogic; -- serial clock line
|
spi_sdo_o : out std_ulogic; -- serial data line out
|
spi_sdo_o : out std_ulogic; -- serial data line out
|
spi_sdi_i : in std_ulogic := '0'; -- serial data line in
|
spi_sdi_i : in std_ulogic := '0'; -- serial data line in
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- TWI (available if IO_TWI_USE = true) --
|
-- TWI (available if IO_TWI_USE = true) --
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
-- PWM (available if IO_PWM_USE = true) --
|
-- PWM (available if IO_PWM_USE = true) --
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
-- Interrupts (available if IO_CLIC_USE = true) --
|
-- Interrupts (available if IO_CLIC_USE = true) --
|
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
|
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
|
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
|
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
|
);
|
);
|
end neorv32_top;
|
end neorv32_top;
|
```
|
```
|
|
|
|
|
|
|
## Getting Started
|
## Getting Started
|
|
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
|
|
[ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
|
[ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
|
|
|
|
|
### Building the Toolchain
|
### Building the Toolchain
|
|
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
|
|
To build the toolchain by yourself, get the sources from the official [RISCV-GNU-TOOLCHAIN](https://github.com/riscv/riscv-gnu-toolchain) github page:
|
To build the toolchain by yourself, get the sources from the official [RISCV-GNU-TOOLCHAIN](https://github.com/riscv/riscv-gnu-toolchain) github page:
|
|
|
$ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
|
$ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
|
|
|
Download and install the prerequisite standard packages:
|
Download and install the prerequisite standard packages:
|
|
|
$ sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
|
$ sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
|
|
|
To build the Linux cross-compiler, pick an install path. If you choose, say, `/opt/riscv`, then add `/opt/riscv/bin` to your `PATH` environment variable.
|
To build the Linux cross-compiler, pick an install path. If you choose, say, `/opt/riscv`, then add `/opt/riscv/bin` to your `PATH` environment variable.
|
|
|
$ export PATH:$PATH:/opt/riscv/bin
|
$ export PATH:$PATH:/opt/riscv/bin
|
|
|
Then, simply run the following commands in the RISC-V GNU toolchain source folder (for the `rv32i` toolchain):
|
Then, simply run the following commands in the RISC-V GNU toolchain source folder (for the `rv32i` toolchain):
|
|
|
riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i –with-abi=ilp32
|
riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i –with-abi=ilp32
|
riscv-gnu-toolchain$ make
|
riscv-gnu-toolchain$ make
|
|
|
After a while (hours!) you will get `riscv32-unknown-elf-gcc` and all of its friends in your `/opt/riscv/bin` folder.
|
After a while (hours!) you will get `riscv32-unknown-elf-gcc` and all of its friends in your `/opt/riscv/bin` folder.
|
|
|
|
|
### Using a Prebuilt Toolchain
|
### Using a Prebuilt Toolchain
|
|
|
Alternatively, you can download a prebuilt toolchain. I have uploaded the toolchain I am using to GitHub. This toolchain
|
Alternatively, you can download a prebuilt toolchain. I have uploaded the toolchain I am using to GitHub. This toolchain
|
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice:
|
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice:
|
|
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
|
|
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### Dowload the Project and Create a Hardware Project
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### Dowload the Project and Create a Hardware Project
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|
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Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
|
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
|
`git` from the command line (suggested for easy project updates via `git pull`):
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`git` from the command line (suggested for easy project updates via `git pull`):
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|
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$ git clone https://github.com/stnolting/neorv32.git
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$ git clone https://github.com/stnolting/neorv32.git
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|
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Create a new HW project with your FPGA design tool of choice. Add all files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
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Create a new HW project with your FPGA design tool of choice. Add all files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
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folder to this project and add them to a **new library** called `neorv32`.
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folder to this project and add them to a **new library** called `neorv32`.
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|
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You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in you own project, or you
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in you own project, or you
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. This test
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can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. This test
|
setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are
|
setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are
|
propagated:
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propagated:
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```vhdl
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```vhdl
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entity neorv32_test_setup is
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entity neorv32_test_setup is
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port (
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port (
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-- Global control --
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-- Global control --
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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-- GPIO --
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-- GPIO --
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gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
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gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
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-- UART --
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-- UART --
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uart_txd_o : out std_ulogic; -- UART send data
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uart_txd_o : out std_ulogic; -- UART send data
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uart_rxd_i : in std_ulogic := '0' -- UART receive data
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uart_rxd_i : in std_ulogic := '0' -- UART receive data
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);
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);
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end neorv32_test_setup;
|
end neorv32_test_setup;
|
```
|
```
|
|
|
This test setup is intended as quick and easy "hello world" test setup to get into the NEORV32.
|
This test setup is intended as quick and easy "hello world" test setup to get into the NEORV32.
|
|
|
|
|
### Compiling and Uploading One of the Example Projects
|
### Compiling and Uploading One of the Example Projects
|
|
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain, navigate to an example project like
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain, navigate to an example project like
|
`sw/example/blink_led` and run:
|
`sw/example/blink_led` and run:
|
|
|
neorv32/sw/example/blink_led$ make check
|
neorv32/sw/example/blink_led$ make check
|
|
|
The NEORV32 project includes some example programs from which you can start your own application:
|
The NEORV32 project includes some example programs from which you can start your own application:
|
[SW example projects](https://github.com/stnolting/neorv32/tree/master/sw/example)
|
[SW example projects](https://github.com/stnolting/neorv32/tree/master/sw/example)
|
|
|
Simply compile one of these projects. This will create a NEORV32 executable `neorv32_exe.bin` in the same folder.
|
Simply compile one of these projects. This will create a NEORV32 executable `neorv32_exe.bin` in the same folder.
|
|
|
neorv32/sw/example/blink_led$ make clean_all compile
|
neorv32/sw/example/blink_led$ make clean_all compile
|
|
|
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
|
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
|
uses the following default UART configuration:
|
uses the following default UART configuration:
|
|
|
- 19200 Baud
|
- 19200 Baud
|
- 8 data bits
|
- 8 data bits
|
- 1 stop bit
|
- 1 stop bit
|
- No parity bits
|
- No parity bits
|
- No transmission / flow control protocol (raw bytes only)
|
- No transmission / flow control protocol (raw bytes only)
|
- Newline on `\r\n` (carriage return & newline)
|
- Newline on `\r\n` (carriage return & newline)
|
|
|
Use the bootloader console to upload and execute your application image.
|
Use the bootloader console to upload and execute your application image.
|
|
|
Going further: Take a look at the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
Going further: Take a look at the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
|
|
|
|
|
|
## Contact
|
## Contact
|
|
|
If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kind of feedback, open a
|
If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kind of feedback, open a
|
[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line:
|
[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line:
|
|
|
stnolting@gmail.com
|
stnolting@gmail.com
|
|
|
|
|
|
|
## Citation
|
## Citation
|
|
|
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
|
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
|
|
|
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
|
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
|
|
|
|
|
|
|
## Legal
|
## Legal
|
|
|
This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
|
This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
|
Other implied/used projects might have different licensing - see their documentation to get more information.
|
Other implied/used projects might have different licensing - see their documentation to get more information.
|
|
|
**BSD 3-Clause License**
|
**BSD 3-Clause License**
|
|
|
Copyright (c) 2020, Stephan Nolting. All rights reserved.
|
Copyright (c) 2020, Stephan Nolting. All rights reserved.
|
|
|
Redistribution and use in source and binary forms, with or without modification, are
|
Redistribution and use in source and binary forms, with or without modification, are
|
permitted provided that the following conditions are met:
|
permitted provided that the following conditions are met:
|
|
|
1. Redistributions of source code must retain the above copyright notice, this list of
|
1. Redistributions of source code must retain the above copyright notice, this list of
|
conditions and the following disclaimer.
|
conditions and the following disclaimer.
|
2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
conditions and the following disclaimer in the documentation and/or other materials
|
conditions and the following disclaimer in the documentation and/or other materials
|
provided with the distribution.
|
provided with the distribution.
|
3. Neither the name of the copyright holder nor the names of its contributors may be used to
|
3. Neither the name of the copyright holder nor the names of its contributors may be used to
|
endorse or promote products derived from this software without specific prior written
|
endorse or promote products derived from this software without specific prior written
|
permission.
|
permission.
|
|
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
|
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
OF THE POSSIBILITY OF SUCH DAMAGE.
|
OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
"Windows" is a trademark of Microsoft Corporation.
|
"Windows" is a trademark of Microsoft Corporation.
|
|
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
|
|
"Cyclone", "Quartus Prime" and "Avalon Bus" are trademarks of Intel Corporation.
|
"Cyclone", "Quartus Prime" and "Avalon Bus" are trademarks of Intel Corporation.
|
|
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
|
|
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
|
|
|
|
|
[](https://travis-ci.com/stnolting/neorv32)
|
[](https://travis-ci.com/stnolting/neorv32)
|
|
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
|
|
|
|
|
|
|
|
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
|
|
|
|
|
Made with :coffee: in Hannover, Germany.
|
Made with :coffee: in Hannover, Germany.
|
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|
