Subversion Repositories neorv32

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== Overview

== Overview

The NEORV32footnote:[Pronounced "neo-R-V-thirty-two" or "neo-risc-five-thirty-two" in its long form.] is an open-source

The NEORV32footnote:[Pronounced "neo-R-V-thirty-two" or "neo-risc-five-thirty-two" in its long form.] is an open-source

RISC-V compatible processor system that is intended as *ready-to-go* auxiliary processor within a larger SoC

RISC-V compatible processor system that is intended as *ready-to-go* auxiliary processor within a larger SoC

designs or as stand-alone custom / customizable microcontroller.

designs or as stand-alone custom / customizable microcontroller.

The system is highly configurable and provides optional common peripherals like embedded memories,

The system is highly configurable and provides optional common peripherals like embedded memories,

timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like

timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like

memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb

memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb

compatible on-chip debugger accessible via JTAG.

compatible on-chip debugger accessible via JTAG.

Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.

Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.

Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions

Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions

are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.

are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.

The software framework of the processor comes with application makefiles, software libraries for all CPU

The software framework of the processor comes with application makefiles, software libraries for all CPU

and processor features, a bootloader, a runtime environment and several example programs - including a port

and processor features, a bootloader, a runtime environment and several example programs - including a port

of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as

of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as

default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).

default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).

Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**

Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**

that provides hands-on tutorials to get you started.

that provides hands-on tutorials to get you started.

**Structure**

**Structure**

[start=2]

[start=2]

. <<_neorv32_processor_soc>>

. <<_neorv32_processor_soc>>

. <<_neorv32_central_processing_unit_cpu>>

. <<_neorv32_central_processing_unit_cpu>>

. <<_software_framework>>

. <<_software_framework>>

. <<_on_chip_debugger_ocd>>

. <<_on_chip_debugger_ocd>>

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=== Project Key Features

=== Project Key Features

* open-source and documented; including user guides to get started

* open-source and documented; including user guides to get started

* completely described in behavioral, platform-independent VHDL (yet platform-optimized modules are provided)

* completely described in behavioral, platform-independent VHDL (yet platform-optimized modules are provided)

* fully synchronous design, no latches, no gated clocks

* fully synchronous design, no latches, no gated clocks

* small hardware footprint and high operating frequency for easy integration

* small hardware footprint and high operating frequency for easy integration

* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU

* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU

** RISC-V compatibility: passes the official architecture tests

** RISC-V compatibility: passes the official architecture tests

** base architecture + privileged architecture (optional) + ISA extensions (optional)

** base architecture + privileged architecture (optional) + ISA extensions (optional)

** option to add custom RISC-V instructions (as custom ISA extension)

** option to add custom RISC-V instructions (as custom ISA extension)

** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)

** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)

** aims to support <<_full_virtualization>> capabilities (CPU _and_ SoC) to increase execution safety

** aims to support <<_full_virtualization>> capabilities (CPU _and_ SoC) to increase execution safety

** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]

** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]

* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system

* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system

** based on the NEORV32 CPU

** based on the NEORV32 CPU

** optional serial interfaces (UARTs, TWI, SPI)

** optional serial interfaces (UARTs, TWI, SPI)

** optional timers and counters (WDT, MTIME)

** optional timers and counters (WDT, MTIME)

** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface

** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface

** optional embedded memories / caches for data, instructions and bootloader

** optional embedded memories / caches for data, instructions and bootloader

** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity

** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity

** optional execute in place (XIP) module

** optional execute in place (XIP) module

** on-chip debugger compatible with OpenOCD and gdb including hardware trigger module

** on-chip debugger compatible with OpenOCD and gdb including hardware trigger module

* **Software framework**

* **Software framework**

** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles

** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles

** internal bootloader with serial user interface

** internal bootloader with serial user interface

** core libraries for high-level usage of the provided functions and peripherals

** core libraries for high-level usage of the provided functions and peripherals

** runtime environment and several example programs

** runtime environment and several example programs

** doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html

** doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html

** FreeRTOS port + demos available

** FreeRTOS port + demos available

[TIP]

[TIP]

For more in-depth details regarding the feature provided by he hardware see the according sections:

For more in-depth details regarding the feature provided by he hardware see the according sections:

<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.

<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.

**Extensibility and Customization**

**Extensibility and Customization**

The NEORV32 processor was designed to ease customization and extensibility and provides several options for adding

The NEORV32 processor was designed to ease customization and extensibility and provides several options for adding

application-specific custom hardware modules and accelerators. The three most common options for adding custom

application-specific custom hardware modules and accelerators. The three most common options for adding custom

on-chip modules are listed below.

on-chip modules are listed below.

* <<_processor_external_memory_interface_wishbone_axi4_lite>> for processor-external modules

* <<_processor_external_memory_interface_wishbone_axi4_lite>> for processor-external modules

* <<_custom_functions_subsystem_cfs>> for tightly-coupled processor-internal co-processors

* <<_custom_functions_subsystem_cfs>> for tightly-coupled processor-internal co-processors

* <<_custom_functions_unit_cfu>> for custom RISC-V instructions

* <<_custom_functions_unit_cfu>> for custom RISC-V instructions

[TIP]

[TIP]

A more detailed comparison of the extension/customization options can be found in section

A more detailed comparison of the extension/customization options can be found in section

https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding Custom Hardware Modules]

https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding Custom Hardware Modules]

of the user guide.

of the user guide.

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=== Project Folder Structure

=== Project Folder Structure

...................................

...................................

neorv32                - Project home folder

neorv32                - Project home folder

│

│

├docs                  - Project documentation

├docs                  - Project documentation

│├datasheet            - AsciiDoc sources for the NEORV32 data sheet

│├datasheet            - AsciiDoc sources for the NEORV32 data sheet

│├figures              - Figures and logos

│├figures              - Figures and logos

│├icons                - Misc. symbols

│├icons                - Misc. symbols

│├references           - Data sheets and RISC-V specs.

│├references           - Data sheets and RISC-V specs.

│└userguide            - AsciiDoc sources for the NEORV32 user guide

│└userguide            - AsciiDoc sources for the NEORV32 user guide

│

│

├rtl                   - VHDL sources

├rtl                   - VHDL sources

│├core                 - Core sources of the CPU & SoC

│├core                 - Core sources of the CPU & SoC

││└mem                 - SoC-internal memories (default architectures)

││└mem                 - SoC-internal memories (default architectures)

│├processor_templates  - Pre-configured SoC wrappers

│├processor_templates  - Pre-configured SoC wrappers

│├system_integration   - System wrappers for advanced connectivity

│├system_integration   - System wrappers for advanced connectivity

│└test_setups          - Minimal test setup "SoCs" used in the User Guide

│└test_setups          - Minimal test setup "SoCs" used in the User Guide

│

│

├sim                   - Simulation files (see User Guide)

├sim                   - Simulation files (see User Guide)

│

│

└sw                    - Software framework

└sw                    - Software framework

 ├bootloader           - Sources of the processor-internal bootloader

 ├bootloader           - Sources of the processor-internal bootloader

 ├common               - Linker script, crt0.S start-up code and central makefile

 ├common               - Linker script, crt0.S start-up code and central makefile

 ├example              - Various example programs

 ├example              - Various example programs

 │└...

 │└...

 ├lib                  - Processor core library

 ├lib                  - Processor core library

 │├include             - Header files (*.h)

 │├include             - Header files (*.h)

 │└source              - Source files (*.c)

 │└source              - Source files (*.c)

 ├image_gen            - Helper program to generate NEORV32 executables

 ├image_gen            - Helper program to generate NEORV32 executables

 ├isa-test

 ├isa-test

 │├riscv-arch-test     - RISC-V spec. compatibility test framework (submodule)

 │├riscv-arch-test     - RISC-V spec. compatibility test framework (submodule)

 │└port-neorv32        - Port files for the official RISC-V architecture tests

 │└port-neorv32        - Port files for the official RISC-V architecture tests

 ├ocd_firmware         - Source code for on-chip debugger's "park loop"

 ├ocd_firmware         - Source code for on-chip debugger's "park loop"

 ├openocd              - OpenOCD on-chip debugger configuration files

 ├openocd              - OpenOCD on-chip debugger configuration files

 └svd                  - Processor system view description file (CMSIS-SVD)

 └svd                  - Processor system view description file (CMSIS-SVD)

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=== VHDL File Hierarchy

=== VHDL File Hierarchy

All necessary VHDL hardware description files are located in the project's `rtl/core` folder. The top entity

All necessary VHDL hardware description files are located in the project's `rtl/core` folder. The top entity

of the entire processor including all the required configuration generics is **`neorv32_top.vhd`**.

of the entire processor including all the required configuration generics is **`neorv32_top.vhd`**.

[IMPORTANT]

[IMPORTANT]

All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional

All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional

files, like alternative top entities, can be assigned to any library.

files, like alternative top entities, can be assigned to any library.

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...................................

neorv32_top.vhd                  - NEORV32 Processor top entity

neorv32_top.vhd                  - NEORV32 Processor top entity

│

│

├neorv32_fifo.vhd                - General purpose FIFO component

├neorv32_fifo.vhd                - General purpose FIFO component

├neorv32_package.vhd             - Processor/CPU main VHDL package file

├neorv32_package.vhd             - Processor/CPU main VHDL package file

│

│

├neorv32_cpu.vhd                 - NEORV32 CPU top entity

├neorv32_cpu.vhd                 - NEORV32 CPU top entity

│├neorv32_cpu_alu.vhd            - Arithmetic/logic unit

│├neorv32_cpu_alu.vhd            - Arithmetic/logic unit

││├neorv32_cpu_cp_bitmanip.vhd   - Bit-manipulation co-processor (B ext.)

││├neorv32_cpu_cp_bitmanip.vhd   - Bit-manipulation co-processor (B ext.)

││├neorv32_cpu_cp_cfu.vhd        - Custom functions (instruction) co-processor (Zxcfu ext.)

││├neorv32_cpu_cp_cfu.vhd        - Custom functions (instruction) co-processor (Zxcfu ext.)

││├neorv32_cpu_cp_fpu.vhd        - Floating-point co-processor (Zfinx ext.)

││├neorv32_cpu_cp_fpu.vhd        - Floating-point co-processor (Zfinx ext.)

││├neorv32_cpu_cp_muldiv.vhd     - Mul/Div co-processor (M extension)

││├neorv32_cpu_cp_muldiv.vhd     - Mul/Div co-processor (M extension)

││└neorv32_cpu_cp_shifter.vhd    - Bit-shift co-processor

││└neorv32_cpu_cp_shifter.vhd    - Bit-shift co-processor

│├neorv32_cpu_bus.vhd            - Bus interface + physical memory protection

│├neorv32_cpu_bus.vhd            - Bus interface + physical memory protection

│├neorv32_cpu_control.vhd        - CPU control, exception/IRQ system and CSRs

│├neorv32_cpu_control.vhd        - CPU control, exception/IRQ system and CSRs

││└neorv32_cpu_decompressor.vhd  - Compressed instructions decoder

││└neorv32_cpu_decompressor.vhd  - Compressed instructions decoder

│└neorv32_cpu_regfile.vhd        - Data register file

│└neorv32_cpu_regfile.vhd        - Data register file

│

│

├neorv32_boot_rom.vhd            - Bootloader ROM

├neorv32_boot_rom.vhd            - Bootloader ROM

│└neorv32_bootloader_image.vhd   - Bootloader boot ROM memory image

│└neorv32_bootloader_image.vhd   - Bootloader boot ROM memory image

├neorv32_busswitch.vhd           - Processor bus switch for CPU buses (I&D)

├neorv32_busswitch.vhd           - Processor bus switch for CPU buses (I&D)

├neorv32_bus_keeper.vhd          - Processor-internal bus monitor

├neorv32_bus_keeper.vhd          - Processor-internal bus monitor

├neorv32_cfs.vhd                 - Custom functions subsystem

├neorv32_cfs.vhd                 - Custom functions subsystem

├neorv32_debug_dm.vhd            - on-chip debugger: debug module

├neorv32_debug_dm.vhd            - on-chip debugger: debug module

├neorv32_debug_dtm.vhd           - on-chip debugger: debug transfer module

├neorv32_debug_dtm.vhd           - on-chip debugger: debug transfer module

├neorv32_dmem.entity.vhd         - Processor-internal data memory (entity-only!)

├neorv32_dmem.entity.vhd         - Processor-internal data memory (entity-only!)

├neorv32_gpio.vhd                - General purpose input/output port unit

├neorv32_gpio.vhd                - General purpose input/output port unit

├neorv32_gptmr.vhd               - General purpose 32-bit timer

├neorv32_gptmr.vhd               - General purpose 32-bit timer

├neorv32_icache.vhd              - Processor-internal instruction cache

├neorv32_icache.vhd              - Processor-internal instruction cache

├neorv32_imem.entity.vhd         - Processor-internal instruction memory (entity-only!)

├neorv32_imem.entity.vhd         - Processor-internal instruction memory (entity-only!)

│└neor32_application_image.vhd   - IMEM application initialization image

│└neor32_application_image.vhd   - IMEM application initialization image

├neorv32_mtime.vhd               - Machine system timer

├neorv32_mtime.vhd               - Machine system timer

├neorv32_neoled.vhd              - NeoPixel (TM) compatible smart LED interface

├neorv32_neoled.vhd              - NeoPixel (TM) compatible smart LED interface

├neorv32_pwm.vhd                 - Pulse-width modulation controller

├neorv32_pwm.vhd                 - Pulse-width modulation controller

├neorv32_slink.vhd               - Stream link controller

├neorv32_slink.vhd               - Stream link controller

├neorv32_spi.vhd                 - Serial peripheral interface controller

├neorv32_spi.vhd                 - Serial peripheral interface controller

├neorv32_sysinfo.vhd             - System configuration information memory

├neorv32_sysinfo.vhd             - System configuration information memory

├neorv32_trng.vhd                - True random number generator

├neorv32_trng.vhd                - True random number generator

├neorv32_twi.vhd                 - Two wire serial interface controller

├neorv32_twi.vhd                 - Two wire serial interface controller

├neorv32_uart.vhd                - Universal async. receiver/transmitter

├neorv32_uart.vhd                - Universal async. receiver/transmitter

├neorv32_wdt.vhd                 - Watchdog timer

├neorv32_wdt.vhd                 - Watchdog timer

├neorv32_wishbone.vhd            - External (Wishbone) bus interface

├neorv32_wishbone.vhd            - External (Wishbone) bus interface

├neorv32_xip.vhd                 - Execute in place module

├neorv32_xip.vhd                 - Execute in place module

├neorv32_xirq.vhd                - External interrupt controller

├neorv32_xirq.vhd                - External interrupt controller

│

│

├mem/neorv32_dmem.default.vhd    - _Default_ data memory (architecture-only)

├mem/neorv32_dmem.default.vhd    - _Default_ data memory (architecture-only)

└mem/neorv32_imem.default.vhd    - _Default_ instruction memory (architecture-only)

└mem/neorv32_imem.default.vhd    - _Default_ instruction memory (architecture-only)

...................................

...................................

[NOTE]

[NOTE]

The processor-internal instruction and data memories (IMEM and DMEM) are split into two design files each:

The processor-internal instruction and data memories (IMEM and DMEM) are split into two design files each:

a plain entity definition (`neorv32_*mem.entity.vhd`) and the actual architecture definition

a plain entity definition (`neorv32_*mem.entity.vhd`) and the actual architecture definition

(`mem/neorv32_*mem.default.vhd`). The `*.default.vhd` architecture definitions from `rtl/core/mem` provide a _generic_ and

(`mem/neorv32_*mem.default.vhd`). The `*.default.vhd` architecture definitions from `rtl/core/mem` provide a _generic_ and

_platform independent_ memory design that (should) infers embedded memory blocks. You can replace/modify the architecture

_platform independent_ memory design that (should) infers embedded memory blocks. You can replace/modify the architecture

source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping

source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping

and/or timing.

and/or timing.

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=== FPGA Implementation Results

=== FPGA Implementation Results

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==== CPU

==== CPU

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| Top entity: | `rtl/core/neorv32_cpu.vhd`

| Top entity: | `rtl/core/neorv32_cpu.vhd`

| FPGA:       | Intel Cyclone IV E `EP4CE22F17C6`

| FPGA:       | Intel Cyclone IV E `EP4CE22F17C6`

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[TIP]

[TIP]

The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal

The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal

counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).

counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).

See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section

See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section

https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].

https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].

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| Top entity: | `rtl/core/neorv32_top.vhd`

| Top entity: | `rtl/core/neorv32_top.vhd`

| FPGA:       | Intel Cyclone IV E `EP4CE22F17C6`

| FPGA:       | Intel Cyclone IV E `EP4CE22F17C6`

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| Module        | Description                                           | LEs | FFs | MEM bits | DSPs

| Module        | Description                                           | LEs | FFs | MEM bits | DSPs

| TWI           | Two-wire interface                                    |  77 |  43 |        0 |    0

| TWI           | Two-wire interface                                    |  77 |  43 |        0 |    0

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==== Exemplary Setups

==== Exemplary Setups

Check out the `neorv32-setups` repository (@GitHub: https://github.com/stnolting/neorv32-setups),

Check out the `neorv32-setups` repository (@GitHub: https://github.com/stnolting/neorv32-setups),

which provides several demo setups for various FPGA boards and toolchains.

which provides several demo setups for various FPGA boards and toolchains.

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=== CPU Performance

=== CPU Performance

The performance of the NEORV32 was tested and evaluated using the https://www.eembc.org/coremark/[Core Mark CPU benchmark].

The performance of the NEORV32 was tested and evaluated using the https://www.eembc.org/coremark/[Core Mark CPU benchmark].

This benchmark focuses on testing the capabilities of the CPU core itself rather than the performance of the whole

This benchmark focuses on testing the capabilities of the CPU core itself rather than the performance of the whole

system. The according sources can be found in the `sw/example/coremark` folder.

system. The according sources can be found in the `sw/example/coremark` folder.

.Dhrystone

.Dhrystone

[TIP]

[TIP]

A _simple_ port of the Dhrystone benchmark is also available in `sw/example/dhrystone`.

A _simple_ port of the Dhrystone benchmark is also available in `sw/example/dhrystone`.

The resulting CoreMark score is defined as CoreMark iterations per second.

The resulting CoreMark score is defined as CoreMark iterations per second.

The execution time is determined via the RISC-V `[m]cycle[h]` CSRs. The relative CoreMark score is

The execution time is determined via the RISC-V `[m]cycle[h]` CSRs. The relative CoreMark score is

defined as CoreMark score divided by the CPU's clock frequency in MHz.

defined as CoreMark score divided by the CPU's clock frequency in MHz.

.Configuration

.Configuration

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| HW version:     | `1.5.7.10`

| HW version:     | `1.5.7.10`

| Hardware:       | 32kB int. IMEM, 16kB int. DMEM, no caches, 100MHz clock

| Hardware:       | 32kB int. IMEM, 16kB int. DMEM, no caches, 100MHz clock

| CoreMark:       | 2000 iterations, MEM_METHOD is MEM_STACK

| CoreMark:       | 2000 iterations, MEM_METHOD is MEM_STACK

| Compiler:       | RISCV32-GCC 10.2.0

| Compiler:       | RISCV32-GCC 10.2.0

| Compiler flags: | default, see makefile

| Compiler flags: | default, see makefile

|=======================

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.CoreMark results

.CoreMark results

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| CPU                                             | CoreMark Score | CoreMarks/MHz | Average CPI

| CPU                                             | CoreMark Score | CoreMarks/MHz | Average CPI

| _small_ (`rv32i_Zicsr`)                         |          33.89 | **0.3389**    | **4.04**

| _small_ (`rv32i_Zicsr`)                         |          33.89 | **0.3389**    | **4.04**

| _medium_ (`rv32imc_Zicsr`)                      |          62.50 | **0.6250**    | **5.34**

| _medium_ (`rv32imc_Zicsr`)                      |          62.50 | **0.6250**    | **5.34**

| _performance_ (`rv32imc_Zicsr` + perf. options) |          95.23 | **0.9523**    | **3.54**

| _performance_ (`rv32imc_Zicsr` + perf. options) |          95.23 | **0.9523**    | **3.54**

|=======================

|=======================

The CoreMark results were generated using a `rv32i` toolchain. This toolchain supports standard extensions

The CoreMark results were generated using a `rv32i` toolchain. This toolchain supports standard extensions

like `M` and `C` but the built-in libraries only use the base `I` ISA.

like `M` and `C` but the built-in libraries only use the base `I` ISA.

[NOTE]

[NOTE]

The "_performance_" CPU configuration uses the <<_fast_mul_en>> and <<_fast_shift_en>> options.

The "_performance_" CPU configuration uses the <<_fast_mul_en>> and <<_fast_shift_en>> options.

The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of

The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of

several consecutive micro operations.

several consecutive micro operations.

The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on

The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on

the available CPU extensions. The average CPI is computed by dividing the total number of required clock cycles

the available CPU extensions. The average CPI is computed by dividing the total number of required clock cycles

(only the timed core to avoid distortion due to IO wait cycles) by the number of executed instructions

(only the timed core to avoid distortion due to IO wait cycles) by the number of executed instructions

chapter <<_instruction_timing>>.

chapter <<_instruction_timing>>.