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==== General Purpose Timer (GPTMR)
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==== General Purpose Timer (GPTMR)
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|=======================
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|=======================
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| Hardware source file(s): | neorv32_gptmr.vhd |
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| Hardware source file(s): | neorv32_gptmr.vhd |
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| Software driver file(s): | neorv32_gptmr.c |
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| Software driver file(s): | neorv32_gptmr.c |
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| | neorv32_gptmr.h |
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| | neorv32_gptmr.h |
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| Top entity port: | none |
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| Top entity port: | none |
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| Configuration generics: | _IO_GPTMR_EN_ | implement timer when _true_
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| Configuration generics: | _IO_GPTMR_EN_ | implement timer when _true_
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| CPU interrupts: | fast IRQ channel 12 | transmission done interrupt (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 12 | transmission done interrupt (see <<_processor_interrupts>>)
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|=======================
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|=======================
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**Theory of Operation**
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**Theory of Operation**
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The general purpose timer module provides a simple yet universal 32-bit timer. The timer is implemented if
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The general purpose timer module provides a simple yet universal 32-bit timer. The timer is implemented if
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_IO_GPTMR_EN_ top generic is set _true_. It provides a 32-bit counter register (`COUNT`) and a 32-bit threshold
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_IO_GPTMR_EN_ top generic is set _true_. It provides a 32-bit counter register (`COUNT`) and a 32-bit threshold
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register (`THRES`). An interrupt is generated whenever the value of the counter registers matches the one from
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register (`THRES`). An interrupt is generated whenever the value of the counter registers matches the one from
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threshold register.
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threshold register.
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The timer is enabled by setting the _GPTMR_CTRL_EN_ bit in the device's control register `CTRL`. The `COUNT`
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The timer is enabled by setting the _GPTMR_CTRL_EN_ bit in the device's control register `CTRL`. The `COUNT`
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register will start incrementing at a programmable rate, which scales the main processor clock. The
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register will start incrementing at a programmable rate, which scales the main processor clock. The
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pre-scaler value is configured via the three _GPTMR_CTRL_PRSCx_ control register bits:
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pre-scaler value is configured via the three _GPTMR_CTRL_PRSCx_ control register bits:
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.GPTMR prescaler configuration
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.GPTMR prescaler configuration
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|=======================
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|=======================
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| **`GPTMR_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| **`GPTMR_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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|=======================
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The timer provides two operation modes that are configured by the _GPTMR_CTRL_MODE_ control register bit:
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The timer provides two operation modes that are configured by the _GPTMR_CTRL_MODE_ control register bit:
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if _GPTMR_CTRL_MODE_ is cleared (`0`) the timer operates in _single-shot mode_. As soon as `COUNT` matches
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if _GPTMR_CTRL_MODE_ is cleared (`0`) the timer operates in _single-shot mode_. As soon as `COUNT` matches
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`THRES` an interrupt request is generated and the timer stops operation (i.e. it stops incrementing). If
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`THRES` an interrupt request is generated and the timer stops operation (i.e. it stops incrementing). If
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_GPTMR_CTRL_MODE_ is set (`1`) the timer operates in _continuous mode_. When `COUNT` matches `THRES` an interrupt
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_GPTMR_CTRL_MODE_ is set (`1`) the timer operates in _continuous mode_. When `COUNT` matches `THRES` an interrupt
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request is generated and `COUNT` is automatically reset to all-zero before continuing to increment.
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request is generated and `COUNT` is automatically reset to all-zero before continuing to increment.
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[NOTE]
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[NOTE]
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Disabling the timer will not clear the `COUNT` register. However, it can be manually reset at any time by
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Disabling the timer will not clear the `COUNT` register. However, it can be manually reset at any time by
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writing zero to it.
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writing zero to it.
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**Timer Interrupt**
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**Timer Interrupt**
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The timer interrupt gets pending when the timer is enabled and `COUNT` matches `THRES`. The interrupt
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The timer interrupt is triggered when the timer is enabled and `COUNT` matches `THRES`. The interrupt
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request is indicated via the _GPTMR_CTRL_ALARM_ control register bit. This bit as well as the actual
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remains pending until explicitly cleared by writing the according `mip` CSR bit.
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interrupt keeps pending until the bit is explicitly cleared by application software or if the
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timer is disabled.
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.GPTMR register map (`struct NEORV32_GPTMR`)
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.GPTMR register map (`struct NEORV32_GPTMR`)
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.6+<| `0xffffff60` .6+<| `NEORV32_GPTMR.CTRL` <|`0` _GPTMR_CTRL_EN_ ^| r/w <| Timer enable flag
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.5+<| `0xffffff60` .5+<| `NEORV32_GPTMR.CTRL` <|`0` _GPTMR_CTRL_EN_ ^| r/w <| Timer enable flag
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<|`1` _GPTMR_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`1` _GPTMR_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`2` _GPTMR_CTRL_PRSC1_ ^| r/w
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<|`2` _GPTMR_CTRL_PRSC1_ ^| r/w
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<|`3` _GPTMR_CTRL_PRSC2_ ^| r/w
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<|`3` _GPTMR_CTRL_PRSC2_ ^| r/w
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<|`4` _GPTMR_CTRL_MODE_ ^| r/w <| Counter mode: `0`=single-shot, `1`=continuous
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<|`4` _GPTMR_CTRL_MODE_ ^| r/w <| Counter mode: `0`=single-shot, `1`=continuous
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<|`5` _GPTMR_CTRL_ALARM_ ^| r/c <| Pending interrupt/alarm, cleared by setting bit to zero
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| `0xffffff64` | `NEORV32_GPTMR.THRES` |`31:0` | r/w | Threshold value register
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| `0xffffff64` | `NEORV32_GPTMR.THRES` |`31:0` | r/w | Threshold value register
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| `0xffffff68` | `NEORV32_GPTMR.COUNT` |`31:0` | r/w | Counter register
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| `0xffffff68` | `NEORV32_GPTMR.COUNT` |`31:0` | r/w | Counter register
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|=======================
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|=======================
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