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<<<
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:sectnums:
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==== Two-Wire Serial Interface Controller (TWI)
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==== Two-Wire Serial Interface Controller (TWI)
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[cols="<3,<3,<4"]
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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[frame="topbot",grid="none"]
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|=======================
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|=======================
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| Hardware source file(s): | neorv32_twi.vhd |
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| Hardware source file(s): | neorv32_twi.vhd |
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| Software driver file(s): | neorv32_twi.c |
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| Software driver file(s): | neorv32_twi.c |
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| | neorv32_twi.h |
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| | neorv32_twi.h |
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| Top entity port: | `twi_sda_io` | 1-bit bi-directional serial data
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| Top entity port: | `twi_sda_io` | 1-bit bi-directional serial data
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| | `twi_scl_io` | 1-bit bi-directional serial clock
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| | `twi_scl_io` | 1-bit bi-directional serial clock
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| Configuration generics: | _IO_TWI_EN_ | implement TWI controller when _true_
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| Configuration generics: | _IO_TWI_EN_ | implement TWI controller when _true_
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| CPU interrupts: | fast IRQ channel 7 | transmission done interrupt (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 7 | transmission done interrupt (see <<_processor_interrupts>>)
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|=======================
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|=======================
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**Theory of Operation**
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**Theory of Operation**
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The two wire interface - also called "I²C" - is a quite famous interface for connecting several on-board
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The two wire interface - also called "I²C" - is a quite famous interface for connecting several on-board
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components. Since this interface only needs two signals (the serial data line `twi_sda_io` and the serial
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components. Since this interface only needs two signals (the serial data line `twi_sda_io` and the serial
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clock line `twi_scl_io`) - despite of the number of connected devices - it allows easy interconnections of
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clock line `twi_scl_io`) - despite of the number of connected devices - it allows easy interconnections of
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several peripheral nodes.
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several peripheral nodes.
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The NEORV32 TWI implements a **TWI controller**. It supports "clock so a slow peripheral can halt
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The NEORV32 TWI implements a **TWI controller**. It supports "clock so a slow peripheral can halt
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the transmission by pulling the SCL line low. Currently, **no multi-controller
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the transmission by pulling the SCL line low. Currently, **no multi-controller
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support** is available. Also, the NEORV32 TWI unit cannot operate in peripheral mode.
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support** is available. Also, the NEORV32 TWI unit cannot operate in peripheral mode.
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The TWI is enabled via the _TWI_CTRL_EN_ bit in the `CTRL` control register. The user program can start / stop a
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The TWI is enabled via the _TWI_CTRL_EN_ bit in the `CTRL` control register. The user program can start / stop a
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transmission by issuing a START or STOP condition. These conditions are generated by setting the
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transmission by issuing a START or STOP condition. These conditions are generated by setting the
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according bits (_TWI_CTRL_START_ or _TWI_CTRL_STOP_) in the control register.
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according bits (_TWI_CTRL_START_ or _TWI_CTRL_STOP_) in the control register.
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Data is send by writing a byte to the `DATA` register. Received data can also be read from this
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Data is send by writing a byte to the `DATA` register. Received data can also be read from this
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register. The TWI controller is busy (transmitting data or performing a START or STOP condition) as long as the
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register. The TWI controller is busy (transmitting data or performing a START or STOP condition) as long as the
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_TWI_CTRL_BUSY_ bit in the control register is set.
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_TWI_CTRL_BUSY_ bit in the control register is set.
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An accessed peripheral has to acknowledge each transferred byte. When the _TWI_CTRL_ACK_ bit is set after a
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An accessed peripheral has to acknowledge each transferred byte. When the _TWI_CTRL_ACK_ bit is set after a
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completed transmission, the accessed peripheral has send an acknowledge. If it is cleared after a
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completed transmission, the accessed peripheral has send an acknowledge. If it is cleared after a
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transmission, the peripheral has send a not-acknowledge (NACK). The NEORV32 TWI controller can also
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transmission, the peripheral has send a not-acknowledge (NACK). The NEORV32 TWI controller can also
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send an ACK by itself ("controller acknowledge _MACK_") after a transmission by pulling SDA low during the
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send an ACK by itself ("controller acknowledge _MACK_") after a transmission by pulling SDA low during the
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ACK time slot. Set the _TWI_CTRL_MACK_ bit to activate this feature. If this bit is cleared, the ACK/NACK of the
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ACK time slot. Set the _TWI_CTRL_MACK_ bit to activate this feature. If this bit is cleared, the ACK/NACK of the
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peripheral is sampled in this time slot instead (normal mode).
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peripheral is sampled in this time slot instead (normal mode).
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In summary, the following independent TWI operations can be triggered by the application program:
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In summary, the following independent TWI operations can be triggered by the application program:
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* send START condition (also as REPEATED START condition)
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* send START condition (also as REPEATED START condition)
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* send STOP condition
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* send STOP condition
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* send (at least) one byte while also sampling one byte from the bus
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* send (at least) one byte while also sampling one byte from the bus
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[TIP]
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[TIP]
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A transmission can be terminated at any time by disabling the TWI module
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A transmission can be terminated at any time by disabling the TWI module
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by clearing the _TWI_CTRL_EN_ control register bit.
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by clearing the _TWI_CTRL_EN_ control register bit.
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[IMPORTANT]
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[IMPORTANT]
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The serial clock (SCL) and the serial data (SDA) lines can only be actively driven low by the
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The serial clock (SCL) and the serial data (SDA) lines can only be actively driven low by the
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controller. Hence, external pull-up resistors are required for these lines.
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controller. Hence, external pull-up resistors are required for these lines.
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The TWI clock frequency is defined via the 3-bit _TWI_CTRL_PRSCx_ clock prescaler. The following prescalers
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The TWI clock frequency is defined via the 3-bit _TWI_CTRL_PRSCx_ clock prescaler. The following prescalers
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are available:
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are available:
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.TWI prescaler configuration
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.TWI prescaler configuration
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| **`TWI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| **`TWI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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|=======================
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Based on the _TWI_CTRL_PRSCx_ configuration, the actual TWI clock frequency f~SCL~ is derived from the processor main clock f~main~ and is determined by:
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Based on the _TWI_CTRL_PRSCx_ configuration, the actual TWI clock frequency f~SCL~ is derived from the processor main clock f~main~ and is determined by:
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_**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler`)
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_**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler`)
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**TWI Interrupt**
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**TWI Interrupt**
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The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI
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The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI
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module completes the current operation (generate stop condition, generate start conditions or transfer byte),
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module completes the current operation (generate stop condition, generate start conditions or transfer byte),
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the interrupt request is set. A pending interrupt request is cleared is cleared by any of
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the interrupt is triggered. Once triggered, the interrupt has to be explicitly cleared again by setting the according
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the following operations:
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`mip` CSR bit.
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* read or write access to `NEORV32_TWI.DATA` (for example to trigger a new transmission)
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* write access to `NEORV32_TWI.CTRL`
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* disabling the TWI module
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[TIP]
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A dummy read from `NEORV32_TWI.DATA` can be executed to acknowledge the interrupt without affecting data
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or the state of the TWI module.
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.TWI register map (`struct NEORV32_TWI`)
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.TWI register map (`struct NEORV32_TWI`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.9+<| `0xffffffb0` .9+<| `NEORV32_TWI.CTRL` <|`0` _TWI_CTRL_EN_ ^| r/w <| TWI enable
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.9+<| `0xffffffb0` .9+<| `NEORV32_TWI.CTRL` <|`0` _TWI_CTRL_EN_ ^| r/w <| TWI enable
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<|`1` _TWI_CTRL_START_ ^| r/w <| generate START condition
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<|`1` _TWI_CTRL_START_ ^| r/w <| generate START condition
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<|`2` _TWI_CTRL_STOP_ ^| r/w <| generate STOP condition
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<|`2` _TWI_CTRL_STOP_ ^| r/w <| generate STOP condition
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<|`3` _TWI_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
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<|`3` _TWI_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
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<|`4` _TWI_CTRL_PRSC1_ ^| r/w
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<|`4` _TWI_CTRL_PRSC1_ ^| r/w
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<|`5` _TWI_CTRL_PRSC2_ ^| r/w
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<|`5` _TWI_CTRL_PRSC2_ ^| r/w
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<|`6` _TWI_CTRL_MACK_ ^| r/w <| generate controller ACK for each transmission ("MACK")
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<|`6` _TWI_CTRL_MACK_ ^| r/w <| generate controller ACK for each transmission ("MACK")
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<|`30` _TWI_CTRL_ACK_ ^| r/- <| ACK received when set
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<|`30` _TWI_CTRL_ACK_ ^| r/- <| ACK received when set
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<|`31` _TWI_CTRL_BUSY_ ^| r/- <| transfer/START/STOP in progress when set
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<|`31` _TWI_CTRL_BUSY_ ^| r/- <| transfer/START/STOP in progress when set
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| `0xffffffb4` | `NEORV32_TWI.DATA` |`7:0` _TWI_DATA_MSB_ : TWI_DATA_LSB_ | r/w | receive/transmit data
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| `0xffffffb4` | `NEORV32_TWI.DATA` |`7:0` _TWI_DATA_MSB_ : TWI_DATA_LSB_ | r/w | receive/transmit data
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|=======================
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|=======================
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