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==== Processor-External Memory Interface (WISHBONE) (AXI4-Lite)
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==== Processor-External Memory Interface (WISHBONE) (AXI4-Lite)
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|=======================
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|=======================
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| Hardware source file(s): | neorv32_wishbone.vhd |
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| Hardware source file(s): | neorv32_wishbone.vhd |
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| Software driver file(s): | none | _implicitly used_
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| Software driver file(s): | none | _implicitly used_
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| Top entity port: | `wb_tag_o` | request tag output (3-bit)
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| Top entity port: | `wb_tag_o` | request tag output (3-bit)
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| | `wb_adr_o` | address output (32-bit)
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| | `wb_adr_o` | address output (32-bit)
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| | `wb_dat_i` | data input (32-bit)
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| | `wb_dat_i` | data input (32-bit)
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| | `wb_dat_o` | data output (32-bit)
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| | `wb_dat_o` | data output (32-bit)
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| | `wb_we_o` | write enable (1-bit)
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| | `wb_we_o` | write enable (1-bit)
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| | `wb_sel_o` | byte enable (4-bit)
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| | `wb_sel_o` | byte enable (4-bit)
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| | `wb_stb_o` | strobe (1-bit)
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| | `wb_stb_o` | strobe (1-bit)
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| | `wb_cyc_o` | valid cycle (1-bit)
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| | `wb_cyc_o` | valid cycle (1-bit)
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| | `wb_lock_o` | exclusive access request (1-bit)
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| | `wb_lock_o` | exclusive access request (1-bit)
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| | `wb_ack_i` | acknowledge (1-bit)
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| | `wb_ack_i` | acknowledge (1-bit)
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| | `wb_err_i` | bus error (1-bit)
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| | `wb_err_i` | bus error (1-bit)
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| | `fence_o` | an executed `fence` instruction
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| | `fence_o` | an executed `fence` instruction
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| | `fencei_o` | an executed `fence.i` instruction
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| | `fencei_o` | an executed `fence.i` instruction
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| Configuration generics: | _MEM_EXT_EN_ | enable external memory interface when _true_
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| Configuration generics: | _MEM_EXT_EN_ | enable external memory interface when _true_
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| | _MEM_EXT_TIMEOUT_ | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
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| | _MEM_EXT_TIMEOUT_ | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
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| | _MEM_EXT_PIPE_MODE_ | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
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| | _MEM_EXT_PIPE_MODE_ | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
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| | _MEM_EXT_BIG_ENDIAN_ | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
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| | _MEM_EXT_BIG_ENDIAN_ | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
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| | _MEM_EXT_ASYNC_RX_ | use registered RX path when _false_ (default); use async/direct RX path when _true_
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| | _MEM_EXT_ASYNC_RX_ | use registered RX path when _false_ (default); use async/direct RX path when _true_
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| CPU interrupts: | none |
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| CPU interrupts: | none |
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|=======================
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|=======================
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The external memory interface provides a Wishbone b4-compatible on-chip bus interface. The bus interface is
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The external memory interface provides a Wishbone b4-compatible on-chip bus interface. The bus interface is
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implemented when the _MEM_EXT_EN_ generic is _true_. This interface can be used to attach external memories,
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implemented when the _MEM_EXT_EN_ generic is _true_. This interface can be used to attach external memories,
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custom hardware accelerators, additional IO devices or all other kinds of IP blocks.
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custom hardware accelerators, additional IO devices or all other kinds of IP blocks.
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The external interface is _not_ mapped to a _specific_ address space region. Instead, all CPU memory accesses that
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The external interface is _not_ mapped to a _specific_ address space region. Instead, all CPU memory accesses that
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do not target a processor-internal module are delegated to the external memory interface. In summary, a CPU load/store
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do not target a processor-internal module are delegated to the external memory interface. In summary, a CPU load/store
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access is delegated to the external bus interface if...
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access is delegated to the external bus interface if...
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. it does not target the internal instruction memory IMEM (if implemented at all)
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. it does not target the internal instruction memory IMEM (if implemented at all)
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. **and** it does not target the internal data memory DMEM (if implemented at all)
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. **and** it does not target the internal data memory DMEM (if implemented at all)
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. **and** it does not target the internal bootloader ROM or any of the IO devices - regardless if one or more of these components are
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. **and** it does not target the internal bootloader ROM or any of the IO devices - regardless if one or more of these components are
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actually implemented or not.
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actually implemented or not.
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[NOTE]
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If the Execute In Place module (XIP) is implemented accesses map to this module are not forwarded to the
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external memory interface. See section <<_execute_in_place_module_xip>> for more information.
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[TIP]
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[TIP]
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See section <<_address_space>> for more information.
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See section <<_address_space>> for more information.
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**Wishbone Bus Protocol**
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**Wishbone Bus Protocol**
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The external memory interface either uses the **standard** ("classic") Wishbone transaction protocol (default) or
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The external memory interface either uses the **standard** ("classic") Wishbone transaction protocol (default) or
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**pipelined** Wishbone transaction protocol. The transaction protocol is configured via the _MEM_EXT_PIPE_MODE_ generic:
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**pipelined** Wishbone transaction protocol. The transaction protocol is configured via the _MEM_EXT_PIPE_MODE_ generic:
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When _MEM_EXT_PIPE_MODE_ is _false_, all bus control signals including _STB_ are active and remain stable until the
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When _MEM_EXT_PIPE_MODE_ is _false_, all bus control signals including _STB_ are active and remain stable until the
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transfer is acknowledged/terminated. If _MEM_EXT_PIPE_MODE_ is _true_, all bus control except _STB_ are active
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transfer is acknowledged/terminated. If _MEM_EXT_PIPE_MODE_ is _true_, all bus control except _STB_ are active
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and remain until the transfer is acknowledged/terminated. In this case, _STB_ is asserted only during the very
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and remain until the transfer is acknowledged/terminated. In this case, _STB_ is asserted only during the very
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first bus clock cycle.
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first bus clock cycle.
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.Exemplary Wishbone bus accesses using "classic" and "pipelined" protocol
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.Exemplary Wishbone bus accesses using "classic" and "pipelined" protocol
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|=======================
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|=======================
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a| image::wishbone_classic_read.png[700,300]
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a| image::wishbone_classic_read.png[700,300]
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a| image::wishbone_pipelined_write.png[700,300]
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a| image::wishbone_pipelined_write.png[700,300]
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| **Classic** Wishbone read access | **Pipelined** Wishbone write access
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| **Classic** Wishbone read access | **Pipelined** Wishbone write access
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|=======================
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|=======================
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[TIP]
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[TIP]
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A detailed description of the implemented Wishbone bus protocol and the according interface signals
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A detailed description of the implemented Wishbone bus protocol and the according interface signals
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can be found in the data sheet "Wishbone B4 - WISHBONE System-on-Chip (SoC) Interconnection
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can be found in the data sheet "Wishbone B4 - WISHBONE System-on-Chip (SoC) Interconnection
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Architecture for Portable IP Cores". A copy of this document can be found in the docs folder of this
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Architecture for Portable IP Cores". A copy of this document can be found in the docs folder of this
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project.
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project.
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**Bus Access**
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**Bus Access**
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The NEORV32 Wishbone gateway does not support burst transfer yet, so there is always just one transfer in progress.
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The NEORV32 Wishbone gateway does not support burst transfer yet, so there is always just one transfer in progress.
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Hence, the Wishbone `STALL` signal is not implemented. An accessed Wishbone device does not have to respond immediately to a bus
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Hence, the Wishbone `STALL` signal is not implemented. An accessed Wishbone device does not have to respond immediately to a bus
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request by sending an ACK. instead, there is a _time window_ where the device has to acknowledge the transfer. This time window
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request by sending an ACK. instead, there is a _time window_ where the device has to acknowledge the transfer. This time window
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id configured by the _MEM_EXT_TIMEOUT_ top generic that defines the maximum time (in clock cycles) a bus access can be pending
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id configured by the _MEM_EXT_TIMEOUT_ top generic that defines the maximum time (in clock cycles) a bus access can be pending
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before it is automatically terminated. If _MEM_EXT_TIMEOUT_ is set to zero, the timeout disabled an a bus access can take an
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before it is automatically terminated. If _MEM_EXT_TIMEOUT_ is set to zero, the timeout disabled an a bus access can take an
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arbitrary number of cycles to complete.
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arbitrary number of cycles to complete.
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When _MEM_EXT_TIMEOUT_ is greater than zero, the Wishbone gateway starts an internal countdown whenever the CPU
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When _MEM_EXT_TIMEOUT_ is greater than zero, the Wishbone gateway starts an internal countdown whenever the CPU
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accesses a memory address via the external memory interface. If the accessed memory / device does not acknowledge (via `wb_ack_i`)
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accesses a memory address via the external memory interface. If the accessed memory / device does not acknowledge (via `wb_ack_i`)
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or terminate (via `wb_err_i`) the transfer within _MEM_EXT_TIMEOUT_ clock cycles, the bus access is automatically canceled
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or terminate (via `wb_err_i`) the transfer within _MEM_EXT_TIMEOUT_ clock cycles, the bus access is automatically canceled
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setting `wb_cyc_o` low again and a CPU load/store/instruction fetch bus access fault exception is raised.
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setting `wb_cyc_o` low again and a CPU load/store/instruction fetch bus access fault exception is raised.
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[IMPORTANT]
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[IMPORTANT]
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Setting _MEM_EXT_TIMEOUT_ to zero will permanently stall the CPU if the targeted Wishbone device never responds. Hence,
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Setting _MEM_EXT_TIMEOUT_ to zero will permanently stall the CPU if the targeted Wishbone device never responds. Hence,
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_MEM_EXT_TIMEOUT_ should be always set to a value greater than zero. +
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_MEM_EXT_TIMEOUT_ should be always set to a value greater than zero. +
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+
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+
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This feature can be used as **safety guard** if the external memory system does not check for "address space holes". That means
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This feature can be used as **safety guard** if the external memory system does not check for "address space holes". That means
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that accessing addresses, which do not belong to a certain memory or device, do not permanently stall the processor due to an
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that accessing addresses, which do not belong to a certain memory or device, do not permanently stall the processor due to an
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unacknowledged/unterminated bus access. If the external memory system can guarantee to access **any** bus access
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unacknowledged/unterminated bus access. If the external memory system can guarantee to access **any** bus access
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(even it targets an unimplemented address) the timeout feature should be disabled (_MEM_EXT_TIMEOUT_ = 0).
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(even it targets an unimplemented address) the timeout feature should be disabled (_MEM_EXT_TIMEOUT_ = 0).
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**Wishbone Tag**
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**Wishbone Tag**
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The 3-bit wishbone `wb_tag_o` signal provides additional information regarding the access type. This signal
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The 3-bit wishbone `wb_tag_o` signal provides additional information regarding the access type. This signal
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is compatible to the AXI4 _AxPROT_ signal.
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is compatible to the AXI4 _AxPROT_ signal.
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* `wb_tag_o(0)` 1: privileged access (CPU is in machine mode); 0: unprivileged access
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* `wb_tag_o(0)` 1: privileged access (CPU is in machine mode); 0: unprivileged access
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* `wb_tag_o(1)` always zero (indicating "secure access")
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* `wb_tag_o(1)` always zero (indicating "secure access")
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* `wb_tag_o(2)` 1: instruction fetch access, 0: data access
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* `wb_tag_o(2)` 1: instruction fetch access, 0: data access
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**Exclusive / Atomic Bus Access**
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**Exclusive / Atomic Bus Access**
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If the atomic memory access CPU extension (via _CPU_EXTENSION_RISCV_A_) is enabled, the CPU can
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If the atomic memory access CPU extension (via _CPU_EXTENSION_RISCV_A_) is enabled, the CPU can
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request an atomic/exclusive bus access via the external memory interface.
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request an atomic/exclusive bus access via the external memory interface.
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The load-reservate instruction (`lr.w`) will set the `wb_lock_o` signal telling the bus interconnect to establish a
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The load-reservate instruction (`lr.w`) will set the `wb_lock_o` signal telling the bus interconnect to establish a
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reservation for the current accessed address (start of an exclusive access). This signal will stay asserted until
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reservation for the current accessed address (start of an exclusive access). This signal will stay asserted until
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another memory access instruction is executed (for example a `sc.w`).
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another memory access instruction is executed (for example a `sc.w`).
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The memory system has to make sure that no other entity can access the reservated address until `wb_lock_o`
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The memory system has to make sure that no other entity can access the reservated address until `wb_lock_o`
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is released again. If this attempt fails, the memory system has to assert `wb_err_i` in order to indicate that the
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is released again. If this attempt fails, the memory system has to assert `wb_err_i` in order to indicate that the
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reservation was broken.
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reservation was broken.
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[TIP]
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[TIP]
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See section <<_bus_interface>> for the CPU bus interface protocol.
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See section <<_bus_interface>> for the CPU bus interface protocol.
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**Endianness**
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**Endianness**
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The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
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The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
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to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
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to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
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Endianness (of the external memory interface) can be configured via the _MEM_EXT_BIG_ENDIAN_ generic.
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Endianness (of the external memory interface) can be configured via the _MEM_EXT_BIG_ENDIAN_ generic.
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By default, the external memory interface uses little-endian byte-order (like the rest of the processor / CPU).
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By default, the external memory interface uses little-endian byte-order (like the rest of the processor / CPU).
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Application software can check the Endianness configuration of the external bus interface via the
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Application software can check the Endianness configuration of the external bus interface via the
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SYSINFO module (see section <<_system_configuration_information_memory_sysinfo>> for more information).
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SYSINFO module (see section <<_system_configuration_information_memory_sysinfo>> for more information).
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**Gateway Latency**
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**Gateway Latency**
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By default, the Wishbone gateway introduces two additional latency cycles: processor-outgoing ("TX") and
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By default, the Wishbone gateway introduces two additional latency cycles: processor-outgoing ("TX") and
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processor-incoming ("RX") signals are fully registered. Thus, any access from the CPU to a processor-external devices
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processor-incoming ("RX") signals are fully registered. Thus, any access from the CPU to a processor-external devices
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via Wishbone requires 2 additional clock cycles (at least; depending on device's latency).
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via Wishbone requires 2 additional clock cycles (at least; depending on device's latency).
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If the attached Wishbone network / peripheral already provides output registers or if the Wishbone network is not relevant
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If the attached Wishbone network / peripheral already provides output registers or if the Wishbone network is not relevant
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for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled by implementing an
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for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled by implementing an
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"asynchronous" RX path. The configuration is done via the _MEM_EXT_ASYNC_RX_ generic.
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"asynchronous" RX path. The configuration is done via the _MEM_EXT_ASYNC_RX_ generic.
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**AXI4-Lite Connectivity**
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**AXI4-Lite Connectivity**
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The AXI4-Lite wrapper (`rtl/system_integration/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
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The AXI4-Lite wrapper (`rtl/system_integration/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
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AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
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AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
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this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
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this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
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The AXI Interface has been verified using Xilinx Vivado IP Packager and Block Designer. The AXI
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The AXI Interface has been verified using Xilinx Vivado IP Packager and Block Designer. The AXI
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interface port signals are automatically detected when packaging the core.
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interface port signals are automatically detected when packaging the core.
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.Example AXI SoC using Xilinx Vivado
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.Example AXI SoC using Xilinx Vivado
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image::neorv32_axi_soc.png[]
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image::neorv32_axi_soc.png[]
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[WARNING]
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[WARNING]
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Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as
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Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as
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the AXI protocol does not support canceling of bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface
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the AXI protocol does not support canceling of bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface
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(`rtl/system_integration/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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(`rtl/system_integration/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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