<<<
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<<<
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:sectnums:
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==== External Interrupt Controller (XIRQ)
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==== External Interrupt Controller (XIRQ)
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|=======================
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|=======================
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| Hardware source file(s): | neorv32_xirq.vhd |
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| Hardware source file(s): | neorv32_xirq.vhd |
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| Software driver file(s): | neorv32_xirq.c |
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| Software driver file(s): | neorv32_xirq.c |
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| | neorv32_xirq.h |
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| | neorv32_xirq.h |
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| Top entity port: | `xirq_i` | IRQ input (up to 32-bit)
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| Top entity port: | `xirq_i` | IRQ input (32-bit, fixed)
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| Configuration generics: | _XIRQ_NUM_CH_ | Number of IRQs to implement (0..32)
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| Configuration generics: | _XIRQ_NUM_CH_ | Number of IRQs to implement (0..32)
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| | _XIRQ_TRIGGER_TYPE_ | IRQ trigger type configuration
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| | _XIRQ_TRIGGER_TYPE_ | IRQ trigger type configuration
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| | _XIRQ_TRIGGER_POLARITY_ | IRQ trigger polarity configuration
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| | _XIRQ_TRIGGER_POLARITY_ | IRQ trigger polarity configuration
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| CPU interrupts: | fast IRQ channel 8 | XIRQ (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 8 | XIRQ (see <<_processor_interrupts>>)
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|=======================
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|=======================
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The eXternal interrupt controller provides a simple mechanism to implement up to 32 processor-external interrupt
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The eXternal interrupt controller provides a simple mechanism to implement up to 32 processor-external interrupt
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request signals. The external IRQ requests are prioritized, queued and signaled to the CPU via a
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request signals. The external IRQ requests are prioritized, queued and signaled to the CPU via a
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single _CPU fast interrupt request_.
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single _CPU fast interrupt request_.
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**Theory of Operation**
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**Theory of Operation**
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The XIRQ provides up to 32 interrupt _channels_ (configured via the _XIRQ_NUM_CH_ generic). Each bit in the `xirq_i`
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The XIRQ provides up to 32 interrupt _channels_ (configured via the _XIRQ_NUM_CH_ generic). Each bit in the `xirq_i`
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input signal vector represents one interrupt channel. An interrupt channel is enabled by setting the according bit in the
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input signal vector represents one interrupt channel. If less than 32 channels are configure, only the LSB-aligned channels
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are used while the remaining bits are left unconnected. An interrupt channel is enabled by setting the according bit in the
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interrupt enable register `IER`.
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interrupt enable register `IER`.
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If the configured trigger (see below) of an enabled channel fires, the request is stored into an internal buffer.
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If the configured trigger (see below) of an enabled channel fires, the request is stored into an internal buffer.
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This buffer is available via the interrupt pending register `IPR`. A `1` in this register indicates that the
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This buffer is available via the interrupt pending register `IPR`. A `1` in this register indicates that the
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corresponding interrupt channel has fired but has not yet been serviced (so it is pending). An interrupt channel can
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corresponding interrupt channel has fired but has not yet been serviced (so it is pending). An interrupt channel can
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become pending if the according `IER` bit is set. Pending IRQs can be cleared by writing `0` to the according `IPR`
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become pending if the according `IER` bit is set. Pending IRQs can be cleared by writing `0` to the according `IPR`
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bit. As soon as there is a least one pending interrupt in the buffer, an interrupt request is send to the CPU.
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bit. As soon as there is a least one pending interrupt in the buffer, an interrupt request is send to the CPU.
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[NOTE]
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[NOTE]
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A disabled interrupt channel can still be pending if it has been triggered before clearing the according `IER` bit.
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A disabled interrupt channel can still be pending if it has been triggered before clearing the according `IER` bit.
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The CPU can determine active external interrupt request either by checking the bits in the `IPR` register, which show all
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The CPU can determine active external interrupt request either by checking the bits in the `IPR` register, which show all
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pending interrupt channels, or by reading the interrupt source register `SCR`.
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pending interrupt channels, or by reading the interrupt source register `SCR`.
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This register provides a 5-bit wide ID (0..31) that shows the interrupt request with _highest priority_.
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This register provides a 5-bit wide ID (0..31) that shows the interrupt request with _highest priority_.
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Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority.
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Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority.
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This priority assignment is fixed and cannot be altered by software.
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This priority assignment is fixed and cannot be altered by software.
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The CPU can use the ID from `SCR` to service IRQ according to their priority. To acknowledge the according
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The CPU can use the ID from `SCR` to service IRQ according to their priority. To acknowledge the according
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interrupt the CPU can write `1 << SCR` to `IPR`.
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interrupt the CPU can write `1 << SCR` to `IPR`.
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In order to clear a pending FIRQ interrupt from the external interrupt controller again, the according `mip` CSR bit has
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In order to clear a pending FIRQ interrupt from the external interrupt controller again, the according `mip` CSR bit has
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to be set. Additionally, the XIRQ interrupt has to be acknowledged by writing _any_
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to be set. Additionally, the XIRQ interrupt has to be acknowledged by writing _any_
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value to the interrupt source register `SRC`.
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value to the interrupt source register `SRC`.
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[NOTE]
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[NOTE]
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An interrupt handler should clear the interrupt pending bit that caused the interrupt first before
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An interrupt handler should clear the interrupt pending bit that caused the interrupt first before
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acknowledging the interrupt by writing the `SCR` register.
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acknowledging the interrupt by writing the `SCR` register.
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**IRQ Trigger Configuration**
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**IRQ Trigger Configuration**
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The controller does not provide a configuration option to define the IRQ triggers _during runtime_. Instead, two
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The controller does not provide a configuration option to define the IRQ triggers _during runtime_. Instead, two
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generics are provided to configure the trigger of each interrupt channel before synthesis: the _XIRQ_TRIGGER_TYPE_
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generics are provided to configure the trigger of each interrupt channel before synthesis: the _XIRQ_TRIGGER_TYPE_
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and _XIRQ_TRIGGER_POLARITY_ generic. Both generics are 32 bit wide representing one bit per interrupt channel. If
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and _XIRQ_TRIGGER_POLARITY_ generic. Both generics are 32 bit wide representing one bit per interrupt channel. If
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less than 32 interrupt channels are implemented the remaining configuration bits are ignored.
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less than 32 interrupt channels are implemented the remaining configuration bits are ignored.
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_XIRQ_TRIGGER_TYPE_ is used to define the general trigger type. This can be either _level-triggered_ (`0`) or
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_XIRQ_TRIGGER_TYPE_ is used to define the general trigger type. This can be either _level-triggered_ (`0`) or
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_edge-triggered_ (`1`). _XIRQ_TRIGGER_POLARITY_ is used to configure the polarity of the trigger: a `0` defines
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_edge-triggered_ (`1`). _XIRQ_TRIGGER_POLARITY_ is used to configure the polarity of the trigger: a `0` defines
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low-level or falling-edge and a `1` defines high-level or rising-edge.
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low-level or falling-edge and a `1` defines high-level or rising-edge.
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.Example trigger configuration: channel 0 for rising-edge, IRQ channels 1 to 31 for high-level
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.Example trigger configuration: channel 0 for rising-edge, IRQ channels 1 to 31 for high-level
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[source, vhdl]
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[source, vhdl]
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----
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----
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XIRQ_TRIGGER_TYPE => x"00000001";
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XIRQ_TRIGGER_TYPE => x"00000001";
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XIRQ_TRIGGER_POLARITY => x"ffffffff";
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XIRQ_TRIGGER_POLARITY => x"ffffffff";
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----
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----
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.XIRQ register map (`struct NEORV32_XIRQ`)
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.XIRQ register map (`struct NEORV32_XIRQ`)
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|=======================
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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| Address | Name [C] | Bit(s) | R/W | Function
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| `0xffffff80` | `NEORV32_XIRQ.IER` | `31:0` | r/w | Interrupt enable register (one bit per channel, LSB-aligned)
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| `0xffffff80` | `NEORV32_XIRQ.IER` | `31:0` | r/w | Interrupt enable register (one bit per channel, LSB-aligned)
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| `0xffffff84` | `NEORV32_XIRQ.IPR` | `31:0` | r/w | Interrupt pending register (one bit per channel, LSB-aligned); writing 0 to a bit clears according pending interrupt
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| `0xffffff84` | `NEORV32_XIRQ.IPR` | `31:0` | r/w | Interrupt pending register (one bit per channel, LSB-aligned); writing 0 to a bit clears according pending interrupt
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| `0xffffff88` | `NEORV32_XIRQ.SCR` | `4:0` | r/w | Channel id (0..31) of firing IRQ (prioritized!); writing _any_ value will acknowledge the current interrupt
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| `0xffffff88` | `NEORV32_XIRQ.SCR` | `4:0` | r/w | Channel id (0..31) of firing IRQ (prioritized!); writing _any_ value will acknowledge the current interrupt
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| `0xffffff8c` | - | `31:0` | r/- | _reserved_, read as zero
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| `0xffffff8c` | - | `31:0` | r/- | _reserved_, read as zero
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|=======================
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|=======================
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