-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Top Entity >> #
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-- # << NEORV32 - CPU Top Entity >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Top NEORV32 CPU: #
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-- # Top NEORV32 CPU: #
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-- # * neorv32_cpu_alu: Arithemtical/logical unit #
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-- # * neorv32_cpu_alu: Arithemtic/logic unit #
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-- # * neorv32_cpu_ctrl: CPU control and CSR system #
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-- # * neorv32_cpu_ctrl: CPU control and CSR system #
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-- # * neorv32_cpu_decompressor: Compressed instructions decoder #
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-- # * neorv32_cpu_decompressor: Compressed instructions decoder #
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-- # * neorv32_cpu_bus: Memory/IO bus interface unit #
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-- # * neorv32_cpu_bus: Instruction and data bus interface unit #
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-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor #
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-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor #
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-- # * neorv32_cpu_regfile: Data register file #
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-- # * neorv32_cpu_regfile: Data register file #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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-- Memory configuration: External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- bus interface --
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-- instruction bus interface --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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-- data bus interface --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- external interrupts --
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-- external interrupts --
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msw_irq_i : in std_ulogic; -- software interrupt
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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);
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);
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end neorv32_cpu;
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end neorv32_cpu;
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architecture neorv32_cpu_rtl of neorv32_cpu is
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architecture neorv32_cpu_rtl of neorv32_cpu is
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-- local signals --
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-- local signals --
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signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal bus_wait : std_ulogic; -- wait for bus to finish operation
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signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
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signal bus_d_wait : std_ulogic; -- wait for current bus data access
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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signal ma_instr : std_ulogic; -- misaligned instruction address
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signal ma_instr : std_ulogic; -- misaligned instruction address
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signal ma_load : std_ulogic; -- misaligned load data address
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signal ma_load : std_ulogic; -- misaligned load data address
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signal ma_store : std_ulogic; -- misaligned store data address
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signal ma_store : std_ulogic; -- misaligned store data address
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal bus_busy : std_ulogic; -- bus unit is busy
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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|
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-- co-processor interface --
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-- co-processor interface --
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_valid, cp1_valid : std_ulogic;
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|
|
begin
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begin
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|
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-- Control Unit ---------------------------------------------------------------------------
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-- Control Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_control_inst: neorv32_cpu_control
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neorv32_cpu_control_inst: neorv32_cpu_control
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generic map (
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generic map (
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-- General --
|
-- General --
|
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
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HART_ID => HART_ID, -- custom hardware thread ID
|
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BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
|
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CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
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HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
|
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
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MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
|
|
MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
|
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MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
|
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MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
|
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
|
|
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
|
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_o => ctrl, -- main control bus
|
ctrl_o => ctrl, -- main control bus
|
-- status input --
|
-- status input --
|
alu_wait_i => alu_wait, -- wait for ALU
|
alu_wait_i => alu_wait, -- wait for ALU
|
bus_wait_i => bus_wait, -- wait for bus
|
bus_i_wait_i => bus_i_wait, -- wait for bus
|
|
bus_d_wait_i => bus_d_wait, -- wait for bus
|
-- data input --
|
-- data input --
|
instr_i => instr, -- instruction
|
instr_i => instr, -- instruction
|
cmp_i => alu_cmp, -- comparator status
|
cmp_i => alu_cmp, -- comparator status
|
alu_add_i => alu_add, -- ALU.add result
|
alu_add_i => alu_add, -- ALU.add result
|
-- data output --
|
-- data output --
|
imm_o => imm, -- immediate
|
imm_o => imm, -- immediate
|
fetch_pc_o => fetch_pc, -- PC for instruction fetch
|
fetch_pc_o => fetch_pc, -- PC for instruction fetch
|
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
next_pc_o => next_pc, -- next PC (corresponding to current instruction)
|
next_pc_o => next_pc, -- next PC (corresponding to current instruction)
|
-- csr interface --
|
-- csr interface --
|
csr_wdata_i => alu_res, -- CSR write data
|
csr_wdata_i => alu_res, -- CSR write data
|
csr_rdata_o => csr_rdata, -- CSR read data
|
csr_rdata_o => csr_rdata, -- CSR read data
|
-- external interrupt --
|
-- external interrupt --
|
|
msw_irq_i => msw_irq_i, -- software interrupt
|
clic_irq_i => clic_irq_i, -- CLIC interrupt request
|
clic_irq_i => clic_irq_i, -- CLIC interrupt request
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => time_i, -- current system time
|
time_i => time_i, -- current system time
|
-- bus access exceptions --
|
-- bus access exceptions --
|
mar_i => mar, -- memory address register
|
mar_i => mar, -- memory address register
|
ma_instr_i => ma_instr, -- misaligned instruction address
|
ma_instr_i => ma_instr, -- misaligned instruction address
|
ma_load_i => ma_load, -- misaligned load data address
|
ma_load_i => ma_load, -- misaligned load data address
|
ma_store_i => ma_store, -- misaligned store data address
|
ma_store_i => ma_store, -- misaligned store data address
|
be_instr_i => be_instr, -- bus error on instruction access
|
be_instr_i => be_instr, -- bus error on instruction access
|
be_load_i => be_load, -- bus error on load data access
|
be_load_i => be_load, -- bus error on load data access
|
be_store_i => be_store, -- bus error on store data access
|
be_store_i => be_store -- bus error on store data access
|
bus_busy_i => bus_busy -- bus unit is busy
|
|
);
|
);
|
|
|
|
|
-- Register File --------------------------------------------------------------------------
|
-- Register File --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_regfile_inst: neorv32_cpu_regfile
|
neorv32_regfile_inst: neorv32_cpu_regfile
|
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E -- implement embedded RF extension?
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
-- data input --
|
-- data input --
|
mem_i => rdata, -- memory read data
|
mem_i => rdata, -- memory read data
|
alu_i => alu_res, -- ALU result
|
alu_i => alu_res, -- ALU result
|
csr_i => csr_rdata, -- CSR read data
|
csr_i => csr_rdata, -- CSR read data
|
pc_i => next_pc, -- next pc
|
pc_i => next_pc, -- next pc
|
-- data output --
|
-- data output --
|
rs1_o => rs1, -- operand 1
|
rs1_o => rs1, -- operand 1
|
rs2_o => rs2 -- operand 2
|
rs2_o => rs2 -- operand 2
|
);
|
);
|
|
|
|
|
-- ALU ------------------------------------------------------------------------------------
|
-- ALU ------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_alu_inst: neorv32_cpu_alu
|
neorv32_cpu_alu_inst: neorv32_cpu_alu
|
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension?
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
-- data input --
|
-- data input --
|
rs1_i => rs1, -- rf source 1
|
rs1_i => rs1, -- rf source 1
|
rs2_i => rs2, -- rf source 2
|
rs2_i => rs2, -- rf source 2
|
pc2_i => curr_pc, -- delayed PC
|
pc2_i => curr_pc, -- delayed PC
|
imm_i => imm, -- immediate
|
imm_i => imm, -- immediate
|
csr_i => csr_rdata, -- csr read data
|
csr_i => csr_rdata, -- csr read data
|
-- data output --
|
-- data output --
|
cmp_o => alu_cmp, -- comparator status
|
cmp_o => alu_cmp, -- comparator status
|
add_o => alu_add, -- OPA + OPB
|
add_o => alu_add, -- OPA + OPB
|
res_o => alu_res, -- ALU result
|
res_o => alu_res, -- ALU result
|
-- co-processor interface --
|
-- co-processor interface --
|
cp0_data_i => cp0_data, -- co-processor 0 result
|
cp0_data_i => cp0_data, -- co-processor 0 result
|
cp0_valid_i => cp0_valid, -- co-processor 0 result valid
|
cp0_valid_i => cp0_valid, -- co-processor 0 result valid
|
cp1_data_i => cp1_data, -- co-processor 1 result
|
cp1_data_i => cp1_data, -- co-processor 1 result
|
cp1_valid_i => cp1_valid, -- co-processor 1 result valid
|
cp1_valid_i => cp1_valid, -- co-processor 1 result valid
|
-- status --
|
-- status --
|
wait_o => alu_wait -- busy due to iterative processing units
|
wait_o => alu_wait -- busy due to iterative processing units
|
);
|
);
|
|
|
|
|
-- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
|
-- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_muldiv_inst_true:
|
neorv32_cpu_cp_muldiv_inst_true:
|
if (CPU_EXTENSION_RISCV_M = true) generate
|
if (CPU_EXTENSION_RISCV_M = true) generate
|
neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
|
neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
-- data input --
|
-- data input --
|
rs1_i => rs1, -- rf source 1
|
rs1_i => rs1, -- rf source 1
|
rs2_i => rs2, -- rf source 2
|
rs2_i => rs2, -- rf source 2
|
-- result and status --
|
-- result and status --
|
res_o => cp0_data, -- operation result
|
res_o => cp0_data, -- operation result
|
valid_o => cp0_valid -- data output valid
|
valid_o => cp0_valid -- data output valid
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_cp_muldiv_inst_false:
|
neorv32_cpu_cp_muldiv_inst_false:
|
if (CPU_EXTENSION_RISCV_M = false) generate
|
if (CPU_EXTENSION_RISCV_M = false) generate
|
cp0_data <= (others => '0');
|
cp0_data <= (others => '0');
|
cp0_valid <= '0';
|
cp0_valid <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
-- Co-Processor 1: Not Implemented Yet ----------------------------------------------------
|
-- Co-Processor 1: Not Implemented Yet ----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
cp1_data <= (others => '0');
|
cp1_data <= (others => '0');
|
cp1_valid <= '0';
|
cp1_valid <= '0';
|
|
|
|
|
-- Bus Unit -------------------------------------------------------------------------------
|
-- Bus Interface Unit ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
-- data input --
|
-- cpu instruction fetch interface --
|
wdata_i => rs2, -- write data
|
fetch_pc_i => fetch_pc, -- PC for instruction fetch
|
pc_i => fetch_pc, -- current PC for instruction fetch
|
|
alu_i => alu_res, -- ALU result
|
|
-- data output --
|
|
instr_o => instr, -- instruction
|
instr_o => instr, -- instruction
|
|
i_wait_o => bus_i_wait, -- wait for fetch to complete
|
|
--
|
|
ma_instr_o => ma_instr, -- misaligned instruction address
|
|
be_instr_o => be_instr, -- bus error on instruction access
|
|
-- cpu data access interface --
|
|
addr_i => alu_add, -- ALU.add result -> access address
|
|
wdata_i => rs2, -- write data
|
rdata_o => rdata, -- read data
|
rdata_o => rdata, -- read data
|
-- status --
|
|
mar_o => mar, -- current memory address register
|
mar_o => mar, -- current memory address register
|
ma_instr_o => ma_instr, -- misaligned instruction address
|
d_wait_o => bus_d_wait, -- wait for access to complete
|
|
--
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_store_o => ma_store, -- misaligned store data address
|
ma_store_o => ma_store, -- misaligned store data address
|
be_instr_o => be_instr, -- bus error on instruction access
|
|
be_load_o => be_load, -- bus error on load data access
|
be_load_o => be_load, -- bus error on load data access
|
be_store_o => be_store, -- bus error on store data access
|
be_store_o => be_store, -- bus error on store data access
|
bus_wait_o => bus_wait, -- wait for bus operation to finish
|
-- instruction bus --
|
bus_busy_o => bus_busy, -- bus unit is busy
|
i_bus_addr_o => i_bus_addr_o, -- bus access address
|
-- bus system --
|
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
bus_addr_o => bus_addr_o, -- bus access address
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
bus_rdata_i => bus_rdata_i, -- bus read data
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
bus_wdata_o => bus_wdata_o, -- bus write data
|
i_bus_we_o => i_bus_we_o, -- write enable
|
bus_ben_o => bus_ben_o, -- byte enable
|
i_bus_re_o => i_bus_re_o, -- read enable
|
bus_we_o => bus_we_o, -- write enable
|
i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
|
bus_re_o => bus_re_o, -- read enable
|
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
|
bus_cancel_o => bus_cancel_o, -- cancel current bus transaction
|
i_bus_err_i => i_bus_err_i, -- bus transfer error
|
bus_ack_i => bus_ack_i, -- bus transfer acknowledge
|
i_bus_fence_o => i_bus_fence_o, -- fence operation
|
bus_err_i => bus_err_i -- bus transfer error
|
-- data bus --
|
|
d_bus_addr_o => d_bus_addr_o, -- bus access address
|
|
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
|
|
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
|
|
d_bus_ben_o => d_bus_ben_o, -- byte enable
|
|
d_bus_we_o => d_bus_we_o, -- write enable
|
|
d_bus_re_o => d_bus_re_o, -- read enable
|
|
d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
|
|
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
|
|
d_bus_err_i => d_bus_err_i, -- bus transfer error
|
|
d_bus_fence_o => d_bus_fence_o -- fence operation
|
);
|
);
|
|
|
|
|
end neorv32_cpu_rtl;
|
end neorv32_cpu_rtl;
|
|
|