-- #################################################################################################
|
-- #################################################################################################
|
-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter. #
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-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter. #
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-- # The shifter sub-unit uses an iterative approach. #
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-- # The shifter sub-unit uses an iterative approach. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
|
-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
|
-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
-- # endorse or promote products derived from this software without specific prior written #
|
-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
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|
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_alu is
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entity neorv32_cpu_alu is
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generic (
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generic (
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CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
|
);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- co-processor interface --
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-- co-processor interface --
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cp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand a
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cp_opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand b
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
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cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
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cp1_start_o : out std_ulogic; -- trigger co-processor 1
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cp1_start_o : out std_ulogic; -- trigger co-processor 1
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cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
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cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
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cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
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cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
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-- status --
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-- status --
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wait_o : out std_ulogic -- busy due to iterative processing units
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wait_o : out std_ulogic -- busy due to iterative processing units
|
);
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);
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end neorv32_cpu_alu;
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end neorv32_cpu_alu;
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|
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
|
|
|
-- operands --
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-- operands --
|
signal opa, opb, opc : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb, opc : std_ulogic_vector(data_width_c-1 downto 0);
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|
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-- results --
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-- results --
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signal add_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal add_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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|
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-- comparator --
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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signal sub_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal sub_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cmp_equal : std_ulogic;
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signal cmp_equal : std_ulogic;
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signal cmp_less : std_ulogic;
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signal cmp_less : std_ulogic;
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|
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-- shifter --
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-- shifter --
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type shifter_t is record
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type shifter_t is record
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cmd : std_ulogic;
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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cmd_ff : std_ulogic;
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start : std_ulogic;
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start : std_ulogic;
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run : std_ulogic;
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run : std_ulogic;
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halt : std_ulogic;
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halt : std_ulogic;
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cnt : std_ulogic_vector(4 downto 0);
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cnt : std_ulogic_vector(4 downto 0);
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sreg : std_ulogic_vector(data_width_c-1 downto 0);
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sreg : std_ulogic_vector(data_width_c-1 downto 0);
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end record;
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end record;
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signal shifter : shifter_t;
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signal shifter : shifter_t;
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|
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-- co-processor arbiter and interface --
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-- co-processor arbiter and interface --
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type cp_ctrl_t is record
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type cp_ctrl_t is record
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cmd_ff : std_ulogic;
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cmd_ff : std_ulogic;
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busy : std_ulogic;
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busy : std_ulogic;
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start : std_ulogic;
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start : std_ulogic;
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halt : std_ulogic;
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halt : std_ulogic;
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rb_ff0 : std_ulogic;
|
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rb_ff1 : std_ulogic;
|
|
end record;
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end record;
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signal cp_ctrl : cp_ctrl_t;
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signal cp_ctrl : cp_ctrl_t;
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|
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-- bit manipulation --
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signal bitm_res : std_ulogic_vector(31 downto 0);
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|
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begin
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begin
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|
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-- Operand Mux ----------------------------------------------------------------------------
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-- Operand Mux ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
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input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
|
begin
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begin
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-- opa (first ALU input operand) --
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-- opa (first ALU input operand) --
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case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is
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case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is
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when "00" => opa <= rs1_i;
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when "00" => opa <= rs1_i;
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when "01" => opa <= pc2_i;
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when "01" => opa <= pc2_i;
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when others => opa <= csr_i;
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when others => opa <= csr_i;
|
end case;
|
end case;
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-- opb (second ALU input operand) --
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-- opb (second ALU input operand) --
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case ctrl_i(ctrl_alu_opb_mux_msb_c downto ctrl_alu_opb_mux_lsb_c) is
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case ctrl_i(ctrl_alu_opb_mux_msb_c downto ctrl_alu_opb_mux_lsb_c) is
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when "00" => opb <= rs2_i;
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when "00" => opb <= rs2_i;
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when "01" => opb <= imm_i;
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when "01" => opb <= imm_i;
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when others => opb <= rs1_i;
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when others => opb <= rs1_i;
|
end case;
|
end case;
|
-- opc (second operand for comparison and SUB) --
|
-- opc (second operand for comparison and SUB) --
|
if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
|
if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
|
opc <= imm_i;
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opc <= imm_i;
|
else
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else
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opc <= rs2_i;
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opc <= rs2_i;
|
end if;
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end if;
|
end process input_op_mux;
|
end process input_op_mux;
|
|
|
|
|
-- Comparator Unit ------------------------------------------------------------------------
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-- Comparator Unit ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- less than (x < y) --
|
-- less than (x < y) --
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
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cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
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cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
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cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
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cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
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cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
|
sub_res <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
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sub_res <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
|
|
|
-- equal (x = y) --
|
-- equal (x = y) --
|
cmp_equal <= '1' when (rs1_i = opc) else '0';
|
cmp_equal <= '1' when (rs1_i = opc) else '0';
|
|
|
-- output for branch condition evaluation -
|
-- output for branch condition evaluation -
|
cmp_o(alu_cmp_equal_c) <= cmp_equal;
|
cmp_o(alu_cmp_equal_c) <= cmp_equal;
|
cmp_o(alu_cmp_less_c) <= cmp_less;
|
cmp_o(alu_cmp_less_c) <= cmp_less;
|
|
|
|
|
-- Binary Adder ---------------------------------------------------------------------------
|
-- Binary Adder ---------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
|
add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
|
add_o <= add_res; -- direct output
|
add_o <= add_res; -- direct output
|
|
|
|
|
-- Bit Manipulation Unit ------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
|
|
-- ------------------ --
|
|
-- UNDER CONSTRUCTION --
|
|
-- ------------------ --
|
|
|
|
--bitm_minmax <= rs1_i when ((cmp_less xor ???) = '1') else rs2_i; -- min[u] / max[u]
|
|
|
|
-- result of bit manipulation operation --
|
|
bitm_res <= opa and (not opb); -- ANDN
|
|
|
|
|
|
-- Iterative Shifter Unit -----------------------------------------------------------------
|
-- Iterative Shifter Unit -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
shifter_unit: process(rstn_i, clk_i)
|
shifter_unit: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
shifter.sreg <= (others => '0');
|
shifter.sreg <= (others => '0');
|
shifter.cnt <= (others => '0');
|
shifter.cnt <= (others => '0');
|
shifter.cmd_ff <= '0';
|
shifter.cmd_ff <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
shifter.cmd_ff <= shifter.cmd;
|
shifter.cmd_ff <= shifter.cmd;
|
if (shifter.start = '1') then -- trigger new shift
|
if (shifter.start = '1') then -- trigger new shift
|
shifter.sreg <= opa; -- shift operand
|
shifter.sreg <= opa; -- shift operand
|
shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
|
shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
|
elsif (shifter.run = '1') then -- running shift
|
elsif (shifter.run = '1') then -- running shift
|
-- coarse shift: multiples of 4 --
|
-- coarse shift: multiples of 4 --
|
if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
|
if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
|
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
|
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
|
shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
|
shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
|
else -- SRL: shift right logical / SRA: shift right arithmetical
|
else -- SRL: shift right logical / SRA: shift right arithmetical
|
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
|
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
|
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
|
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
|
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
|
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
|
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
|
(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
|
end if;
|
end if;
|
-- fine shift: single shifts, 0..3 times --
|
-- fine shift: single shifts, 0..3 times --
|
else
|
else
|
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
|
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
|
if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
|
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
|
shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
|
else -- SRL: shift right logical / SRA: shift right arithmetical
|
else -- SRL: shift right logical / SRA: shift right arithmetical
|
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
|
shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process shifter_unit;
|
end process shifter_unit;
|
|
|
-- is shift operation? --
|
-- is shift operation? --
|
shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) and (ctrl_i(ctrl_cp_use_c) = '0') else '0';
|
shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) and (ctrl_i(ctrl_cp_use_c) = '0') else '0';
|
shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
|
shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
|
|
|
-- shift operation running? --
|
-- shift operation running? --
|
shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
|
shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
|
shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
|
shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
|
|
|
|
|
-- Coprocessor Arbiter --------------------------------------------------------------------
|
-- Coprocessor Arbiter --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cp_arbiter: process(rstn_i, clk_i)
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cp_arbiter: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.rb_ff0 <= '0';
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cp_ctrl.rb_ff1 <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (CPU_EXTENSION_RISCV_M = true) then
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if (CPU_EXTENSION_RISCV_M = true) then
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cp_ctrl.cmd_ff <= ctrl_i(ctrl_cp_use_c);
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cp_ctrl.cmd_ff <= ctrl_i(ctrl_cp_use_c);
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cp_ctrl.rb_ff0 <= '0';
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cp_ctrl.rb_ff1 <= cp_ctrl.rb_ff0;
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if (cp_ctrl.start = '1') then
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if (cp_ctrl.start = '1') then
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cp_ctrl.busy <= '1';
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cp_ctrl.busy <= '1';
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elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done?
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elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done?
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.rb_ff0 <= '1';
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end if;
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end if;
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else -- no co-processor(s) implemented
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else -- no co-processor(s) implemented
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.rb_ff0 <= '0';
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cp_ctrl.rb_ff1 <= '0';
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end if;
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end if;
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end if;
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end if;
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end process cp_arbiter;
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end process cp_arbiter;
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|
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-- is co-processor operation? --
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-- is co-processor operation? --
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cp_ctrl.start <= '1' when (ctrl_i(ctrl_cp_use_c) = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp_ctrl.start <= '1' when (ctrl_i(ctrl_cp_use_c) = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) else '0'; -- MULDIV CP
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cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) else '0'; -- MULDIV CP
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cp1_start_o <= '0'; -- not yet implemented
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cp1_start_o <= '0'; -- not yet implemented
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|
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-- co-processor operation running? --
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-- co-processor operation running? --
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cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
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cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
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|
|
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-- co-processor operands --
|
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cp_opa_o <= opa;
|
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cp_opb_o <= opb;
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|
|
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-- co-processor result --
|
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cp_res <= cp0_data_i or cp1_data_i; -- only the selcted cp may output data != 0
|
|
|
|
|
-- ALU Function Select --------------------------------------------------------------------
|
-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter, bitm_res)
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alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter)
|
begin
|
begin
|
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
|
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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when alu_cmd_bitm_c => alu_res <= bitm_res;
|
|
when alu_cmd_xor_c => alu_res <= opa xor opb;
|
when alu_cmd_xor_c => alu_res <= opa xor opb;
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when alu_cmd_or_c => alu_res <= opa or opb;
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when alu_cmd_or_c => alu_res <= opa or opb;
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when alu_cmd_and_c => alu_res <= opa and opb;
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when alu_cmd_and_c => alu_res <= opa and opb;
|
|
when alu_cmd_bclr_c => alu_res <= opa and (not opb);
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when alu_cmd_sub_c => alu_res <= sub_res;
|
when alu_cmd_sub_c => alu_res <= sub_res;
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when alu_cmd_add_c => alu_res <= add_res;
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when alu_cmd_add_c => alu_res <= add_res;
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when alu_cmd_shift_c => alu_res <= shifter.sreg;
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when alu_cmd_shift_c => alu_res <= shifter.sreg;
|
when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
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when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
|
when others => alu_res <= (others => '0'); -- undefined
|
when others => alu_res <= (others => '0'); -- undefined
|
end case;
|
end case;
|
end process alu_function_mux;
|
end process alu_function_mux;
|
|
|
|
|
-- ALU Result -----------------------------------------------------------------------------
|
-- ALU Result -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
wait_o <= shifter.halt or cp_ctrl.halt; -- wait until iterative units have completed
|
wait_o <= shifter.halt or cp_ctrl.halt; -- wait until iterative units have completed
|
res_o <= (cp0_data_i or cp1_data_i) when (cp_ctrl.rb_ff1 = '1') else alu_res; -- FIXME
|
res_o <= cp_res when (ctrl_i(ctrl_cp_use_c) = '1') else alu_res; -- FIXME?
|
|
|
|
|
end neorv32_cpu_cpu_rtl;
|
end neorv32_cpu_cpu_rtl;
|
|
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