-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Main data and address ALU and co-processor interface/arbiter. #
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-- # Main data and address ALU and co-processor interface/arbiter. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_alu is
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entity neorv32_cpu_alu is
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generic (
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generic (
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
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CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
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CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
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CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
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fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
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-- status --
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-- status --
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idone_o : out std_ulogic -- iterative processing units done?
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idone_o : out std_ulogic -- iterative processing units done?
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);
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);
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end neorv32_cpu_alu;
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end neorv32_cpu_alu;
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp : std_ulogic_vector(1 downto 0); -- comparator status
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-- operands --
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-- operands --
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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-- results --
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-- results --
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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--
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--
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- co-processor arbiter and interface --
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-- co-processor arbiter and interface --
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type cp_ctrl_t is record
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type cp_ctrl_t is record
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cmd : std_ulogic;
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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cmd_ff : std_ulogic;
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start : std_ulogic;
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start : std_ulogic;
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busy : std_ulogic;
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busy : std_ulogic;
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timeout : std_ulogic_vector(9 downto 0);
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timeout : std_ulogic_vector(9 downto 0);
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end record;
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end record;
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signal cp_ctrl : cp_ctrl_t;
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signal cp_ctrl : cp_ctrl_t;
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-- co-processor interface --
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-- co-processor interface --
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signal cp_start : std_ulogic_vector(3 downto 0); -- trigger co-processor i
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signal cp_start : std_ulogic_vector(3 downto 0); -- trigger co-processor i
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signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done
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signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done
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signal cp_result : cp_data_if_t; -- co-processor result
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signal cp_result : cp_data_if_t; -- co-processor result
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begin
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begin
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-- Operand Mux ----------------------------------------------------------------------------
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-- Comparator Unit (for conditional branches) ---------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opy <= (rs2_i(rs2_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2_i;
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cmp(cmp_equal_c) <= '1' when (rs1_i = rs2_i) else '0';
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cmp(cmp_less_c) <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0';
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cmp_o <= cmp;
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-- ALU Input Operand Mux ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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-- Binary Adder/Subtracter ----------------------------------------------------------------
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-- Binary Adder/Subtracter ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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binary_arithmetic_core: process(ctrl_i, opa, opb)
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binary_arithmetic_core: process(ctrl_i, opa, opb)
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variable cin_v : std_ulogic_vector(0 downto 0);
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variable cin_v : std_ulogic_vector(0 downto 0);
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variable op_a_v : std_ulogic_vector(data_width_c downto 0);
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variable op_a_v : std_ulogic_vector(data_width_c downto 0);
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variable op_b_v : std_ulogic_vector(data_width_c downto 0);
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variable op_b_v : std_ulogic_vector(data_width_c downto 0);
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variable op_y_v : std_ulogic_vector(data_width_c downto 0);
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variable op_y_v : std_ulogic_vector(data_width_c downto 0);
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variable res_v : std_ulogic_vector(data_width_c downto 0);
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variable res_v : std_ulogic_vector(data_width_c downto 0);
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begin
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begin
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-- operand sign-extension --
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-- operand sign-extension --
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op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
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op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
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op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
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op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
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-- add/sub(slt) select --
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-- add/sub(slt) select --
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if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction
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if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction
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op_y_v := not op_b_v;
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op_y_v := not op_b_v;
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cin_v(0) := '1';
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cin_v(0) := '1';
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else -- addition
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else -- addition
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op_y_v := op_b_v;
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op_y_v := op_b_v;
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cin_v(0) := '0';
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cin_v(0) := '0';
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end if;
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end if;
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-- adder core (result + carry/borrow) --
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-- adder core (result + carry/borrow) --
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addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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end process binary_arithmetic_core;
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end process binary_arithmetic_core;
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-- direct output of address result --
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-- direct output of address result --
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add_o <= addsub_res(data_width_c-1 downto 0);
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add_o <= addsub_res(data_width_c-1 downto 0);
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-- ALU arithmetic logic core --
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-- ALU arithmetic logic core --
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arithmetic_core: process(ctrl_i, addsub_res)
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arithmetic_core: process(ctrl_i, addsub_res)
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begin
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begin
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if (ctrl_i(ctrl_alu_arith_c) = alu_arith_cmd_addsub_c) then -- ADD/SUB
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if (ctrl_i(ctrl_alu_arith_c) = alu_arith_cmd_addsub_c) then -- ADD/SUB
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arith_res <= addsub_res(data_width_c-1 downto 0);
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arith_res <= addsub_res(data_width_c-1 downto 0);
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else -- SLT
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else -- SLT
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arith_res <= (others => '0');
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arith_res <= (others => '0');
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arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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end if;
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end if;
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end process arithmetic_core;
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end process arithmetic_core;
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-- Co-Processor Arbiter -------------------------------------------------------------------
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-- Co-Processor Arbiter -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Interface:
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-- Interface:
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-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
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-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
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-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
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-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
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cp_arbiter: process(rstn_i, clk_i)
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cp_arbiter: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.timeout <= (others => '0');
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cp_ctrl.timeout <= (others => '0');
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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-- timeout counter --
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-- timeout counter --
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if (cp_ctrl.start = '1') then
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if (cp_ctrl.start = '1') then
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cp_ctrl.busy <= '1';
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cp_ctrl.busy <= '1';
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elsif (or_reduce_f(cp_valid) = '1') then
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elsif (or_reduce_f(cp_valid) = '1') then
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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end if;
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end if;
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if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
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if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
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cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
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cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
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else
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else
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cp_ctrl.timeout <= (others => '0');
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cp_ctrl.timeout <= (others => '0');
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end if;
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end if;
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if (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
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if (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
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assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
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assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
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end if;
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end if;
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end if;
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end if;
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end process cp_arbiter;
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end process cp_arbiter;
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-- is co-processor operation? --
|
-- is co-processor operation? --
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0';
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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|
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-- co-processor select / star trigger --
|
-- co-processor select / star trigger --
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cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
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cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
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cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
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cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
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cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0';
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cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0';
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cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0';
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cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0';
|
|
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-- co-processor operation done? --
|
-- co-processor operation done? --
|
idone_o <= or_reduce_f(cp_valid);
|
idone_o <= or_reduce_f(cp_valid);
|
|
|
-- co-processor result - only the *actually selected* co-processor may output data != 0 --
|
-- co-processor result - only the *actually selected* co-processor may output data != 0 --
|
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3);
|
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3);
|
|
|
|
|
-- ALU Logic Core -------------------------------------------------------------------------
|
-- ALU Logic Core -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
alu_logic_core: process(ctrl_i, rs1_i, opb)
|
alu_logic_core: process(ctrl_i, rs1_i, opb)
|
begin
|
begin
|
case ctrl_i(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) is
|
case ctrl_i(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) is
|
when alu_logic_cmd_movb_c => logic_res <= opb; -- (default)
|
when alu_logic_cmd_movb_c => logic_res <= opb; -- (default)
|
when alu_logic_cmd_xor_c => logic_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
|
when alu_logic_cmd_xor_c => logic_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
|
when alu_logic_cmd_or_c => logic_res <= rs1_i or opb;
|
when alu_logic_cmd_or_c => logic_res <= rs1_i or opb;
|
when alu_logic_cmd_and_c => logic_res <= rs1_i and opb;
|
when alu_logic_cmd_and_c => logic_res <= rs1_i and opb;
|
when others => logic_res <= opb; -- undefined
|
when others => logic_res <= opb; -- undefined
|
end case;
|
end case;
|
end process alu_logic_core;
|
end process alu_logic_core;
|
|
|
|
|
-- ALU Function Select --------------------------------------------------------------------
|
-- ALU Function Select --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
alu_function_mux: process(ctrl_i, arith_res, logic_res, csr_i, cp_res)
|
alu_function_mux: process(ctrl_i, arith_res, logic_res, csr_i, cp_res)
|
begin
|
begin
|
case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
|
case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
|
when alu_func_cmd_arith_c => res_o <= arith_res; -- (default)
|
when alu_func_cmd_arith_c => res_o <= arith_res; -- (default)
|
when alu_func_cmd_logic_c => res_o <= logic_res;
|
when alu_func_cmd_logic_c => res_o <= logic_res;
|
when alu_func_cmd_csrr_c => res_o <= csr_i;
|
when alu_func_cmd_csrr_c => res_o <= csr_i;
|
when alu_func_cmd_copro_c => res_o <= cp_res;
|
when alu_func_cmd_copro_c => res_o <= cp_res;
|
when others => res_o <= arith_res; -- undefined
|
when others => res_o <= arith_res; -- undefined
|
end case;
|
end case;
|
end process alu_function_mux;
|
end process alu_function_mux;
|
|
|
|
|
-- **************************************************************************************************************************
|
-- **************************************************************************************************************************
|
-- Co-Processors
|
-- Co-Processors
|
-- **************************************************************************************************************************
|
-- **************************************************************************************************************************
|
|
|
-- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
|
-- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
|
neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
|
generic map (
|
generic map (
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl_i, -- main control bus
|
ctrl_i => ctrl_i, -- main control bus
|
start_i => cp_start(0), -- trigger operation
|
start_i => cp_start(0), -- trigger operation
|
-- data input --
|
-- data input --
|
rs1_i => rs1_i, -- rf source 1
|
rs1_i => rs1_i, -- rf source 1
|
rs2_i => rs2_i, -- rf source 2
|
rs2_i => rs2_i, -- rf source 2
|
imm_i => imm_i, -- immediate
|
imm_i => imm_i, -- immediate
|
-- result and status --
|
-- result and status --
|
res_o => cp_result(0), -- operation result
|
res_o => cp_result(0), -- operation result
|
valid_o => cp_valid(0) -- data output valid
|
valid_o => cp_valid(0) -- data output valid
|
);
|
);
|
|
|
|
|
-- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------
|
-- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_muldiv_inst_true:
|
neorv32_cpu_cp_muldiv_inst_true:
|
if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate
|
if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate
|
neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
|
neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
|
generic map (
|
generic map (
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for faster multiplication
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for faster multiplication
|
DIVISION_EN => CPU_EXTENSION_RISCV_M -- implement divider hardware
|
DIVISION_EN => CPU_EXTENSION_RISCV_M -- implement divider hardware
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl_i, -- main control bus
|
ctrl_i => ctrl_i, -- main control bus
|
start_i => cp_start(1), -- trigger operation
|
start_i => cp_start(1), -- trigger operation
|
-- data input --
|
-- data input --
|
rs1_i => rs1_i, -- rf source 1
|
rs1_i => rs1_i, -- rf source 1
|
rs2_i => rs2_i, -- rf source 2
|
rs2_i => rs2_i, -- rf source 2
|
-- result and status --
|
-- result and status --
|
res_o => cp_result(1), -- operation result
|
res_o => cp_result(1), -- operation result
|
valid_o => cp_valid(1) -- data output valid
|
valid_o => cp_valid(1) -- data output valid
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_cp_muldiv_inst_false:
|
neorv32_cpu_cp_muldiv_inst_false:
|
if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate
|
if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate
|
cp_result(1) <= (others => '0');
|
cp_result(1) <= (others => '0');
|
cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
|
end generate;
|
end generate;
|
|
|
|
|
-- Co-Processor 2: Bit-Manipulation Unit ('Zbb' Extension) --------------------------------
|
-- Co-Processor 2: Bit-Manipulation Unit ('B'/'Zbb' Extension) ----------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_bitmanip_inst_true:
|
neorv32_cpu_cp_bitmanip_inst_true:
|
if (CPU_EXTENSION_RISCV_Zbb = true) generate
|
if (CPU_EXTENSION_RISCV_Zbb = true) generate
|
neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
|
neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
|
generic map (
|
generic map (
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl_i, -- main control bus
|
ctrl_i => ctrl_i, -- main control bus
|
start_i => cp_start(2), -- trigger operation
|
start_i => cp_start(2), -- trigger operation
|
-- data input --
|
-- data input --
|
cmp_i => cmp_i, -- comparator status
|
cmp_i => cmp, -- comparator status
|
rs1_i => rs1_i, -- rf source 1
|
rs1_i => rs1_i, -- rf source 1
|
rs2_i => rs2_i, -- rf source 2
|
rs2_i => rs2_i, -- rf source 2
|
-- result and status --
|
-- result and status --
|
res_o => cp_result(2), -- operation result
|
res_o => cp_result(2), -- operation result
|
valid_o => cp_valid(2) -- data output valid
|
valid_o => cp_valid(2) -- data output valid
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_cp_bitmanip_inst_false:
|
neorv32_cpu_cp_bitmanip_inst_false:
|
if (CPU_EXTENSION_RISCV_Zbb = false) generate
|
if (CPU_EXTENSION_RISCV_Zbb = false) generate
|
cp_result(2) <= (others => '0');
|
cp_result(2) <= (others => '0');
|
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
|
end generate;
|
end generate;
|
|
|
|
|
-- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
|
-- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_fpu_inst_true:
|
neorv32_cpu_cp_fpu_inst_true:
|
if (CPU_EXTENSION_RISCV_Zfinx = true) generate
|
if (CPU_EXTENSION_RISCV_Zfinx = true) generate
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl_i, -- main control bus
|
ctrl_i => ctrl_i, -- main control bus
|
start_i => cp_start(3), -- trigger operation
|
start_i => cp_start(3), -- trigger operation
|
-- data input --
|
-- data input --
|
cmp_i => cmp_i, -- comparator status
|
cmp_i => cmp, -- comparator status
|
rs1_i => rs1_i, -- rf source 1
|
rs1_i => rs1_i, -- rf source 1
|
rs2_i => rs2_i, -- rf source 2
|
rs2_i => rs2_i, -- rf source 2
|
-- result and status --
|
-- result and status --
|
res_o => cp_result(3), -- operation result
|
res_o => cp_result(3), -- operation result
|
fflags_o => fpu_flags_o, -- exception flags
|
fflags_o => fpu_flags_o, -- exception flags
|
valid_o => cp_valid(3) -- data output valid
|
valid_o => cp_valid(3) -- data output valid
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_cp_fpu_inst_false:
|
neorv32_cpu_cp_fpu_inst_false:
|
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
|
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
|
cp_result(3) <= (others => '0');
|
cp_result(3) <= (others => '0');
|
fpu_flags_o <= (others => '0');
|
fpu_flags_o <= (others => '0');
|
cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access
|
end generate;
|
end generate;
|
|
|
|
|
end neorv32_cpu_cpu_rtl;
|
end neorv32_cpu_cpu_rtl;
|
|
|
