-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Instruction and data bus interfaces. #
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-- # Instruction and data bus interfaces. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- cpu instruction fetch interface --
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-- cpu instruction fetch interface --
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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--
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--
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_instr_o : out std_ulogic; -- bus error on instruction access
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-- cpu data access interface --
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-- cpu data access interface --
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addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
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addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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d_wait_o : out std_ulogic; -- wait for access to complete
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d_wait_o : out std_ulogic; -- wait for access to complete
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--
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--
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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-- instruction bus --
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-- instruction bus --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- fence operation
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i_bus_fence_o : out std_ulogic; -- fence operation
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-- data bus --
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-- data bus --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic -- fence operation
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d_bus_fence_o : out std_ulogic -- fence operation
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);
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);
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end neorv32_cpu_bus;
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end neorv32_cpu_bus;
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|
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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-- data interface registers --
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-- data interface registers --
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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-- data access --
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-- data access --
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signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
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signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
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signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
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signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
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-- misaligned access? --
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-- misaligned access? --
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signal d_misaligned, i_misaligned : std_ulogic;
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signal d_misaligned, i_misaligned : std_ulogic;
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-- bus arbiter --
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-- bus arbiter --
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type bus_arbiter_t is record
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type bus_arbiter_t is record
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rd_req : std_ulogic; -- read access in progress
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rd_req : std_ulogic; -- read access in progress
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wr_req : std_ulogic; -- write access in progress
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wr_req : std_ulogic; -- write access in progress
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err_align : std_ulogic; -- alignment error
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err_align : std_ulogic; -- alignment error
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err_bus : std_ulogic; -- bus access error
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err_bus : std_ulogic; -- bus access error
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timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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end record;
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end record;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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begin
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begin
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-- Data Interface: Access Address ---------------------------------------------------------
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-- Data Interface: Access Address ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_adr_reg: process(rstn_i, clk_i)
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mem_adr_reg: process(rstn_i, clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
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mar <= addr_i;
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mar <= addr_i;
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end if;
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end if;
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end if;
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end if;
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end process mem_adr_reg;
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end process mem_adr_reg;
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-- read-back for exception controller --
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-- read-back for exception controller --
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mar_o <= mar;
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mar_o <= mar;
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-- alignment check --
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-- alignment check --
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misaligned_d_check: process(mar, ctrl_i)
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misaligned_d_check: process(mar, ctrl_i)
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begin
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begin
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-- check data access --
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-- check data access --
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d_misaligned <= '0'; -- default
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d_misaligned <= '0'; -- default
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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when "00" => -- byte
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when "00" => -- byte
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d_misaligned <= '0';
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d_misaligned <= '0';
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when "01" => -- half-word
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when "01" => -- half-word
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if (mar(0) /= '0') then
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if (mar(0) /= '0') then
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d_misaligned <= '1';
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d_misaligned <= '1';
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end if;
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end if;
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when others => -- word
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when others => -- word
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if (mar(1 downto 0) /= "00") then
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if (mar(1 downto 0) /= "00") then
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d_misaligned <= '1';
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d_misaligned <= '1';
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end if;
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end if;
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end case;
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end case;
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end process misaligned_d_check;
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end process misaligned_d_check;
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-- Data Interface: Write Data -------------------------------------------------------------
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-- Data Interface: Write Data -------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_do_reg: process(clk_i)
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mem_do_reg: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
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mdo <= wdata_i;
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mdo <= wdata_i;
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end if;
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end if;
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end if;
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end if;
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end process mem_do_reg;
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end process mem_do_reg;
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-- byte enable and output data alignment --
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-- byte enable and output data alignment --
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byte_enable: process(mar, mdo, ctrl_i)
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byte_enable: process(mar, mdo, ctrl_i)
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begin
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begin
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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when "00" => -- byte
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when "00" => -- byte
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d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
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d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
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d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
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d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
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d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
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d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
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d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
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d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
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d_bus_ben <= (others => '0');
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d_bus_ben <= (others => '0');
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d_bus_ben(to_integer(unsigned(mar(1 downto 0)))) <= '1';
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d_bus_ben(to_integer(unsigned(mar(1 downto 0)))) <= '1';
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when "01" => -- half-word
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when "01" => -- half-word
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d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
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d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
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d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
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d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
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if (mar(1) = '0') then
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if (mar(1) = '0') then
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d_bus_ben <= "0011"; -- low half-word
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d_bus_ben <= "0011"; -- low half-word
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else
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else
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d_bus_ben <= "1100"; -- high half-word
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d_bus_ben <= "1100"; -- high half-word
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end if;
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end if;
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when others => -- word
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when others => -- word
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d_bus_wdata <= mdo;
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d_bus_wdata <= mdo;
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d_bus_ben <= "1111"; -- full word
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d_bus_ben <= "1111"; -- full word
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end case;
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end case;
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end process byte_enable;
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end process byte_enable;
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-- Data Interface: Read Data --------------------------------------------------------------
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-- Data Interface: Read Data --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_out_buf: process(clk_i)
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mem_out_buf: process(clk_i)
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begin
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begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- memory data in register (MDI) --
|
-- memory data in register (MDI) --
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if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
|
mdi <= d_bus_rdata;
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mdi <= d_bus_rdata;
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end if;
|
end if;
|
end if;
|
end if;
|
end process mem_out_buf;
|
end process mem_out_buf;
|
|
|
-- input data alignment and sign extension --
|
-- input data alignment and sign extension --
|
read_align: process(mdi, mar, ctrl_i)
|
read_align: process(mdi, mar, ctrl_i)
|
variable signed_v : std_ulogic;
|
variable signed_v : std_ulogic;
|
begin
|
begin
|
signed_v := not ctrl_i(ctrl_bus_unsigned_c);
|
signed_v := not ctrl_i(ctrl_bus_unsigned_c);
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
when "00" => -- byte
|
when "00" => -- byte
|
case mar(1 downto 0) is
|
case mar(1 downto 0) is
|
when "00" =>
|
when "00" =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(07)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(07)));
|
rdata_o(07 downto 00) <= mdi(07 downto 00); -- byte 0
|
rdata_o(07 downto 00) <= mdi(07 downto 00); -- byte 0
|
when "01" =>
|
when "01" =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(15)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(15)));
|
rdata_o(07 downto 00) <= mdi(15 downto 08); -- byte 1
|
rdata_o(07 downto 00) <= mdi(15 downto 08); -- byte 1
|
when "10" =>
|
when "10" =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(23)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(23)));
|
rdata_o(07 downto 00) <= mdi(23 downto 16); -- byte 2
|
rdata_o(07 downto 00) <= mdi(23 downto 16); -- byte 2
|
when others =>
|
when others =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(31)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(31)));
|
rdata_o(07 downto 00) <= mdi(31 downto 24); -- byte 3
|
rdata_o(07 downto 00) <= mdi(31 downto 24); -- byte 3
|
end case;
|
end case;
|
when "01" => -- half-word
|
when "01" => -- half-word
|
if (mar(1) = '0') then
|
if (mar(1) = '0') then
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(15)));
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(15)));
|
rdata_o(15 downto 00) <= mdi(15 downto 00); -- low half-word
|
rdata_o(15 downto 00) <= mdi(15 downto 00); -- low half-word
|
else
|
else
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(31)));
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(31)));
|
rdata_o(15 downto 00) <= mdi(31 downto 16); -- high half-word
|
rdata_o(15 downto 00) <= mdi(31 downto 16); -- high half-word
|
end if;
|
end if;
|
when others => -- word
|
when others => -- word
|
rdata_o <= mdi; -- full word
|
rdata_o <= mdi; -- full word
|
end case;
|
end case;
|
end process read_align;
|
end process read_align;
|
|
|
|
|
-- Instruction Interface: Check for Misaligned Access -------------------------------------
|
-- Instruction Interface: Check for Misaligned Access -------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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misaligned_i_check: process(ctrl_i, fetch_pc_i)
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misaligned_i_check: process(ctrl_i, fetch_pc_i)
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begin
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begin
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-- check instruction access --
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-- check instruction access --
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i_misaligned <= '0'; -- default
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i_misaligned <= '0'; -- default
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if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
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if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
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i_misaligned <= '0'; -- no alignment exceptions possible
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i_misaligned <= '0'; -- no alignment exceptions possible
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else -- 32-bit instruction accesses only
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else -- 32-bit instruction accesses only
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if (fetch_pc_i(1) = '1') then -- PC(0) is always zero
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if (fetch_pc_i(1) = '1') then -- PC(0) is always zero
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i_misaligned <= '1';
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i_misaligned <= '1';
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end if;
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end if;
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end if;
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end if;
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end process misaligned_i_check;
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end process misaligned_i_check;
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ifetch_arbiter: process(rstn_i, clk_i)
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ifetch_arbiter: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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i_arbiter.rd_req <= '0';
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i_arbiter.rd_req <= '0';
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i_arbiter.wr_req <= '0';
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i_arbiter.wr_req <= '0';
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i_arbiter.err_align <= '0';
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i_arbiter.err_align <= '0';
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i_arbiter.err_bus <= '0';
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i_arbiter.err_bus <= '0';
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i_arbiter.timeout <= (others => '0');
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i_arbiter.timeout <= (others => '0');
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
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i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
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|
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-- instruction fetch request --
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-- instruction fetch request --
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if (i_arbiter.rd_req = '0') then -- idle
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if (i_arbiter.rd_req = '0') then -- idle
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i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
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i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
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i_arbiter.err_align <= i_misaligned;
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i_arbiter.err_align <= i_misaligned;
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i_arbiter.err_bus <= '0';
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i_arbiter.err_bus <= '0';
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i_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
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i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
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else -- in progress
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else -- in progress
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i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
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i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
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i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
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if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
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if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error
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if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error
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i_arbiter.rd_req <= '0';
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i_arbiter.rd_req <= '0';
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end if;
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end if;
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elsif (i_bus_ack_i = '1') then -- wait for normal termination
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elsif (i_bus_ack_i = '1') then -- wait for normal termination
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i_arbiter.rd_req <= '0';
|
i_arbiter.rd_req <= '0';
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end if;
|
end if;
|
end if;
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end if;
|
|
|
-- cancel bus access --
|
-- cancel bus access --
|
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
|
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
|
end if;
|
end if;
|
end process ifetch_arbiter;
|
end process ifetch_arbiter;
|
|
|
|
|
-- wait for bus transaction to finish --
|
-- wait for bus transaction to finish --
|
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
|
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
|
|
|
-- output instruction fetch error to controller --
|
-- output instruction fetch error to controller --
|
ma_instr_o <= i_arbiter.err_align;
|
ma_instr_o <= i_arbiter.err_align;
|
be_instr_o <= i_arbiter.err_bus;
|
be_instr_o <= i_arbiter.err_bus;
|
|
|
-- instruction bus (read-only) --
|
-- instruction bus (read-only) --
|
i_bus_addr_o <= fetch_pc_i;
|
i_bus_addr_o <= fetch_pc_i;
|
i_bus_wdata_o <= (others => '0');
|
i_bus_wdata_o <= (others => '0');
|
i_bus_ben_o <= (others => '0');
|
i_bus_ben_o <= (others => '0');
|
i_bus_we_o <= '0';
|
i_bus_we_o <= '0';
|
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned); -- no actual read when misaligned
|
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned); -- no actual read when misaligned
|
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
|
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
|
instr_o <= i_bus_rdata_i;
|
instr_o <= i_bus_rdata_i;
|
|
|
|
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
data_access_arbiter: process(rstn_i, clk_i)
|
data_access_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
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d_arbiter.err_align <= '0';
|
d_arbiter.err_align <= '0';
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d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.timeout <= (others => '0');
|
d_arbiter.timeout <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
|
|
-- data access request --
|
-- data access request --
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.err_align <= d_misaligned;
|
d_arbiter.err_align <= d_misaligned;
|
d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
|
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
else -- in progress
|
else -- in progress
|
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
|
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
|
if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
|
if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error
|
if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
end if;
|
end if;
|
elsif (d_bus_ack_i = '1') then -- wait for normal termination
|
elsif (d_bus_ack_i = '1') then -- wait for normal termination
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- cancel bus access --
|
-- cancel bus access --
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
end if;
|
end if;
|
end process data_access_arbiter;
|
end process data_access_arbiter;
|
|
|
|
|
-- wait for bus transaction to finish --
|
-- wait for bus transaction to finish --
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
|
|
-- output data access error to controller --
|
-- output data access error to controller --
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
|
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
|
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
|
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
|
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
|
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
|
|
|
-- data bus --
|
-- data bus --
|
d_bus_addr_o <= mar;
|
d_bus_addr_o <= mar;
|
d_bus_wdata_o <= d_bus_wdata;
|
d_bus_wdata_o <= d_bus_wdata;
|
d_bus_ben_o <= d_bus_ben;
|
d_bus_ben_o <= d_bus_ben;
|
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned); -- no actual write when misaligned
|
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned); -- no actual write when misaligned
|
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned); -- no actual read when misaligned
|
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned); -- no actual read when misaligned
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_rdata <= d_bus_rdata_i;
|
d_bus_rdata <= d_bus_rdata_i;
|
|
|
|
|
end neorv32_cpu_bus_rtl;
|
end neorv32_cpu_bus_rtl;
|
|
|
