-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Instruction and data bus interfaces and physical memory protection (PMP). #
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-- # Instruction and data bus interfaces and physical memory protection (PMP). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Bus Timeout --
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-- Bus Timeout --
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BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- cpu instruction fetch interface --
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-- cpu instruction fetch interface --
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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--
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--
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_instr_o : out std_ulogic; -- bus error on instruction access
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-- cpu data access interface --
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-- cpu data access interface --
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addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
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addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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d_wait_o : out std_ulogic; -- wait for access to complete
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d_wait_o : out std_ulogic; -- wait for access to complete
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--
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--
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bus_excl_ok_o : out std_ulogic; -- bus exclusive access successful
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bus_excl_ok_o : out std_ulogic; -- bus exclusive access successful
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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-- physical memory protection --
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-- physical memory protection --
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pmp_addr_i : in pmp_addr_if_t; -- addresses
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pmp_addr_i : in pmp_addr_if_t; -- addresses
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pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
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pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
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-- instruction bus --
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-- instruction bus --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- fence operation
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i_bus_fence_o : out std_ulogic; -- fence operation
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-- data bus --
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-- data bus --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- fence operation
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d_bus_fence_o : out std_ulogic; -- fence operation
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d_bus_excl_o : out std_ulogic; -- exclusive access request
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d_bus_excl_o : out std_ulogic; -- exclusive access request
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d_bus_excl_i : in std_ulogic -- state of exclusiv access (set if success)
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d_bus_excl_i : in std_ulogic -- state of exclusiv access (set if success)
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);
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);
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end neorv32_cpu_bus;
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end neorv32_cpu_bus;
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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-- PMP modes --
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-- PMP modes --
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constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
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constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
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--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
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--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
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--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
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--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
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constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
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constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
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-- PMP granularity --
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-- PMP granularity --
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constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY);
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constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY);
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-- PMP configuration register bits --
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-- PMP configuration register bits --
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constant pmp_cfg_r_c : natural := 0; -- read permit
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constant pmp_cfg_r_c : natural := 0; -- read permit
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constant pmp_cfg_w_c : natural := 1; -- write permit
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constant pmp_cfg_w_c : natural := 1; -- write permit
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constant pmp_cfg_x_c : natural := 2; -- execute permit
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constant pmp_cfg_x_c : natural := 2; -- execute permit
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constant pmp_cfg_al_c : natural := 3; -- mode bit low
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constant pmp_cfg_al_c : natural := 3; -- mode bit low
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constant pmp_cfg_ah_c : natural := 4; -- mode bit high
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constant pmp_cfg_ah_c : natural := 4; -- mode bit high
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constant pmp_cfg_l_c : natural := 7; -- locked entry
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constant pmp_cfg_l_c : natural := 7; -- locked entry
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-- data interface registers --
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-- data interface registers --
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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-- data access --
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-- data access --
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signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
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signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
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signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
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signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
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-- misaligned access? --
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-- misaligned access? --
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signal d_misaligned, i_misaligned : std_ulogic;
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signal d_misaligned, i_misaligned : std_ulogic;
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-- bus arbiter --
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-- bus arbiter --
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type bus_arbiter_t is record
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type bus_arbiter_t is record
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rd_req : std_ulogic; -- read access in progress
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rd_req : std_ulogic; -- read access in progress
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wr_req : std_ulogic; -- write access in progress
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wr_req : std_ulogic; -- write access in progress
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err_align : std_ulogic; -- alignment error
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err_align : std_ulogic; -- alignment error
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err_bus : std_ulogic; -- bus access error
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err_bus : std_ulogic; -- bus access error
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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end record;
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end record;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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-- physical memory protection --
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-- physical memory protection --
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type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
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type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
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type pmp_t is record
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type pmp_t is record
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addr_mask : pmp_addr_t;
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addr_mask : pmp_addr_t;
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region_base : pmp_addr_t; -- region config base address
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region_base : pmp_addr_t; -- region config base address
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region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
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region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
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region_d_addr : pmp_addr_t; -- masked data access base address for comparator
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region_d_addr : pmp_addr_t; -- masked data access base address for comparator
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i_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
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i_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
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d_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
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d_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
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if_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
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if_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
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ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
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ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
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st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
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st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
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end record;
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end record;
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signal pmp : pmp_t;
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signal pmp : pmp_t;
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|
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-- memory control signal buffer (when using PMP) --
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-- memory control signal buffer (when using PMP) --
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signal d_bus_we, d_bus_we_buf : std_ulogic;
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signal d_bus_we, d_bus_we_buf : std_ulogic;
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signal d_bus_re, d_bus_re_buf : std_ulogic;
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signal d_bus_re, d_bus_re_buf : std_ulogic;
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signal i_bus_re, i_bus_re_buf : std_ulogic;
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signal i_bus_re, i_bus_re_buf : std_ulogic;
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|
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-- pmp faults anyone? --
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-- pmp faults anyone? --
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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signal ld_pmp_fault : std_ulogic; -- pmp load access fault
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signal ld_pmp_fault : std_ulogic; -- pmp load access fault
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signal st_pmp_fault : std_ulogic; -- pmp store access fault
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signal st_pmp_fault : std_ulogic; -- pmp store access fault
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|
|
begin
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begin
|
|
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
|
assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
|
|
|
|
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-- Data Interface: Access Address ---------------------------------------------------------
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-- Data Interface: Access Address ---------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_adr_reg: process(clk_i)
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mem_adr_reg: process(rstn_i, clk_i)
|
begin
|
begin
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if rising_edge(clk_i) then
|
if (rstn_i = '0') then
|
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mar <= (others => def_rst_val_c);
|
|
elsif rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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mar <= addr_i;
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mar <= addr_i;
|
end if;
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end if;
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end if;
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end if;
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end process mem_adr_reg;
|
end process mem_adr_reg;
|
|
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-- read-back for exception controller --
|
-- read-back for exception controller --
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mar_o <= mar;
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mar_o <= mar;
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|
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-- alignment check --
|
-- alignment check --
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misaligned_d_check: process(mar, ctrl_i)
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misaligned_d_check: process(mar, ctrl_i)
|
begin
|
begin
|
-- check data access --
|
-- check data access --
|
d_misaligned <= '0'; -- default
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d_misaligned <= '0'; -- default
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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when "00" => -- byte
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when "00" => -- byte
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d_misaligned <= '0';
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d_misaligned <= '0';
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when "01" => -- half-word
|
when "01" => -- half-word
|
if (mar(0) /= '0') then
|
if (mar(0) /= '0') then
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d_misaligned <= '1';
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d_misaligned <= '1';
|
end if;
|
end if;
|
when others => -- word
|
when others => -- word
|
if (mar(1 downto 0) /= "00") then
|
if (mar(1 downto 0) /= "00") then
|
d_misaligned <= '1';
|
d_misaligned <= '1';
|
end if;
|
end if;
|
end case;
|
end case;
|
end process misaligned_d_check;
|
end process misaligned_d_check;
|
|
|
|
|
-- Data Interface: Write Data -------------------------------------------------------------
|
-- Data Interface: Write Data -------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_do_reg: process(clk_i)
|
mem_do_reg: process(rstn_i, clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if (rstn_i = '0') then
|
|
mdo <= (others => def_rst_val_c);
|
|
elsif rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
mdo <= wdata_i; -- memory data output register (MDO)
|
mdo <= wdata_i; -- memory data output register (MDO)
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_do_reg;
|
end process mem_do_reg;
|
|
|
-- byte enable and output data alignment --
|
-- byte enable and output data alignment --
|
byte_enable: process(mar, mdo, ctrl_i)
|
byte_enable: process(mar, mdo, ctrl_i)
|
begin
|
begin
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
when "00" => -- byte
|
when "00" => -- byte
|
d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
|
d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
|
d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
|
d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
|
d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
|
d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
|
d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
|
d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
|
case mar(1 downto 0) is
|
case mar(1 downto 0) is
|
when "00" => d_bus_ben <= "0001";
|
when "00" => d_bus_ben <= "0001";
|
when "01" => d_bus_ben <= "0010";
|
when "01" => d_bus_ben <= "0010";
|
when "10" => d_bus_ben <= "0100";
|
when "10" => d_bus_ben <= "0100";
|
when others => d_bus_ben <= "1000";
|
when others => d_bus_ben <= "1000";
|
end case;
|
end case;
|
when "01" => -- half-word
|
when "01" => -- half-word
|
d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
|
d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
|
d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
|
d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
|
if (mar(1) = '0') then
|
if (mar(1) = '0') then
|
d_bus_ben <= "0011"; -- low half-word
|
d_bus_ben <= "0011"; -- low half-word
|
else
|
else
|
d_bus_ben <= "1100"; -- high half-word
|
d_bus_ben <= "1100"; -- high half-word
|
end if;
|
end if;
|
when others => -- word
|
when others => -- word
|
d_bus_wdata <= mdo;
|
d_bus_wdata <= mdo;
|
d_bus_ben <= "1111"; -- full word
|
d_bus_ben <= "1111"; -- full word
|
end case;
|
end case;
|
end process byte_enable;
|
end process byte_enable;
|
|
|
|
|
-- Data Interface: Read Data --------------------------------------------------------------
|
-- Data Interface: Read Data --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_out_buf: process(clk_i)
|
mem_out_buf: process(rstn_i, clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if (rstn_i = '0') then
|
|
mdi <= (others => def_rst_val_c);
|
|
elsif rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
|
mdi <= d_bus_rdata; -- memory data input register (MDI)
|
mdi <= d_bus_rdata; -- memory data input register (MDI)
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_out_buf;
|
end process mem_out_buf;
|
|
|
-- input data alignment and sign extension --
|
-- input data alignment and sign extension --
|
read_align: process(mdi, mar, ctrl_i)
|
read_align: process(mdi, mar, ctrl_i)
|
variable byte_in_v : std_ulogic_vector(07 downto 0);
|
variable byte_in_v : std_ulogic_vector(07 downto 0);
|
variable hword_in_v : std_ulogic_vector(15 downto 0);
|
variable hword_in_v : std_ulogic_vector(15 downto 0);
|
begin
|
begin
|
-- sub-word input --
|
-- sub-word input --
|
case mar(1 downto 0) is
|
case mar(1 downto 0) is
|
when "00" => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0
|
when "00" => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0
|
when "01" => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0
|
when "01" => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0
|
when "10" => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1
|
when "10" => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1
|
when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
|
when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
|
end case;
|
end case;
|
-- actual data size --
|
-- actual data size --
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
|
when "00" => -- byte
|
when "00" => -- byte
|
rdata_o(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
|
rdata_o(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
|
rdata_o(07 downto 00) <= byte_in_v;
|
rdata_o(07 downto 00) <= byte_in_v;
|
when "01" => -- half-word
|
when "01" => -- half-word
|
rdata_o(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
|
rdata_o(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
|
rdata_o(15 downto 00) <= hword_in_v; -- high half-word
|
rdata_o(15 downto 00) <= hword_in_v; -- high half-word
|
when others => -- word
|
when others => -- word
|
rdata_o <= mdi; -- full word
|
rdata_o <= mdi; -- full word
|
end case;
|
end case;
|
end process read_align;
|
end process read_align;
|
|
|
|
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
data_access_arbiter: process(rstn_i, clk_i)
|
data_access_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.timeout <= (others => '0');
|
d_arbiter.timeout <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- data access request --
|
-- data access request --
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.err_align <= d_misaligned;
|
d_arbiter.err_align <= d_misaligned;
|
d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
else -- in progress
|
else -- in progress
|
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
|
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i or
|
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i or
|
(st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
(st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process data_access_arbiter;
|
end process data_access_arbiter;
|
|
|
-- cancel bus access --
|
-- cancel bus access --
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
|
|
-- wait for bus transaction to finish --
|
-- wait for bus transaction to finish --
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
|
|
-- output data access error to controller --
|
-- output data access error to controller --
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
|
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
|
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
|
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
|
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
|
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
|
|
|
-- data bus (read/write)--
|
-- data bus (read/write)--
|
d_bus_addr_o <= mar;
|
d_bus_addr_o <= mar;
|
d_bus_wdata_o <= d_bus_wdata;
|
d_bus_wdata_o <= d_bus_wdata;
|
d_bus_ben_o <= d_bus_ben;
|
d_bus_ben_o <= d_bus_ben;
|
d_bus_we <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
|
d_bus_we <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
|
d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
|
d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
|
d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
|
d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
|
d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
|
d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_rdata <= d_bus_rdata_i;
|
d_bus_rdata <= d_bus_rdata_i;
|
d_bus_excl_o <= ctrl_i(ctrl_bus_excl_c);
|
d_bus_excl_o <= ctrl_i(ctrl_bus_excl_c);
|
|
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
|
pmp_dbus_buffer: process(rstn_i, clk_i)
|
pmp_dbus_buffer: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
d_bus_we_buf <= '0';
|
d_bus_we_buf <= '0';
|
d_bus_re_buf <= '0';
|
d_bus_re_buf <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
d_bus_we_buf <= d_bus_we;
|
d_bus_we_buf <= d_bus_we;
|
d_bus_re_buf <= d_bus_re;
|
d_bus_re_buf <= d_bus_re;
|
end if;
|
end if;
|
end process pmp_dbus_buffer;
|
end process pmp_dbus_buffer;
|
|
|
-- Atomic memory access - status buffer --
|
-- Atomic memory access - status buffer --
|
atomic_access_status: process(rstn_i, clk_i)
|
atomic_access_status: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
bus_excl_ok_o <= '0';
|
bus_excl_ok_o <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (d_bus_ack_i = '1') then
|
if (d_bus_ack_i = '1') then
|
bus_excl_ok_o <= d_bus_excl_i; -- set if access was exclusive
|
bus_excl_ok_o <= d_bus_excl_i; -- set if access was exclusive
|
elsif (d_arbiter.rd_req = '0') and (d_arbiter.wr_req = '0') then -- bus access done
|
elsif (d_arbiter.rd_req = '0') and (d_arbiter.wr_req = '0') then -- bus access done
|
bus_excl_ok_o <= '0';
|
bus_excl_ok_o <= '0';
|
end if;
|
end if;
|
else
|
else
|
bus_excl_ok_o <= '0';
|
bus_excl_ok_o <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process atomic_access_status;
|
end process atomic_access_status;
|
|
|
|
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ifetch_arbiter: process(rstn_i, clk_i)
|
ifetch_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
i_arbiter.rd_req <= '0';
|
i_arbiter.rd_req <= '0';
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.timeout <= (others => '0');
|
i_arbiter.timeout <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- instruction fetch request --
|
-- instruction fetch request --
|
if (i_arbiter.rd_req = '0') then -- idle
|
if (i_arbiter.rd_req = '0') then -- idle
|
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
|
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
|
i_arbiter.err_align <= i_misaligned;
|
i_arbiter.err_align <= i_misaligned;
|
i_arbiter.err_bus <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
else -- in progress
|
else -- in progress
|
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
|
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
|
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
|
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
|
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
|
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
|
if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
i_arbiter.rd_req <= '0';
|
i_arbiter.rd_req <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process ifetch_arbiter;
|
end process ifetch_arbiter;
|
|
|
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
|
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
|
|
|
-- cancel bus access --
|
-- cancel bus access --
|
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
|
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
|
|
|
-- wait for bus transaction to finish --
|
-- wait for bus transaction to finish --
|
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
|
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
|
|
|
-- output instruction fetch error to controller --
|
-- output instruction fetch error to controller --
|
ma_instr_o <= i_arbiter.err_align;
|
ma_instr_o <= i_arbiter.err_align;
|
be_instr_o <= i_arbiter.err_bus;
|
be_instr_o <= i_arbiter.err_bus;
|
|
|
-- instruction bus (read-only) --
|
-- instruction bus (read-only) --
|
i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
|
i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
|
i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only
|
i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only
|
i_bus_ben_o <= (others => '0');
|
i_bus_ben_o <= (others => '0');
|
i_bus_we_o <= '0';
|
i_bus_we_o <= '0';
|
i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
|
i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
|
i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
|
i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
|
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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instr_o <= i_bus_rdata_i;
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instr_o <= i_bus_rdata_i;
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-- check instruction access --
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-- check instruction access --
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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pmp_ibus_buffer: process(rstn_i, clk_i)
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pmp_ibus_buffer: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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i_bus_re_buf <= '0';
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i_bus_re_buf <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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i_bus_re_buf <= i_bus_re;
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i_bus_re_buf <= i_bus_re;
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end if;
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end if;
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end process pmp_ibus_buffer;
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end process pmp_ibus_buffer;
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- compute address masks (ITERATIVE!!!) --
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-- compute address masks (ITERATIVE!!!) --
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pmp_masks: process(clk_i)
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pmp_masks: process(rstn_i, clk_i)
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begin
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begin
|
if rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
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if (rstn_i = '0') then
|
|
pmp.addr_mask <= (others => (others => def_rst_val_c));
|
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elsif rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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pmp.addr_mask(r) <= (others => '0');
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pmp.addr_mask(r) <= (others => '0');
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for i in pmp_g_c to data_width_c-1 loop
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for i in pmp_g_c to data_width_c-1 loop
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pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
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pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
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end loop; -- i
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end loop; -- i
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end loop; -- r
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end loop; -- r
|
end if;
|
end if;
|
end process pmp_masks;
|
end process pmp_masks;
|
|
|
|
|
-- address access check --
|
-- address access check --
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pmp_address_check:
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pmp_address_check:
|
for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
|
for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
|
pmp.region_i_addr(r) <= fetch_pc_i and pmp.addr_mask(r);
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pmp.region_i_addr(r) <= fetch_pc_i and pmp.addr_mask(r);
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pmp.region_d_addr(r) <= mar and pmp.addr_mask(r);
|
pmp.region_d_addr(r) <= mar and pmp.addr_mask(r);
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pmp.region_base(r) <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
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pmp.region_base(r) <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
|
--
|
--
|
pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
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pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
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pmp.d_match(r) <= '1' when (pmp.region_d_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
|
pmp.d_match(r) <= '1' when (pmp.region_d_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
|
end generate; -- r
|
end generate; -- r
|
|
|
|
|
-- check access type and regions's permissions --
|
-- check access type and regions's permissions --
|
pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
|
pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
|
begin
|
begin
|
for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
|
for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
|
if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
|
if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
|
(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
|
(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
|
pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
|
pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
|
pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
|
pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
|
pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
|
pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
|
else
|
else
|
pmp.if_fault(r) <= '0';
|
pmp.if_fault(r) <= '0';
|
pmp.ld_fault(r) <= '0';
|
pmp.ld_fault(r) <= '0';
|
pmp.st_fault(r) <= '0';
|
pmp.st_fault(r) <= '0';
|
end if;
|
end if;
|
end loop; -- r
|
end loop; -- r
|
end process pmp_check_permission;
|
end process pmp_check_permission;
|
|
|
|
|
-- final PMP access fault signals --
|
-- final PMP access fault signals --
|
if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
|
|
|
|
|
end neorv32_cpu_bus_rtl;
|
end neorv32_cpu_bus_rtl;
|
|
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