-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # This unit connects the CPU to the memory/IO system. #
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-- # This unit connects the CPU to the memory/IO system. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
|
-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
-- # endorse or promote products derived from this software without specific prior written #
|
-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
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|
|
library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
|
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
);
|
);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
|
-- data input --
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- data output --
|
-- data output --
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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-- status --
|
-- status --
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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|
bus_busy_o : out std_ulogic; -- bus unit is busy
|
exc_ack_i : in std_ulogic; -- exception controller ACK
|
exc_ack_i : in std_ulogic; -- exception controller ACK
|
-- bus system --
|
-- bus system --
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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bus_re_o : out std_ulogic; -- read enable
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic -- bus transfer error
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bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
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end neorv32_cpu_bus;
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end neorv32_cpu_bus;
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|
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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|
|
-- interface registers --
|
-- interface registers --
|
signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
|
|
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-- bus request controller --
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-- bus request controller --
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signal bus_busy : std_ulogic;
|
signal bus_busy : std_ulogic;
|
signal bus_if_req : std_ulogic;
|
signal bus_if_req : std_ulogic;
|
signal bus_rd_req : std_ulogic;
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signal bus_rd_req : std_ulogic;
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signal bus_wr_req : std_ulogic;
|
signal bus_wr_req : std_ulogic;
|
signal access_err : std_ulogic;
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signal access_err : std_ulogic;
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signal align_err : std_ulogic;
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signal align_err : std_ulogic;
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signal bus_timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
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signal bus_timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
|
|
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-- misaligned access? --
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-- misaligned access? --
|
signal misaligned_data, misaligned_instr : std_ulogic;
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signal misaligned_data, misaligned_instr : std_ulogic;
|
|
|
begin
|
begin
|
|
|
-- Address and Control --------------------------------------------------------------------
|
-- Address and Control --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_adr_reg: process(rstn_i, clk_i)
|
mem_adr_reg: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
mar <= (others => '0');
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mar <= (others => '0');
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elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
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mar <= alu_i;
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mar <= alu_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_adr_reg;
|
end process mem_adr_reg;
|
|
|
-- address output --
|
-- address output --
|
bus_addr_o <= pc_i when (ctrl_i(ctrl_bus_if_c) = '1') else mar; -- is instruction fetch?
|
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch?
|
mar_o <= mar;
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mar_o <= mar;
|
|
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-- write request output --
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-- write request output --
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bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data);
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bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data);
|
|
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-- read request output (also used for instruction fetch) --
|
-- read request output (also used for instruction fetch) --
|
bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or (ctrl_i(ctrl_bus_if_c) and (not misaligned_instr));
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bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or ((bus_if_req or ctrl_i(ctrl_bus_if_c)) and (not misaligned_instr));
|
|
|
|
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-- Write Data -----------------------------------------------------------------------------
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-- Write Data -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_do_reg: process(clk_i)
|
mem_do_reg: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
|
mdo <= wdata_i;
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mdo <= wdata_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_do_reg;
|
end process mem_do_reg;
|
|
|
-- byte enable and output data alignment --
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-- byte enable and output data alignment --
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byte_enable: process(mar, mdo, ctrl_i)
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byte_enable: process(mar, mdo, ctrl_i)
|
begin
|
begin
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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when "00" => -- byte
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when "00" => -- byte
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bus_wdata_o(07 downto 00) <= mdo(07 downto 00);
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bus_wdata_o(07 downto 00) <= mdo(07 downto 00);
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bus_wdata_o(15 downto 08) <= mdo(07 downto 00);
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bus_wdata_o(15 downto 08) <= mdo(07 downto 00);
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bus_wdata_o(23 downto 16) <= mdo(07 downto 00);
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bus_wdata_o(23 downto 16) <= mdo(07 downto 00);
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bus_wdata_o(31 downto 24) <= mdo(07 downto 00);
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bus_wdata_o(31 downto 24) <= mdo(07 downto 00);
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bus_ben_o <= (others => '0');
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bus_ben_o <= (others => '0');
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bus_ben_o(to_integer(unsigned(mar(1 downto 0)))) <= '1';
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bus_ben_o(to_integer(unsigned(mar(1 downto 0)))) <= '1';
|
when "01" => -- half-word
|
when "01" => -- half-word
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bus_wdata_o(31 downto 16) <= mdo(15 downto 00);
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bus_wdata_o(31 downto 16) <= mdo(15 downto 00);
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bus_wdata_o(15 downto 00) <= mdo(15 downto 00);
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bus_wdata_o(15 downto 00) <= mdo(15 downto 00);
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if (mar(1) = '0') then
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if (mar(1) = '0') then
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bus_ben_o <= "0011"; -- low half-word
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bus_ben_o <= "0011"; -- low half-word
|
else
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else
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bus_ben_o <= "1100"; -- high half-word
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bus_ben_o <= "1100"; -- high half-word
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end if;
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end if;
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when others => -- word
|
when others => -- word
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bus_wdata_o <= mdo;
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bus_wdata_o <= mdo;
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bus_ben_o <= "1111"; -- full word
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bus_ben_o <= "1111"; -- full word
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end case;
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end case;
|
end process byte_enable;
|
end process byte_enable;
|
|
|
|
|
-- Read Data ------------------------------------------------------------------------------
|
-- Read Data ------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_out_buf: process(clk_i)
|
mem_out_buf: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- memory data in register (MDI) --
|
-- memory data in register (MDI) --
|
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
|
mdi <= bus_rdata_i;
|
mdi <= bus_rdata_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_out_buf;
|
end process mem_out_buf;
|
|
|
-- instruction output --
|
-- instruction output --
|
instr_o <= bus_rdata_i;
|
instr_o <= bus_rdata_i;
|
|
|
-- input data align and sign extension --
|
-- input data align and sign extension --
|
read_align: process(mdi, mar, ctrl_i)
|
read_align: process(mdi, mar, ctrl_i)
|
variable signed_v : std_ulogic;
|
variable signed_v : std_ulogic;
|
begin
|
begin
|
signed_v := not ctrl_i(ctrl_bus_unsigned_c);
|
signed_v := not ctrl_i(ctrl_bus_unsigned_c);
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
when "00" => -- byte
|
when "00" => -- byte
|
case mar(1 downto 0) is
|
case mar(1 downto 0) is
|
when "00" =>
|
when "00" =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(07)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(07)));
|
rdata_o(07 downto 00) <= mdi(07 downto 00); -- byte 0
|
rdata_o(07 downto 00) <= mdi(07 downto 00); -- byte 0
|
when "01" =>
|
when "01" =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(15)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(15)));
|
rdata_o(07 downto 00) <= mdi(15 downto 08); -- byte 1
|
rdata_o(07 downto 00) <= mdi(15 downto 08); -- byte 1
|
when "10" =>
|
when "10" =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(23)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(23)));
|
rdata_o(07 downto 00) <= mdi(23 downto 16); -- byte 2
|
rdata_o(07 downto 00) <= mdi(23 downto 16); -- byte 2
|
when others =>
|
when others =>
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(31)));
|
rdata_o(31 downto 08) <= (others => (signed_v and mdi(31)));
|
rdata_o(07 downto 00) <= mdi(31 downto 24); -- byte 3
|
rdata_o(07 downto 00) <= mdi(31 downto 24); -- byte 3
|
end case;
|
end case;
|
when "01" => -- half-word
|
when "01" => -- half-word
|
if (mar(1) = '0') then
|
if (mar(1) = '0') then
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(15)));
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(15)));
|
rdata_o(15 downto 00) <= mdi(15 downto 00); -- low half-word
|
rdata_o(15 downto 00) <= mdi(15 downto 00); -- low half-word
|
else
|
else
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(31)));
|
rdata_o(31 downto 16) <= (others => (signed_v and mdi(31)));
|
rdata_o(15 downto 00) <= mdi(31 downto 16); -- high half-word
|
rdata_o(15 downto 00) <= mdi(31 downto 16); -- high half-word
|
end if;
|
end if;
|
when others => -- word
|
when others => -- word
|
rdata_o <= mdi; -- full word
|
rdata_o <= mdi; -- full word
|
end case;
|
end case;
|
end process read_align;
|
end process read_align;
|
|
|
|
|
-- Bus Status Controller ------------------------------------------------------------------
|
-- Bus Status Controller ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
bus_ctrl: process(rstn_i, clk_i)
|
bus_ctrl: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
bus_busy <= '0';
|
bus_busy <= '0';
|
bus_if_req <= '0';
|
bus_if_req <= '0';
|
bus_rd_req <= '0';
|
bus_rd_req <= '0';
|
bus_wr_req <= '0';
|
bus_wr_req <= '0';
|
access_err <= '0';
|
access_err <= '0';
|
align_err <= '0';
|
align_err <= '0';
|
bus_timeout <= (others => '0');
|
bus_timeout <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (bus_busy = '0') then -- wait for new request
|
if (bus_busy = '0') then -- wait for new request
|
bus_busy <= ctrl_i(ctrl_bus_if_c) or ctrl_i(ctrl_bus_rd_c) or ctrl_i(ctrl_bus_wr_c); -- any request at all?
|
bus_busy <= ctrl_i(ctrl_bus_if_c) or ctrl_i(ctrl_bus_rd_c) or ctrl_i(ctrl_bus_wr_c); -- any request at all?
|
bus_if_req <= ctrl_i(ctrl_bus_if_c); -- instruction fetch
|
bus_if_req <= ctrl_i(ctrl_bus_if_c); -- instruction fetch
|
bus_rd_req <= ctrl_i(ctrl_bus_rd_c); -- store access
|
bus_rd_req <= ctrl_i(ctrl_bus_rd_c); -- store access
|
bus_wr_req <= ctrl_i(ctrl_bus_wr_c); -- load access
|
bus_wr_req <= ctrl_i(ctrl_bus_wr_c); -- load access
|
bus_timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
|
bus_timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
|
access_err <= '0';
|
access_err <= '0';
|
align_err <= '0';
|
align_err <= '0';
|
else -- bus transfer in progress
|
else -- bus transfer in progress
|
bus_timeout <= std_ulogic_vector(unsigned(bus_timeout) - 1);
|
bus_timeout <= std_ulogic_vector(unsigned(bus_timeout) - 1);
|
align_err <= (align_err or misaligned_data or misaligned_instr) and (not exc_ack_i);
|
align_err <= (align_err or misaligned_data or misaligned_instr) and (not exc_ack_i);
|
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not exc_ack_i);
|
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not exc_ack_i);
|
if (align_err = '1') or (access_err = '1') then
|
if (align_err = '1') or (access_err = '1') then
|
if (exc_ack_i = '1') then -- wait for controller to ack exception
|
if (exc_ack_i = '1') then -- wait for controller to ack exception
|
bus_if_req <= '0';
|
bus_if_req <= '0';
|
bus_rd_req <= '0';
|
bus_rd_req <= '0';
|
bus_wr_req <= '0';
|
bus_wr_req <= '0';
|
bus_busy <= '0';
|
bus_busy <= '0';
|
end if;
|
end if;
|
elsif (bus_ack_i = '1') then -- normal termination
|
elsif (bus_ack_i = '1') then -- normal termination
|
bus_if_req <= '0';
|
bus_if_req <= '0';
|
bus_rd_req <= '0';
|
bus_rd_req <= '0';
|
bus_wr_req <= '0';
|
bus_wr_req <= '0';
|
bus_busy <= '0';
|
bus_busy <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process bus_ctrl;
|
end process bus_ctrl;
|
|
|
-- output bus access error to controller --
|
-- output bus access error to controller --
|
be_instr_o <= bus_if_req and access_err;
|
be_instr_o <= bus_if_req and access_err;
|
be_load_o <= bus_rd_req and access_err;
|
be_load_o <= bus_rd_req and access_err;
|
be_store_o <= bus_wr_req and access_err;
|
be_store_o <= bus_wr_req and access_err;
|
|
|
-- output alignment error to controller --
|
-- output alignment error to controller --
|
ma_instr_o <= bus_if_req and align_err;
|
ma_instr_o <= bus_if_req and align_err;
|
ma_load_o <= bus_rd_req and align_err;
|
ma_load_o <= bus_rd_req and align_err;
|
ma_store_o <= bus_wr_req and align_err;
|
ma_store_o <= bus_wr_req and align_err;
|
|
|
-- wait for bus --
|
-- wait for bus --
|
|
bus_busy_o <= bus_busy;
|
bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack
|
bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack
|
|
|
|
|
-- Check for Misaligned Access ------------------------------------------------------------
|
-- Check for Misaligned Access ------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
misaligned_d_check: process(mar, ctrl_i)
|
misaligned_d_check: process(mar, ctrl_i)
|
begin
|
begin
|
-- check data access --
|
-- check data access --
|
misaligned_data <= '0'; -- default
|
misaligned_data <= '0'; -- default
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
when "00" => -- byte
|
when "00" => -- byte
|
misaligned_data <= '0';
|
misaligned_data <= '0';
|
when "01" => -- half-word
|
when "01" => -- half-word
|
if (mar(0) /= '0') then
|
if (mar(0) /= '0') then
|
misaligned_data <= '1';
|
misaligned_data <= '1';
|
end if;
|
end if;
|
when others => -- word
|
when others => -- word
|
if (mar(1 downto 0) /= "00") then
|
if (mar(1 downto 0) /= "00") then
|
misaligned_data <= '1';
|
misaligned_data <= '1';
|
end if;
|
end if;
|
end case;
|
end case;
|
end process misaligned_d_check;
|
end process misaligned_d_check;
|
|
|
misaligned_i_check: process(ctrl_i, pc_i)
|
misaligned_i_check: process(ctrl_i, pc_i)
|
begin
|
begin
|
-- check instruction access --
|
-- check instruction access --
|
misaligned_instr <= '0'; -- default
|
misaligned_instr <= '0'; -- default
|
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit instruction access only
|
if (ctrl_i(ctrl_sys_c_ext_en_c) = '1') then -- 16-bit and 32-bit instruction accesses
|
if (pc_i(0) /= '0') then
|
misaligned_instr <= '0';
|
misaligned_instr <= '1';
|
else -- 32-bit instruction accesses only
|
end if;
|
|
else -- 32-bit instruction access only
|
|
if (pc_i(1 downto 0) /= "00") then
|
if (pc_i(1 downto 0) /= "00") then
|
misaligned_instr <= '1';
|
misaligned_instr <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process misaligned_i_check;
|
end process misaligned_i_check;
|
|
|
|
|
end neorv32_cpu_bus_rtl;
|
end neorv32_cpu_bus_rtl;
|
|
|