-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Control >> #
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-- # << NEORV32 - CPU Control >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # CPU operation is split into a fetch engine (responsible for fetching an decompressing instr- #
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-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an #
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-- # uctions), an execute engine (responsible for actually executing the instructions), an inter- #
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-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction #
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-- # rupt and exception handling controller and the RISC-V status and control registers (CSRs). #
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-- # words) and an execute engine (responsible for actually executing the instructions), a trap #
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-- # handling controller and the RISC-V status and control register set (CSRs). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_control is
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entity neorv32_cpu_control is
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_USE : boolean := false; -- implement physical memory protection?
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PMP_USE : boolean := false; -- implement physical memory protection?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
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PMP_GRANULARITY : natural := 0 -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
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PMP_GRANULARITY : natural := 0 -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- status input --
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-- status input --
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alu_wait_i : in std_ulogic; -- wait for ALU
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alu_wait_i : in std_ulogic; -- wait for ALU
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bus_i_wait_i : in std_ulogic; -- wait for bus
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bus_i_wait_i : in std_ulogic; -- wait for bus
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bus_d_wait_i : in std_ulogic; -- wait for bus
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bus_d_wait_i : in std_ulogic; -- wait for bus
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-- data input --
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-- data input --
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU processing result
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alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU processing result
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-- data output --
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-- data output --
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- machine software interrupt
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msw_irq_i : in std_ulogic; -- machine software interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(3 downto 0);
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firq_i : in std_ulogic_vector(3 downto 0);
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- physical memory protection --
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-- physical memory protection --
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pmp_addr_o : out pmp_addr_if_t; -- addresses
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pmp_addr_o : out pmp_addr_if_t; -- addresses
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
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priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_store_i : in std_ulogic -- bus error on store data access
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be_store_i : in std_ulogic -- bus error on store data access
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);
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);
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end neorv32_cpu_control;
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end neorv32_cpu_control;
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|
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architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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|
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-- instruction fetch enginge --
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-- instruction fetch enginge --
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type fetch_engine_state_t is (IFETCH_RESET, IFETCH_0, IFETCH_1, IFETCH_2);
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type fetch_engine_state_t is (IFETCH_RESET, IFETCH_REQUEST, IFETCH_ISSUE);
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type fetch_engine_t is record
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type fetch_engine_t is record
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state : fetch_engine_state_t;
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state : fetch_engine_state_t;
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state_nxt : fetch_engine_state_t;
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state_nxt : fetch_engine_state_t;
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i_buf : std_ulogic_vector(33 downto 0);
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i_buf_nxt : std_ulogic_vector(33 downto 0);
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i_buf2 : std_ulogic_vector(33 downto 0);
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i_buf2_nxt : std_ulogic_vector(33 downto 0);
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ci_input : std_ulogic_vector(15 downto 0); -- input to compressed instr. decoder
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i_buf_state : std_ulogic_vector(01 downto 0);
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i_buf_state_nxt : std_ulogic_vector(01 downto 0);
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pc : std_ulogic_vector(data_width_c-1 downto 0);
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pc : std_ulogic_vector(data_width_c-1 downto 0);
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pc_add : std_ulogic_vector(data_width_c-1 downto 0);
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pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
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reset : std_ulogic;
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reset : std_ulogic;
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bus_err_ack : std_ulogic;
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bus_err_ack : std_ulogic;
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end record;
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end record;
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signal fetch_engine : fetch_engine_t;
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signal fetch_engine : fetch_engine_t;
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-- pre-decoder --
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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signal ci_illegal : std_ulogic;
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-- instrucion prefetch buffer (IPB) --
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-- instrucion prefetch buffer (IPB) --
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type ipb_dbuf_t is array (0 to ipb_entries_c-1) of std_ulogic_vector(35 downto 0);
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type ipb_data_fifo_t is array (0 to ipb_entries_c-1) of std_ulogic_vector(2+31 downto 0);
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type ipb_t is record
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type ipb_t is record
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wdata : std_ulogic_vector(35 downto 0); -- data (+ status) to be written
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wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data
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we : std_ulogic; -- trigger write
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we : std_ulogic; -- trigger write
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free : std_ulogic; -- free entry available?
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free : std_ulogic; -- free entry available?
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clear : std_ulogic; -- clear all entries
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--
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--
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rdata : std_ulogic_vector(35 downto 0); -- read data (+ status)
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rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data
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re : std_ulogic; -- trigger read
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re : std_ulogic; -- read enable
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avail : std_ulogic; -- data available?
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avail : std_ulogic; -- data available?
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--
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--
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clear : std_ulogic; -- clear all entries
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--
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data : ipb_dbuf_t; -- the data fifo
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w_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- write pointer
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w_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- write pointer
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r_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- read pointer
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r_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- read pointer
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empty : std_ulogic;
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empty : std_ulogic;
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full : std_ulogic;
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full : std_ulogic;
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--
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data : ipb_data_fifo_t; -- fifo memory
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end record;
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end record;
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signal ipb : ipb_t;
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signal ipb : ipb_t;
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-- pre-decoder --
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signal ci_instr16 : std_ulogic_vector(15 downto 0);
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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signal ci_illegal : std_ulogic;
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-- instruction issue enginge --
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type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);
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type issue_engine_t is record
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state : issue_engine_state_t;
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state_nxt : issue_engine_state_t;
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align : std_ulogic;
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align_nxt : std_ulogic;
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buf : std_ulogic_vector(2+15 downto 0);
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buf_nxt : std_ulogic_vector(2+15 downto 0);
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end record;
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signal issue_engine : issue_engine_t;
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-- instruction buffer --
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type i_buf_t is record
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wdata : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction
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rdata : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction
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status : std_ulogic;
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clear : std_ulogic;
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we : std_ulogic;
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re : std_ulogic;
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free : std_ulogic;
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avail : std_ulogic;
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end record;
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signal i_buf : i_buf_t;
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|
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-- instruction execution engine --
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-- instruction execution engine --
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);
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type execute_engine_t is record
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type execute_engine_t is record
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state : execute_engine_state_t;
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state : execute_engine_state_t;
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state_prev : execute_engine_state_t;
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state_prev : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci_nxt : std_ulogic;
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is_ci_nxt : std_ulogic;
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is_jump : std_ulogic; -- current instruction is jump instruction
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is_jump : std_ulogic; -- current instruction is jump instruction
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is_jump_nxt : std_ulogic;
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is_jump_nxt : std_ulogic;
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is_cp_op : std_ulogic; -- current instruction is a co-processor operation
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is_cp_op : std_ulogic; -- current instruction is a co-processor operation
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is_cp_op_nxt : std_ulogic;
|
is_cp_op_nxt : std_ulogic;
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branch_taken : std_ulogic; -- branch condition fullfilled
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branch_taken : std_ulogic; -- branch condition fullfilled
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pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
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pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
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pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
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pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
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next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
|
next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
|
last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
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last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
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last_pc_nxt : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
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last_pc_nxt : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
|
sleep : std_ulogic; -- CPU in sleep mode
|
sleep : std_ulogic; -- CPU in sleep mode
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sleep_nxt : std_ulogic; -- CPU in sleep mode
|
sleep_nxt : std_ulogic; -- CPU in sleep mode
|
if_rst : std_ulogic; -- instruction fetch was reset
|
if_rst : std_ulogic; -- instruction fetch was reset
|
if_rst_nxt : std_ulogic; -- instruction fetch was reset
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if_rst_nxt : std_ulogic; -- instruction fetch was reset
|
end record;
|
end record;
|
signal execute_engine : execute_engine_t;
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signal execute_engine : execute_engine_t;
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|
|
signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0);
|
signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0);
|
|
|
-- trap controller --
|
-- trap controller --
|
type trap_ctrl_t is record
|
type trap_ctrl_t is record
|
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
|
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
|
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
|
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
|
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
cause : std_ulogic_vector(5 downto 0); -- trap ID (for "mcause"), only for hw
|
cause : std_ulogic_vector(5 downto 0); -- trap ID (for "mcause"), only for hw
|
cause_nxt : std_ulogic_vector(5 downto 0);
|
cause_nxt : std_ulogic_vector(5 downto 0);
|
--
|
--
|
env_start : std_ulogic; -- start trap handler env
|
env_start : std_ulogic; -- start trap handler env
|
env_start_ack : std_ulogic; -- start of trap handler acknowledged
|
env_start_ack : std_ulogic; -- start of trap handler acknowledged
|
env_end : std_ulogic; -- end trap handler env
|
env_end : std_ulogic; -- end trap handler env
|
--
|
--
|
instr_be : std_ulogic; -- instruction fetch bus error
|
instr_be : std_ulogic; -- instruction fetch bus error
|
instr_ma : std_ulogic; -- instruction fetch misaligned address
|
instr_ma : std_ulogic; -- instruction fetch misaligned address
|
instr_il : std_ulogic; -- illegal instruction
|
instr_il : std_ulogic; -- illegal instruction
|
env_call : std_ulogic;
|
env_call : std_ulogic;
|
break_point : std_ulogic;
|
break_point : std_ulogic;
|
end record;
|
end record;
|
signal trap_ctrl : trap_ctrl_t;
|
signal trap_ctrl : trap_ctrl_t;
|
|
|
-- CPU control signals --
|
-- CPU control signals --
|
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
|
|
-- fast bus access --
|
-- fast bus access --
|
signal bus_fast_ir : std_ulogic;
|
signal bus_fast_ir : std_ulogic;
|
|
|
-- RISC-V control and status registers (CSRs) --
|
-- RISC-V control and status registers (CSRs) --
|
type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
|
type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
|
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
type csr_t is record
|
type csr_t is record
|
we : std_ulogic; -- csr write enable
|
we : std_ulogic; -- csr write enable
|
we_nxt : std_ulogic;
|
we_nxt : std_ulogic;
|
re : std_ulogic; -- csr read enable
|
re : std_ulogic; -- csr read enable
|
re_nxt : std_ulogic;
|
re_nxt : std_ulogic;
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
--
|
--
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
|
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
--
|
--
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W
|
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
--
|
--
|
privilege : std_ulogic_vector(1 downto 0); -- hart's current previous privilege mode
|
privilege : std_ulogic_vector(1 downto 0); -- hart's current previous privilege mode
|
--
|
--
|
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-)
|
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-)
|
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
|
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
|
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
|
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
|
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
|
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
|
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH!
|
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH!
|
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH!
|
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH!
|
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
|
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
|
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
|
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
|
end record;
|
end record;
|
signal csr : csr_t;
|
signal csr : csr_t;
|
|
|
signal mcycle_msb : std_ulogic;
|
signal mcycle_msb : std_ulogic;
|
signal minstret_msb : std_ulogic;
|
signal minstret_msb : std_ulogic;
|
|
|
-- illegal instruction check --
|
-- illegal instruction check --
|
signal illegal_instruction : std_ulogic;
|
signal illegal_instruction : std_ulogic;
|
signal illegal_register : std_ulogic; -- only for E-extension
|
signal illegal_register : std_ulogic; -- only for E-extension
|
signal illegal_compressed : std_ulogic; -- only fir C-extension
|
signal illegal_compressed : std_ulogic; -- only fir C-extension
|
|
|
-- access (privilege) check --
|
-- access (privilege) check --
|
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
|
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
|
|
|
begin
|
begin
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Fetch
|
-- Instruction Fetch (always fetches aligned 32-bit chunks of data)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- registers that require a specific reset state --
|
fetch_engine_fsm_sync: process(rstn_i, clk_i)
|
fetch_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
fetch_engine.state <= IFETCH_RESET;
|
fetch_engine.state <= IFETCH_RESET;
|
|
fetch_engine.pc <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (fetch_engine.reset = '1') then
|
if (fetch_engine.reset = '1') then
|
fetch_engine.state <= IFETCH_RESET;
|
fetch_engine.state <= IFETCH_RESET;
|
else
|
else
|
fetch_engine.state <= fetch_engine.state_nxt;
|
fetch_engine.state <= fetch_engine.state_nxt;
|
end if;
|
end if;
|
end if;
|
fetch_engine.pc <= fetch_engine.pc_nxt;
|
end process fetch_engine_fsm_sync_rst;
|
|
|
|
|
|
-- registers that DO NOT require a specific reset state --
|
|
fetch_engine_fsm_sync: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
if (fetch_engine.state = IFETCH_RESET) then
|
|
fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
|
else
|
|
fetch_engine.pc <= std_ulogic_vector(unsigned(fetch_engine.pc(data_width_c-1 downto 1) & '0') + unsigned(fetch_engine.pc_add(data_width_c-1 downto 1) & '0'));
|
|
end if;
|
|
--
|
|
fetch_engine.i_buf <= fetch_engine.i_buf_nxt;
|
|
fetch_engine.i_buf2 <= fetch_engine.i_buf2_nxt;
|
|
fetch_engine.i_buf_state <= fetch_engine.i_buf_state_nxt;
|
|
end if;
|
end if;
|
end process fetch_engine_fsm_sync;
|
end process fetch_engine_fsm_sync;
|
|
|
-- PC output --
|
-- PC output --
|
fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0';
|
fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned
|
|
|
|
|
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
fetch_engine_fsm_comb: process(fetch_engine, csr, ipb, instr_i, bus_i_wait_i, ci_instr32, ci_illegal, be_instr_i, ma_instr_i)
|
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
bus_fast_ir <= '0';
|
bus_fast_ir <= '0';
|
fetch_engine.state_nxt <= fetch_engine.state;
|
fetch_engine.state_nxt <= fetch_engine.state;
|
fetch_engine.pc_add <= (others => '0');
|
fetch_engine.pc_nxt <= fetch_engine.pc;
|
fetch_engine.i_buf_nxt <= fetch_engine.i_buf;
|
|
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf2;
|
|
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state;
|
|
fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);
|
|
fetch_engine.bus_err_ack <= '0';
|
fetch_engine.bus_err_ack <= '0';
|
|
|
-- instruction prefetch buffer interface --
|
-- instruction prefetch buffer interface --
|
ipb.we <= '0';
|
ipb.we <= '0';
|
|
ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
|
ipb.clear <= '0';
|
ipb.clear <= '0';
|
ipb.wdata <= (others => '0');
|
|
|
|
-- state machine --
|
-- state machine --
|
case fetch_engine.state is
|
case fetch_engine.state is
|
|
|
when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC
|
when IFETCH_RESET => -- reset engine and prefetch buffer, get appilcation PC
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
fetch_engine.i_buf_state_nxt <= (others => '0');
|
|
ipb.clear <= '1'; -- clear instruction prefetch buffer
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
|
|
fetch_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
|
ipb.clear <= '1'; -- clear prefetch buffer
|
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
|
|
when IFETCH_0 => -- output current PC to bus system, request 32-bit word
|
when IFETCH_REQUEST => -- output current PC to bus system and request 32-bit (aligned!) instruction data
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
if (ipb.free = '1') then -- free entry in buffer?
|
bus_fast_ir <= '1'; -- fast instruction fetch request
|
bus_fast_ir <= '1'; -- fast instruction fetch request
|
fetch_engine.state_nxt <= IFETCH_1;
|
fetch_engine.state_nxt <= IFETCH_ISSUE;
|
|
|
when IFETCH_1 => -- store data from memory to buffer(s)
|
|
-- ------------------------------------------------------------
|
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
|
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
|
|
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
|
|
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';
|
|
if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?
|
|
fetch_engine.state_nxt <= IFETCH_2;
|
|
else
|
|
fetch_engine.pc_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
|
fetch_engine.state_nxt <= IFETCH_0; -- get another instruction word
|
|
end if;
|
|
end if;
|
end if;
|
|
|
when IFETCH_2 => -- construct instruction word and issue
|
when IFETCH_ISSUE => -- store instruction data to prefetch buffer
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
|
if (fetch_engine.pc(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
|
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
|
fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);
|
|
|
|
if (ipb.free = '1') then -- free entry in buffer?
|
|
ipb.we <= '1';
|
|
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
|
|
ipb.wdata <= '0' & fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
|
|
fetch_engine.pc_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
|
else -- compressed
|
|
ipb.wdata <= ci_illegal & fetch_engine.i_buf2(33 downto 32) & '1' & ci_instr32;
|
|
fetch_engine.pc_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
|
fetch_engine.state_nxt <= IFETCH_2; -- try to get another 16-bit instruction word in next round
|
|
end if;
|
|
end if;
|
|
|
|
else -- 16-bit aligned
|
|
fetch_engine.ci_input <= fetch_engine.i_buf2(31 downto 16);
|
|
|
|
if (ipb.free = '1') then -- free entry in buffer?
|
|
ipb.we <= '1';
|
ipb.we <= '1';
|
if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed and "unaligned"
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
ipb.wdata <= '0' & fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);
|
|
fetch_engine.pc_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
|
else -- compressed
|
|
ipb.wdata <= ci_illegal & fetch_engine.i_buf(33 downto 32) & '1' & ci_instr32;
|
|
fetch_engine.pc_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
|
end if;
|
|
end if;
|
|
end if;
|
end if;
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
fetch_engine.state_nxt <= IFETCH_RESET;
|
fetch_engine.state_nxt <= IFETCH_RESET;
|
|
|
end case;
|
end case;
|
end process fetch_engine_fsm_comb;
|
end process fetch_engine_fsm_comb;
|
|
|
|
|
-- Compressed Instructions Recoding -------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_decompressor_inst_true:
|
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
|
port map (
|
|
-- instruction input --
|
|
ci_instr16_i => fetch_engine.ci_input, -- compressed instruction input
|
|
-- instruction output --
|
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_decompressor_inst_false:
|
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
|
ci_instr32 <= (others => '0');
|
|
ci_illegal <= '0';
|
|
end generate;
|
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Prefetch Buffer
|
-- Instruction Prefetch Buffer
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
|
-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
instr_prefetch_buffer_ctrl: process(rstn_i, clk_i)
|
instr_prefetch_buffer_ctrl: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
ipb.w_pnt <= (others => '0');
|
ipb.w_pnt <= (others => '0');
|
ipb.r_pnt <= (others => '0');
|
ipb.r_pnt <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- write port --
|
-- write port --
|
if (ipb.clear = '1') then
|
if (ipb.clear = '1') then
|
ipb.w_pnt <= (others => '0');
|
ipb.w_pnt <= (others => '0');
|
elsif (ipb.we = '1') then
|
elsif (ipb.we = '1') then
|
ipb.w_pnt <= std_ulogic_vector(unsigned(ipb.w_pnt) + 1);
|
ipb.w_pnt <= std_ulogic_vector(unsigned(ipb.w_pnt) + 1);
|
end if;
|
end if;
|
-- read port --
|
-- read ports --
|
if (ipb.clear = '1') then
|
if (ipb.clear = '1') then
|
ipb.r_pnt <= (others => '0');
|
ipb.r_pnt <= (others => '0');
|
elsif (ipb.re = '1') then
|
elsif (ipb.re = '1') then
|
ipb.r_pnt <= std_ulogic_vector(unsigned(ipb.r_pnt) + 1);
|
ipb.r_pnt <= std_ulogic_vector(unsigned(ipb.r_pnt) + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process instr_prefetch_buffer_ctrl;
|
end process instr_prefetch_buffer_ctrl;
|
|
|
instr_prefetch_buffer_data: process(clk_i)
|
instr_prefetch_buffer_data: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ipb.we = '1') then -- write port
|
if (ipb.we = '1') then -- write port
|
ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata;
|
ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process instr_prefetch_buffer_data;
|
end process instr_prefetch_buffer_data;
|
|
|
-- async read --
|
-- async read --
|
ipb.rdata <= ipb.data(to_integer(unsigned(ipb.r_pnt(ipb.w_pnt'left-1 downto 0))));
|
ipb.rdata <= ipb.data(to_integer(unsigned(ipb.r_pnt(ipb.r_pnt'left-1 downto 0))));
|
|
|
-- status --
|
-- status --
|
ipb.full <= '1' when (ipb.r_pnt(ipb.r_pnt'left) /= ipb.w_pnt(ipb.w_pnt'left)) and (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
|
ipb.full <= '1' when (ipb.r_pnt(ipb.r_pnt'left) /= ipb.w_pnt(ipb.w_pnt'left)) and (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
|
ipb.empty <= '1' when (ipb.r_pnt(ipb.r_pnt'left) = ipb.w_pnt(ipb.w_pnt'left)) and (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
|
ipb.empty <= '1' when (ipb.r_pnt(ipb.r_pnt'left) = ipb.w_pnt(ipb.w_pnt'left)) and (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
|
|
|
ipb.free <= not ipb.full;
|
ipb.free <= not ipb.full;
|
ipb.avail <= not ipb.empty;
|
ipb.avail <= not ipb.empty;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction)
|
|
-- ****************************************************************************************************************************
|
|
|
|
|
|
-- Issue Engine FSM Sync ------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
|
begin
|
|
if (rstn_i = '0') then
|
|
issue_engine.state <= ISSUE_ACTIVE;
|
|
issue_engine.align <= CPU_BOOT_ADDR(1);
|
|
issue_engine.buf <= (others => '0');
|
|
elsif rising_edge(clk_i) then
|
|
if (ipb.clear = '1') then
|
|
if (CPU_EXTENSION_RISCV_C = true) then
|
|
if (execute_engine.pc(1) = '1') then -- branch to unaligned address?
|
|
issue_engine.state <= ISSUE_REALIGN;
|
|
issue_engine.align <= '1'; -- aligned on 16-bit boundary
|
|
else
|
|
issue_engine.state <= issue_engine.state_nxt;
|
|
issue_engine.align <= '0'; -- aligned on 32-bit boundary
|
|
end if;
|
|
else
|
|
issue_engine.state <= issue_engine.state_nxt;
|
|
issue_engine.align <= '0'; -- always aligned on 32-bit boundaries
|
|
end if;
|
|
else
|
|
issue_engine.state <= issue_engine.state_nxt;
|
|
issue_engine.align <= issue_engine.align_nxt;
|
|
end if;
|
|
issue_engine.buf <= issue_engine.buf_nxt;
|
|
end if;
|
|
end process issue_engine_fsm_sync;
|
|
|
|
|
|
-- Issue Engine FSM Comb ------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
issue_engine_fsm_comb: process(issue_engine, ipb, i_buf, execute_engine, ci_illegal, ci_instr32)
|
|
begin
|
|
-- arbiter defaults --
|
|
issue_engine.state_nxt <= issue_engine.state;
|
|
issue_engine.align_nxt <= issue_engine.align;
|
|
issue_engine.buf_nxt <= issue_engine.buf;
|
|
|
|
-- instruction prefetch buffer interface defaults --
|
|
ipb.re <= '0';
|
|
|
|
-- instruction buffer interface defaults --
|
|
i_buf.we <= '0';
|
|
i_buf.wdata <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
|
|
|
|
-- state machine --
|
|
case issue_engine.state is
|
|
|
|
when ISSUE_ACTIVE => -- issue instruction if available
|
|
-- ------------------------------------------------------------
|
|
if (ipb.avail = '1') then -- instructions available?
|
|
|
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
|
|
if (i_buf.free = '1') then
|
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
|
|
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
|
|
ipb.re <= '1';
|
|
i_buf.wdata <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
|
|
i_buf.we <= '1';
|
|
else -- compressed
|
|
ipb.re <= '1';
|
|
i_buf.wdata <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
|
i_buf.we <= '1';
|
|
issue_engine.align_nxt <= '1';
|
|
end if;
|
|
end if;
|
|
|
|
else -- begin check in HIGH instruction half-word
|
|
if (i_buf.free = '1') then
|
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
|
|
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
|
|
ipb.re <= '1';
|
|
i_buf.wdata <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
|
|
i_buf.we <= '1';
|
|
else -- compressed
|
|
--ipb.re <= '1';
|
|
i_buf.wdata <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
|
i_buf.we <= '1';
|
|
issue_engine.align_nxt <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address
|
|
-- ------------------------------------------------------------
|
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
|
|
if (ipb.avail = '1') then -- instructions available?
|
|
ipb.re <= '1';
|
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
|
end if;
|
|
|
|
when others => -- undefined
|
|
-- ------------------------------------------------------------
|
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
|
|
|
end case;
|
|
end process issue_engine_fsm_comb;
|
|
|
|
-- 16-bit instruction: half-word select --
|
|
ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
|
|
|
|
|
|
-- Compressed Instructions Recoding -------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_decompressor_inst_true:
|
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
|
port map (
|
|
-- instruction input --
|
|
ci_instr16_i => ci_instr16, -- compressed instruction input
|
|
-- instruction output --
|
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_decompressor_inst_false:
|
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
|
ci_instr32 <= (others => '0');
|
|
ci_illegal <= '0';
|
|
end generate;
|
|
|
|
|
|
-- Instruction Buffer ---------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
instruction_buffer_ctrl: process(rstn_i, clk_i)
|
|
begin
|
|
if (rstn_i = '0') then
|
|
i_buf.status <= '0';
|
|
elsif rising_edge(clk_i) then
|
|
if (i_buf.clear = '1') then
|
|
i_buf.status <= '0';
|
|
elsif (i_buf.we = '1') then
|
|
i_buf.status <= '1';
|
|
elsif (i_buf.re = '1') then
|
|
i_buf.status <= '0';
|
|
end if;
|
|
end if;
|
|
end process instruction_buffer_ctrl;
|
|
|
|
instruction_buffer_data: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
if (i_buf.we = '1') and (ipb.clear = '0') then
|
|
i_buf.rdata <= i_buf.wdata;
|
|
end if;
|
|
end if;
|
|
end process instruction_buffer_data;
|
|
|
|
-- status --
|
|
i_buf.free <= not i_buf.status;
|
|
i_buf.avail <= i_buf.status;
|
|
|
|
-- clear i_buf when clearing ipb --
|
|
i_buf.clear <= ipb.clear;
|
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- Instruction Execution
|
-- Instruction Execution
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Immediate Generator --------------------------------------------------------------------
|
-- Immediate Generator --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
imm_gen: process(clk_i)
|
imm_gen: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
when opcode_store_c => -- S-immediate
|
when opcode_store_c => -- S-immediate
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(00) <= execute_engine.i_reg(07);
|
imm_o(00) <= execute_engine.i_reg(07);
|
when opcode_branch_c => -- B-immediate
|
when opcode_branch_c => -- B-immediate
|
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(11) <= execute_engine.i_reg(07);
|
imm_o(11) <= execute_engine.i_reg(07);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(00) <= '0';
|
imm_o(00) <= '0';
|
when opcode_lui_c | opcode_auipc_c => -- U-immediate
|
when opcode_lui_c | opcode_auipc_c => -- U-immediate
|
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
|
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(11 downto 00) <= (others => '0');
|
imm_o(11 downto 00) <= (others => '0');
|
when opcode_jal_c => -- J-immediate
|
when opcode_jal_c => -- J-immediate
|
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(11) <= execute_engine.i_reg(20);
|
imm_o(11) <= execute_engine.i_reg(20);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(00) <= '0';
|
imm_o(00) <= '0';
|
when opcode_syscsr_c => -- CSR-immediate
|
when opcode_syscsr_c => -- CSR-immediate
|
imm_o(31 downto 05) <= (others => '0');
|
imm_o(31 downto 05) <= (others => '0');
|
imm_o(04 downto 00) <= execute_engine.i_reg(19 downto 15);
|
imm_o(04 downto 00) <= execute_engine.i_reg(19 downto 15);
|
when others => -- I-immediate
|
when others => -- I-immediate
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(00) <= execute_engine.i_reg(20);
|
imm_o(00) <= execute_engine.i_reg(20);
|
end case;
|
end case;
|
end if;
|
end if;
|
end process imm_gen;
|
end process imm_gen;
|
|
|
|
|
-- Branch Condition Check -----------------------------------------------------------------
|
-- Branch Condition Check -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
branch_check: process(execute_engine.i_reg, cmp_i)
|
branch_check: process(execute_engine.i_reg, cmp_i)
|
begin
|
begin
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
when funct3_beq_c => -- branch if equal
|
when funct3_beq_c => -- branch if equal
|
execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c);
|
execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c);
|
when funct3_bne_c => -- branch if not equal
|
when funct3_bne_c => -- branch if not equal
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c);
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c);
|
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
execute_engine.branch_taken <= cmp_i(alu_cmp_less_c);
|
execute_engine.branch_taken <= cmp_i(alu_cmp_less_c);
|
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
|
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c);
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c);
|
when others => -- undefined
|
when others => -- undefined
|
execute_engine.branch_taken <= '0';
|
execute_engine.branch_taken <= '0';
|
end case;
|
end case;
|
end process branch_check;
|
end process branch_check;
|
|
|
|
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- for registers that DO require a specific reset state --
|
-- for registers that DO require a specific reset state --
|
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.sleep <= '0';
|
execute_engine.sleep <= '0';
|
execute_engine.if_rst <= '1'; -- instruction fetch is reset after system reset
|
execute_engine.if_rst <= '1'; -- instruction fetch is reset after system reset
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
|
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= execute_engine.last_pc_nxt;
|
execute_engine.last_pc <= execute_engine.last_pc_nxt;
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
execute_engine.if_rst <= execute_engine.if_rst_nxt;
|
execute_engine.if_rst <= execute_engine.if_rst_nxt;
|
end if;
|
end if;
|
end process execute_engine_fsm_sync_rst;
|
end process execute_engine_fsm_sync_rst;
|
|
|
|
|
-- for registers that do NOT require a specific reset state --
|
-- for registers that do NOT require a specific reset state --
|
execute_engine_fsm_sync: process(clk_i)
|
execute_engine_fsm_sync: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
execute_engine.state_prev <= execute_engine.state;
|
execute_engine.state_prev <= execute_engine.state;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_jump <= execute_engine.is_jump_nxt;
|
execute_engine.is_jump <= execute_engine.is_jump_nxt;
|
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
|
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
|
--
|
--
|
ctrl <= ctrl_nxt;
|
ctrl <= ctrl_nxt;
|
end if;
|
end if;
|
end process execute_engine_fsm_sync;
|
end process execute_engine_fsm_sync;
|
|
|
-- next PC --
|
-- next PC --
|
next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
|
|
-- PC output --
|
-- PC output --
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
next_pc_o <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
next_pc_o <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
|
|
|
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine)
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine)
|
begin
|
begin
|
ctrl_o <= ctrl;
|
ctrl_o <= ctrl;
|
-- fast bus access requests --
|
-- fast bus access requests --
|
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;
|
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;
|
-- bus error control --
|
-- bus error control --
|
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
|
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
|
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
|
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
|
-- co-processor operation --
|
-- co-processor operation --
|
ctrl_o(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
|
ctrl_o(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
|
end process ctrl_output;
|
end process ctrl_output;
|
|
|
|
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
execute_engine_fsm_comb: process(execute_engine, fetch_engine, ipb, trap_ctrl, csr, ctrl, csr_acc_valid,
|
execute_engine_fsm_comb: process(execute_engine, fetch_engine, i_buf, trap_ctrl, csr, ctrl, csr_acc_valid,
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alu_res_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
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alu_res_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
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variable alu_immediate_v : std_ulogic;
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variable alu_immediate_v : std_ulogic;
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variable rs1_is_r0_v : std_ulogic;
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variable rs1_is_r0_v : std_ulogic;
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begin
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begin
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-- arbiter defaults --
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-- arbiter defaults --
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execute_engine.state_nxt <= execute_engine.state;
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execute_engine.state_nxt <= execute_engine.state;
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execute_engine.i_reg_nxt <= execute_engine.i_reg;
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execute_engine.i_reg_nxt <= execute_engine.i_reg;
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execute_engine.is_jump_nxt <= '0';
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execute_engine.is_jump_nxt <= '0';
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execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op;
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execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op;
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execute_engine.is_ci_nxt <= execute_engine.is_ci;
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execute_engine.is_ci_nxt <= execute_engine.is_ci;
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execute_engine.pc_nxt <= execute_engine.pc;
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execute_engine.pc_nxt <= execute_engine.pc;
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execute_engine.last_pc_nxt <= execute_engine.last_pc;
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execute_engine.last_pc_nxt <= execute_engine.last_pc;
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execute_engine.sleep_nxt <= execute_engine.sleep;
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execute_engine.sleep_nxt <= execute_engine.sleep;
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execute_engine.if_rst_nxt <= execute_engine.if_rst;
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execute_engine.if_rst_nxt <= execute_engine.if_rst;
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-- instruction dispatch --
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-- instruction dispatch --
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fetch_engine.reset <= '0';
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fetch_engine.reset <= '0';
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ipb.re <= '0';
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i_buf.re <= '0';
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-- trap environment control --
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-- trap environment control --
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trap_ctrl.env_start_ack <= '0';
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trap_ctrl.env_start_ack <= '0';
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trap_ctrl.env_end <= '0';
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trap_ctrl.env_end <= '0';
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-- exception trigger --
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-- exception trigger --
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trap_ctrl.instr_be <= '0';
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trap_ctrl.instr_be <= '0';
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trap_ctrl.instr_ma <= '0';
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trap_ctrl.instr_ma <= '0';
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trap_ctrl.env_call <= '0';
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trap_ctrl.env_call <= '0';
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trap_ctrl.break_point <= '0';
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trap_ctrl.break_point <= '0';
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illegal_compressed <= '0';
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illegal_compressed <= '0';
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-- CSR access --
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-- CSR access --
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csr.we_nxt <= '0';
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csr.we_nxt <= '0';
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csr.re_nxt <= '0';
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csr.re_nxt <= '0';
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-- control defaults --
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-- control defaults --
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ctrl_nxt <= (others => '0'); -- all off at first
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ctrl_nxt <= (others => '0'); -- all off at first
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if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
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if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
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ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU)
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ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU)
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else -- branches
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else -- branches
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ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU)
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ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU)
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end if;
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end if;
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ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
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ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
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ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
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ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
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ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
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ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- default ALU operation: ADD(I)
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- default ALU operation: ADD(I)
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ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (=MULDIV) implemented yet
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ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (=MULDIV) implemented yet
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ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= ctrl(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c); -- keep rd addr
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ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= ctrl(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c); -- keep rd addr
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ctrl_nxt(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= ctrl(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- keep rs1 addr
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ctrl_nxt(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= ctrl(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- keep rs1 addr
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ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= ctrl(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- keep rs2 addr
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ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= ctrl(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- keep rs2 addr
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ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
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ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
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-- is immediate ALU operation? --
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-- is immediate ALU operation? --
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alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1);
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alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1);
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-- is rs1 == r0? --
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-- is rs1 == r0? --
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rs1_is_r0_v := not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
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rs1_is_r0_v := not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
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-- state machine --
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-- state machine --
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case execute_engine.state is
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case execute_engine.state is
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when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) ((and to init r0 with zero if it is a physical register))
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when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) ((and to init r0 with zero if it is a physical register))
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- set reg_file's r0 to zero --
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-- set reg_file's r0 to zero --
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if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero?
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if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero?
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ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= (others => '0'); -- rd addr = r0
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ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= (others => '0'); -- rd addr = r0
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read request)
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read request)
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ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- allow write access to r0
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ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- allow write access to r0
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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end if;
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end if;
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--
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--
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execute_engine.state_nxt <= DISPATCH;
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execute_engine.state_nxt <= DISPATCH;
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when DISPATCH => -- Get new command from instruction prefetch buffer (IPB)
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when DISPATCH => -- Get new command from instruction buffer (I_BUF)
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= ipb.rdata(instr_rd_msb_c downto instr_rd_lsb_c); -- rd addr
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ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= i_buf.rdata(instr_rd_msb_c downto instr_rd_lsb_c); -- rd addr
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ctrl_nxt(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= ipb.rdata(instr_rs1_msb_c downto instr_rs1_lsb_c); -- rs1 addr
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ctrl_nxt(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= i_buf.rdata(instr_rs1_msb_c downto instr_rs1_lsb_c); -- rs1 addr
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ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= ipb.rdata(instr_rs2_msb_c downto instr_rs2_lsb_c); -- rs2 addr
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ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= i_buf.rdata(instr_rs2_msb_c downto instr_rs2_lsb_c); -- rs2 addr
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--
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--
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if (ipb.avail = '1') then -- instruction available?
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if (i_buf.avail = '1') then -- instruction available?
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ipb.re <= '1';
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i_buf.re <= '1';
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--
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--
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execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a de-compressed instruction beeing executed
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execute_engine.is_ci_nxt <= i_buf.rdata(32); -- flag to indicate this is a de-compressed instruction beeing executed
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execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0);
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execute_engine.i_reg_nxt <= i_buf.rdata(31 downto 0);
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execute_engine.if_rst_nxt <= '0';
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execute_engine.if_rst_nxt <= '0';
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--
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--
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trap_ctrl.instr_ma <= ipb.rdata(33); -- misaligned instruction fetch address
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trap_ctrl.instr_ma <= i_buf.rdata(33); -- misaligned instruction fetch address
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trap_ctrl.instr_be <= ipb.rdata(34); -- bus access fault during instrucion fetch
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trap_ctrl.instr_be <= i_buf.rdata(34); -- bus access fault during instrucion fetch
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illegal_compressed <= ipb.rdata(35); -- invalid decompressed instruction
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illegal_compressed <= i_buf.rdata(35); -- invalid decompressed instruction
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--
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--
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if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification
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if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification
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execute_engine.pc_nxt <= execute_engine.next_pc;
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execute_engine.pc_nxt <= execute_engine.next_pc;
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end if;
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end if;
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--
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--
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if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or ((ipb.rdata(33) or ipb.rdata(34)) = '1') then
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if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or ((i_buf.rdata(33) or i_buf.rdata(34)) = '1') then
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execute_engine.state_nxt <= TRAP;
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execute_engine.state_nxt <= TRAP;
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else
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else
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execute_engine.state_nxt <= EXECUTE;
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execute_engine.state_nxt <= EXECUTE;
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end if;
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end if;
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end if;
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end if;
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when TRAP => -- Start trap environment (also used as cpu sleep state)
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when TRAP => -- Start trap environment (also used as cpu sleep state)
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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fetch_engine.reset <= '1';
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fetch_engine.reset <= '1';
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execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
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execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
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if (trap_ctrl.env_start = '1') then -- check here again if we came directly from DISPATCH
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if (trap_ctrl.env_start = '1') then -- check here again if we came directly from DISPATCH
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trap_ctrl.env_start_ack <= '1';
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trap_ctrl.env_start_ack <= '1';
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execute_engine.pc_nxt <= csr.mtvec;
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execute_engine.pc_nxt <= csr.mtvec;
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execute_engine.sleep_nxt <= '0'; -- waky waky
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execute_engine.sleep_nxt <= '0'; -- waky waky
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execute_engine.state_nxt <= SYS_WAIT;
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execute_engine.state_nxt <= SYS_WAIT;
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end if;
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end if;
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when EXECUTE => -- Decode and execute instruction
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when EXECUTE => -- Decode and execute instruction
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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execute_engine.last_pc_nxt <= execute_engine.pc; -- store address of current instruction for commit
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execute_engine.last_pc_nxt <= execute_engine.pc; -- store address of current instruction for commit
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--
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--
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case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
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case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
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when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
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when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
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ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
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ctrl_nxt(ctrl_alu_opb_mux_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
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ctrl_nxt(ctrl_alu_opb_mux_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
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-- cp access? --
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-- cp access? --
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if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and
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if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and
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(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
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(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_cp_c;
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_cp_c;
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execute_engine.is_cp_op_nxt <= '1'; -- use CP
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execute_engine.is_cp_op_nxt <= '1'; -- use CP
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-- ALU operation --
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-- ALU operation --
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else
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else
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU operation (re-coding)
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU operation (re-coding)
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when funct3_sll_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c; -- SLL(I)
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when funct3_sll_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c; -- SLL(I)
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when funct3_slt_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_slt_c; -- SLT(I)
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when funct3_slt_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_slt_c; -- SLT(I)
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when funct3_sltu_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_slt_c; -- SLTU(I)
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when funct3_sltu_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_slt_c; -- SLTU(I)
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when funct3_xor_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_xor_c; -- XOR(I)
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when funct3_xor_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_xor_c; -- XOR(I)
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when funct3_sr_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c; -- SRL(I) / SRA(I)
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when funct3_sr_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c; -- SRL(I) / SRA(I)
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when funct3_or_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- OR(I)
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when funct3_or_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- OR(I)
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when funct3_and_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_and_c; -- AND(I)
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when funct3_and_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_and_c; -- AND(I)
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when others => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- ADD(I) / SUB
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when others => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- ADD(I) / SUB
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end case;
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end case;
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execute_engine.is_cp_op_nxt <= '0'; -- no CP operation
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execute_engine.is_cp_op_nxt <= '0'; -- no CP operation
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end if;
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end if;
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-- ADD/SUB --
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-- ADD/SUB --
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if ((alu_immediate_v = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) or -- not an immediate op and funct7.6 set => SUB
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if ((alu_immediate_v = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) or -- not an immediate op and funct7.6 set => SUB
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or -- SLT operation
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or -- SLT operation
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then -- SLTU operation
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then -- SLTU operation
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ctrl_nxt(ctrl_alu_addsub_c) <= '1'; -- SUB/SLT
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ctrl_nxt(ctrl_alu_addsub_c) <= '1'; -- SUB/SLT
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else
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else
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ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
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ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
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end if;
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end if;
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-- multi cycle alu operation? --
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-- multi cycle alu operation? --
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
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((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
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((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
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execute_engine.state_nxt <= ALU_WAIT;
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execute_engine.state_nxt <= ALU_WAIT;
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else -- single cycle ALU operation
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else -- single cycle ALU operation
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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execute_engine.state_nxt <= DISPATCH;
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execute_engine.state_nxt <= DISPATCH;
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end if;
|
end if;
|
|
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only)
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only)
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
|
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_movb_c; -- actual ALU operation = MOVB
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_movb_c; -- actual ALU operation = MOVB
|
else -- AUIPC
|
else -- AUIPC
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD
|
end if;
|
end if;
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
|
|
when opcode_load_c | opcode_store_c => -- load/store
|
when opcode_load_c | opcode_store_c => -- load/store
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR
|
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR
|
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores)
|
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores)
|
execute_engine.state_nxt <= LOADSTORE_0;
|
execute_engine.state_nxt <= LOADSTORE_0;
|
|
|
when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register)
|
when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD
|
-- compute target address --
|
-- compute target address --
|
if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR
|
if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base)
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base)
|
else -- JAL / branch
|
else -- JAL / branch
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
|
end if;
|
end if;
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
|
-- save return address --
|
-- save return address --
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "10"; -- RF input = next PC (save return address)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "10"; -- RF input = next PC (save return address)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (for JAL/JALR)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (for JAL/JALR)
|
execute_engine.is_jump_nxt <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- is this is a jump operation? (for JAL/JALR)
|
execute_engine.is_jump_nxt <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- is this is a jump operation? (for JAL/JALR)
|
execute_engine.state_nxt <= BRANCH;
|
execute_engine.state_nxt <= BRANCH;
|
|
|
when opcode_fence_c => -- fence operations
|
when opcode_fence_c => -- fence operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- for simplicity: internally, fence and fence.i perform the same operations (flush and reload of instruction prefetch buffer)
|
-- for simplicity: internally, fence and fence.i perform the same operations (flush and reload of instruction prefetch buffer)
|
-- FENCE.I --
|
-- FENCE.I --
|
if (CPU_EXTENSION_RISCV_Zifencei = true) then
|
if (CPU_EXTENSION_RISCV_Zifencei = true) then
|
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction
|
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
-- FENCE --
|
-- FENCE --
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
end if;
|
end if;
|
--
|
--
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
|
when opcode_syscsr_c => -- system/csr access
|
when opcode_syscsr_c => -- system/csr access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= ctrl(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- copy rs1_addr to rs2_addr (for CSR mod)
|
ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= ctrl(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- copy rs1_addr to rs2_addr (for CSR mod)
|
--
|
--
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
when funct12_ecall_c => -- ECALL
|
when funct12_ecall_c => -- ECALL
|
trap_ctrl.env_call <= '1';
|
trap_ctrl.env_call <= '1';
|
when funct12_ebreak_c => -- EBREAK
|
when funct12_ebreak_c => -- EBREAK
|
trap_ctrl.break_point <= '1';
|
trap_ctrl.break_point <= '1';
|
when funct12_mret_c => -- MRET
|
when funct12_mret_c => -- MRET
|
trap_ctrl.env_end <= '1';
|
trap_ctrl.env_end <= '1';
|
execute_engine.pc_nxt <= csr.mepc;
|
execute_engine.pc_nxt <= csr.mepc;
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
when funct12_wfi_c => -- WFI (CPU sleep)
|
when funct12_wfi_c => -- WFI (CPU sleep)
|
execute_engine.sleep_nxt <= '1'; -- good night
|
execute_engine.sleep_nxt <= '1'; -- good night
|
when others => -- undefined
|
when others => -- undefined
|
NULL;
|
NULL;
|
end case;
|
end case;
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
else -- CSR access
|
else -- CSR access
|
csr.re_nxt <= '1'; -- always read CSR (internally)
|
csr.re_nxt <= '1'; -- always read CSR (internally)
|
execute_engine.state_nxt <= CSR_ACCESS;
|
execute_engine.state_nxt <= CSR_ACCESS;
|
end if;
|
end if;
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
|
|
end case;
|
end case;
|
|
|
when CSR_ACCESS => -- write CSR data to RF, write ALU.res to CSR
|
when CSR_ACCESS => -- write CSR data to RF, write ALU.res to CSR
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- OPB = rs2 (which is rs1 here) / immediate
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- OPB = rs2 (which is rs1 here) / immediate
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_movb_c; -- actual ALU operation = MOVB
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_movb_c; -- actual ALU operation = MOVB
|
-- CSR write access --
|
-- CSR write access --
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I)
|
when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I)
|
csr.we_nxt <= csr_acc_valid; -- always write CSR if valid access
|
csr.we_nxt <= csr_acc_valid; -- always write CSR if valid access
|
when funct3_csrrs_c | funct3_csrrsi_c | funct3_csrrc_c | funct3_csrrci_c => -- CSRRS(I) / CSRRC(I)
|
when funct3_csrrs_c | funct3_csrrsi_c | funct3_csrrc_c | funct3_csrrci_c => -- CSRRS(I) / CSRRC(I)
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1/imm is not zero and if valid access
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1/imm is not zero and if valid access
|
when others => -- invalid
|
when others => -- invalid
|
csr.we_nxt <= '0';
|
csr.we_nxt <= '0';
|
end case;
|
end case;
|
-- register file write back --
|
-- register file write back --
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= SYS_WAIT; -- have another cycle to let side-effects kick in (FIXME?)
|
execute_engine.state_nxt <= SYS_WAIT; -- have another cycle to let side-effects kick in (FIXME?)
|
|
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (shifter or CP) to finish
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (shifter or CP) to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
|
-- cp access or alu shift? --
|
-- cp access or alu shift? --
|
if (execute_engine.is_cp_op = '1') then
|
if (execute_engine.is_cp_op = '1') then
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_cp_c;
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_cp_c;
|
else
|
else
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c;
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c;
|
end if;
|
end if;
|
-- wait for result --
|
-- wait for result --
|
if (alu_wait_i = '0') then
|
if (alu_wait_i = '0') then
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
when BRANCH => -- update PC for taken branches and jumps
|
when BRANCH => -- update PC for taken branches and jumps
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then
|
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then
|
execute_engine.pc_nxt <= alu_res_i; -- branch/jump destination
|
execute_engine.pc_nxt <= alu_res_i; -- branch/jump destination
|
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
else
|
else
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
when LOADSTORE_0 => -- trigger memory request
|
when LOADSTORE_0 => -- trigger memory request
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
else -- STORE
|
else -- STORE
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
|
end if;
|
end if;
|
execute_engine.state_nxt <= LOADSTORE_1;
|
execute_engine.state_nxt <= LOADSTORE_1;
|
|
|
when LOADSTORE_1 => -- memory latency
|
when LOADSTORE_1 => -- memory latency
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
|
execute_engine.state_nxt <= LOADSTORE_2;
|
execute_engine.state_nxt <= LOADSTORE_2;
|
|
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
|
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
|
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
end if;
|
end if;
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
|
end case;
|
end case;
|
end process execute_engine_fsm_comb;
|
end process execute_engine_fsm_comb;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Invalid Instruction / CSR access check
|
-- Invalid Instruction / CSR access check
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Illegal CSR Access Check ---------------------------------------------------------------
|
-- Illegal CSR Access Check ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
invalid_csr_access_check: process(execute_engine.i_reg, csr.privilege)
|
invalid_csr_access_check: process(execute_engine.i_reg, csr.privilege)
|
variable is_m_mode_v : std_ulogic;
|
variable is_m_mode_v : std_ulogic;
|
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
|
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
|
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
|
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
|
begin
|
begin
|
-- are we in machine mode? --
|
-- are we in machine mode? --
|
if (csr.privilege = priv_mode_m_c) then
|
if (csr.privilege = priv_mode_m_c) then
|
is_m_mode_v := '1';
|
is_m_mode_v := '1';
|
else
|
else
|
is_m_mode_v := '0';
|
is_m_mode_v := '0';
|
end if;
|
end if;
|
|
|
-- is this CSR instruction really going to write/read to/from a CSR? --
|
-- is this CSR instruction really going to write/read to/from a CSR? --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
|
csr_wacc_v := '1'; -- always write CSR
|
csr_wacc_v := '1'; -- always write CSR
|
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
|
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
|
else
|
else
|
csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
|
csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
|
-- csr_racc_v := '1'; -- always read CSR
|
-- csr_racc_v := '1'; -- always read CSR
|
end if;
|
end if;
|
|
|
-- check CSR access --
|
-- check CSR access --
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
when csr_mstatus_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mstatus_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_misa_c => csr_acc_valid <= is_m_mode_v;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only for the NEORV32 but we don't cause an exception here for compatibility
|
when csr_misa_c => csr_acc_valid <= is_m_mode_v;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only for the NEORV32 but we don't cause an exception here for compatibility
|
when csr_mie_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mie_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mtvec_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mtvec_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mscratch_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mscratch_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mepc_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mepc_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mcause_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mcause_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mtval_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mtval_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mip_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mip_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
--
|
--
|
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
|
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
|
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
|
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
|
--
|
--
|
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 2)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 2)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 3)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 3)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 4)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 4)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 6)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 6)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v; -- M-mode only
|
--
|
--
|
when csr_mcycle_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mcycle_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_minstret_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_minstret_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
--
|
--
|
when csr_mcycleh_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mcycleh_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_minstreth_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_minstreth_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
--
|
--
|
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_time_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_time_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
--
|
--
|
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
--
|
--
|
when csr_mvendorid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mvendorid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_marchid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_marchid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mimpid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mimpid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mhartid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mhartid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
--
|
--
|
when csr_mzext_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mzext_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
--
|
--
|
when others => csr_acc_valid <= '0'; -- undefined, invalid access
|
when others => csr_acc_valid <= '0'; -- undefined, invalid access
|
end case;
|
end case;
|
end process invalid_csr_access_check;
|
end process invalid_csr_access_check;
|
|
|
|
|
-- Illegal Instruction Check --------------------------------------------------------------
|
-- Illegal Instruction Check --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
illegal_instruction_check: process(execute_engine, csr_acc_valid)
|
illegal_instruction_check: process(execute_engine, csr_acc_valid)
|
begin
|
begin
|
-- illegal instructions are checked in the EXECUTE stage
|
-- illegal instructions are checked in the EXECUTE stage
|
-- the execute engine will only commit valid instructions
|
-- the execute engine will only commit valid instructions
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
-- defaults --
|
-- defaults --
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
illegal_register <= '0';
|
illegal_register <= '0';
|
|
|
-- check instructions --
|
-- check instructions --
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
|
|
-- OPCODE check sufficient: LUI, UIPC, JAL --
|
-- OPCODE check sufficient: LUI, UIPC, JAL --
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and (execute_engine.i_reg(instr_rd_msb_c) = '1') then
|
if (CPU_EXTENSION_RISCV_E = true) and (execute_engine.i_reg(instr_rd_msb_c) = '1') then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_alui_c => -- check ALUI funct7
|
when opcode_alui_c => -- check ALUI funct7
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
else
|
else
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_load_c => -- check LOAD funct3
|
when opcode_load_c => -- check LOAD funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_store_c => -- check STORE funct3
|
when opcode_store_c => -- check STORE funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_branch_c => -- check BRANCH funct3
|
when opcode_branch_c => -- check BRANCH funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_jalr_c => -- check JALR funct3
|
when opcode_jalr_c => -- check JALR funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_alu_c => -- check ALU funct3 & funct7
|
when opcode_alu_c => -- check ALU funct3 & funct7
|
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
|
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
|
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
|
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
else
|
else
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and
|
if (CPU_EXTENSION_RISCV_E = true) and
|
((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_fence_c => -- fence instructions --
|
when opcode_fence_c => -- fence instructions --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
|
when opcode_syscsr_c => -- check system instructions --
|
when opcode_syscsr_c => -- check system instructions --
|
-- CSR access --
|
-- CSR access --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c) then
|
-- valid CSR access? --
|
-- valid CSR access? --
|
if (csr_acc_valid = '1') then
|
if (csr_acc_valid = '1') then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) then
|
if (CPU_EXTENSION_RISCV_E = true) then
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
else -- reg-imm CSR
|
else -- reg-imm CSR
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- ecall, ebreak, mret, wfi --
|
-- ecall, ebreak, mret, wfi --
|
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
|
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
|
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
|
when others => -- compressed instruction or undefined instruction
|
when others => -- compressed instruction or undefined instruction
|
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode
|
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
|
end case;
|
end case;
|
else
|
else
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
illegal_register <= '0';
|
illegal_register <= '0';
|
end if;
|
end if;
|
end process illegal_instruction_check;
|
end process illegal_instruction_check;
|
|
|
-- any illegal condition? --
|
-- any illegal condition? --
|
trap_ctrl.instr_il <= illegal_instruction or illegal_register or illegal_compressed;
|
trap_ctrl.instr_il <= illegal_instruction or illegal_register or illegal_compressed;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Exception and Interrupt Control
|
-- Exception and Interrupt Control
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Trap Controller ------------------------------------------------------------------------
|
-- Trap Controller ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_controller: process(rstn_i, clk_i)
|
trap_controller: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.cause <= (others => '0');
|
trap_ctrl.cause <= (others => '0');
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
-- exception buffer: misaligned load/store/instruction address
|
-- exception buffer: misaligned load/store/instruction address
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
|
-- exception buffer: load/store/instruction bus access error
|
-- exception buffer: load/store/instruction bus access error
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
-- exception buffer: illegal instruction / env call / break point
|
-- exception buffer: illegal instruction / env call / break point
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
-- interrupt buffer: machine software/external/timer interrupt
|
-- interrupt buffer: machine software/external/timer interrupt
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
|
-- interrupt buffer: custom fast interrupts
|
-- interrupt buffer: custom fast interrupts
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c));
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c));
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not trap_ctrl.irq_ack(interrupt_firq_1_c));
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not trap_ctrl.irq_ack(interrupt_firq_1_c));
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not trap_ctrl.irq_ack(interrupt_firq_2_c));
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not trap_ctrl.irq_ack(interrupt_firq_2_c));
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not trap_ctrl.irq_ack(interrupt_firq_3_c));
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not trap_ctrl.irq_ack(interrupt_firq_3_c));
|
|
|
-- trap control --
|
-- trap control --
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only -> continue execution even if permanent IRQ
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only -> continue execution even if permanent IRQ
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
end if;
|
end if;
|
else -- trap waiting to get started
|
else -- trap waiting to get started
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process trap_controller;
|
end process trap_controller;
|
|
|
-- any exception/interrupt? --
|
-- any exception/interrupt? --
|
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
|
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
|
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
|
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
|
|
|
|
|
-- Trap Priority Detector -----------------------------------------------------------------
|
-- Trap Priority Detector -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_priority: process(trap_ctrl)
|
trap_priority: process(trap_ctrl)
|
begin
|
begin
|
-- defaults --
|
-- defaults --
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
|
|
-- the following traps are caused by asynchronous exceptions (-> interrupts)
|
-- the following traps are caused by asynchronous exceptions (-> interrupts)
|
-- here we do need a specific acknowledge mask since several sources can trigger at once
|
-- here we do need a specific acknowledge mask since several sources can trigger at once
|
|
|
-- interrupt: 1.11 machine external interrupt --
|
-- interrupt: 1.11 machine external interrupt --
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
|
|
-- interrupt: 1.7 machine timer interrupt --
|
-- interrupt: 1.7 machine timer interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
|
|
-- interrupt: 1.3 machine SW interrupt --
|
-- interrupt: 1.3 machine SW interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
|
|
|
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
|
|
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq1_c;
|
trap_ctrl.cause_nxt <= trap_firq1_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1';
|
|
|
-- interrupt: 1.18 fast interrupt channel 2 --
|
-- interrupt: 1.18 fast interrupt channel 2 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq2_c;
|
trap_ctrl.cause_nxt <= trap_firq2_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1';
|
|
|
-- interrupt: 1.19 fast interrupt channel 3 --
|
-- interrupt: 1.19 fast interrupt channel 3 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq3_c;
|
trap_ctrl.cause_nxt <= trap_firq3_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
|
|
|
|
|
-- the following traps are caused by synchronous exceptions
|
-- the following traps are caused by synchronous exceptions
|
-- here we do not need a specific acknowledge mask since only one exception (the one
|
-- here we do not need a specific acknowledge mask since only one exception (the one
|
-- with highest priority) can trigger at once
|
-- with highest priority) can trigger at once
|
|
|
-- trap/fault: 0.1 instruction access fault --
|
-- trap/fault: 0.1 instruction access fault --
|
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_iba_c;
|
trap_ctrl.cause_nxt <= trap_iba_c;
|
|
|
-- trap/fault: 0.2 illegal instruction --
|
-- trap/fault: 0.2 illegal instruction --
|
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_iil_c;
|
trap_ctrl.cause_nxt <= trap_iil_c;
|
|
|
-- trap/fault: 0.0 instruction address misaligned --
|
-- trap/fault: 0.0 instruction address misaligned --
|
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_ima_c;
|
trap_ctrl.cause_nxt <= trap_ima_c;
|
|
|
|
|
-- trap/fault: 0.11 environment call from M-mode --
|
-- trap/fault: 0.11 environment call from M-mode --
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_menv_c;
|
trap_ctrl.cause_nxt <= trap_menv_c;
|
|
|
-- trap/fault: 0.3 breakpoint --
|
-- trap/fault: 0.3 breakpoint --
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_brk_c;
|
trap_ctrl.cause_nxt <= trap_brk_c;
|
|
|
|
|
-- trap/fault: 0.6 store address misaligned -
|
-- trap/fault: 0.6 store address misaligned -
|
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_sma_c;
|
trap_ctrl.cause_nxt <= trap_sma_c;
|
|
|
-- trap/fault: 0.4 load address misaligned --
|
-- trap/fault: 0.4 load address misaligned --
|
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_lma_c;
|
trap_ctrl.cause_nxt <= trap_lma_c;
|
|
|
-- trap/fault: 0.7 store access fault --
|
-- trap/fault: 0.7 store access fault --
|
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_sbe_c;
|
trap_ctrl.cause_nxt <= trap_sbe_c;
|
|
|
-- trap/fault: 0.5 load access fault --
|
-- trap/fault: 0.5 load access fault --
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_lbe_c;
|
trap_ctrl.cause_nxt <= trap_lbe_c;
|
|
|
-- undefined / not implemented --
|
-- undefined / not implemented --
|
else
|
else
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
end if;
|
end if;
|
end process trap_priority;
|
end process trap_priority;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Control and Status Registers (CSRs)
|
-- Control and Status Registers (CSRs)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Control and Status Registers Write Data ------------------------------------------------
|
-- Control and Status Registers Write Data ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_write_data: process(execute_engine.i_reg, csr.rdata, alu_res_i)
|
csr_write_data: process(execute_engine.i_reg, csr.rdata, alu_res_i)
|
begin
|
begin
|
-- "mini ALU" for CSR update operations --
|
-- "mini ALU" for CSR update operations --
|
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
|
when "10" => csr.wdata <= csr.rdata or alu_res_i; -- CSRRS(I)
|
when "10" => csr.wdata <= csr.rdata or alu_res_i; -- CSRRS(I)
|
when "11" => csr.wdata <= csr.rdata and (not alu_res_i); -- CSRRC(I)
|
when "11" => csr.wdata <= csr.rdata and (not alu_res_i); -- CSRRC(I)
|
when others => csr.wdata <= alu_res_i; -- CSRRW(I)
|
when others => csr.wdata <= alu_res_i; -- CSRRW(I)
|
end case;
|
end case;
|
end process csr_write_data;
|
end process csr_write_data;
|
|
|
|
|
-- Control and Status Registers Write Access ----------------------------------------------
|
-- Control and Status Registers Write Access ----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_write_access: process(rstn_i, clk_i)
|
csr_write_access: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
csr.we <= '0';
|
csr.we <= '0';
|
--
|
--
|
csr.mstatus_mie <= '0';
|
csr.mstatus_mie <= '0';
|
csr.mstatus_mpie <= '0';
|
csr.mstatus_mpie <= '0';
|
csr.mstatus_mpp <= priv_mode_m_c; -- start in MACHINE mode
|
csr.mstatus_mpp <= priv_mode_m_c; -- start in MACHINE mode
|
csr.privilege <= priv_mode_m_c; -- start in MACHINE mode
|
csr.privilege <= priv_mode_m_c; -- start in MACHINE mode
|
csr.mie_msie <= '0';
|
csr.mie_msie <= '0';
|
csr.mie_meie <= '0';
|
csr.mie_meie <= '0';
|
csr.mie_mtie <= '0';
|
csr.mie_mtie <= '0';
|
csr.mie_firqe <= (others => '0');
|
csr.mie_firqe <= (others => '0');
|
csr.mtvec <= (others => '0');
|
csr.mtvec <= (others => '0');
|
csr.mscratch <= (others => '0');
|
csr.mscratch <= (others => '0');
|
csr.mepc <= (others => '0');
|
csr.mepc <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mtval <= (others => '0');
|
csr.mtval <= (others => '0');
|
csr.pmpcfg <= (others => (others => '0'));
|
csr.pmpcfg <= (others => (others => '0'));
|
csr.pmpaddr <= (others => (others => '0'));
|
csr.pmpaddr <= (others => (others => '0'));
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
|
|
-- write access? --
|
-- write access? --
|
csr.we <= csr.we_nxt;
|
csr.we <= csr.we_nxt;
|
|
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSRs that can be written by application software only
|
-- CSRs that can be written by application software only
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.we = '1') then -- manual update
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.we = '1') then -- manual update
|
|
|
-- machine CSRs --
|
-- machine CSRs --
|
if (execute_engine.i_reg(31 downto 28) = csr_mie_c(11 downto 8)) then
|
if (execute_engine.i_reg(31 downto 28) = csr_mie_c(11 downto 8)) then
|
|
|
-- machine trap setup --
|
-- machine trap setup --
|
if (execute_engine.i_reg(27 downto 24) = csr_mie_c(7 downto 4)) then
|
if (execute_engine.i_reg(27 downto 24) = csr_mie_c(7 downto 4)) then
|
if (execute_engine.i_reg(23 downto 20) = csr_mie_c(3 downto 0)) then -- R/W: mie - machine interrupt-enable register
|
if (execute_engine.i_reg(23 downto 20) = csr_mie_c(3 downto 0)) then -- R/W: mie - machine interrupt-enable register
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
--
|
--
|
csr.mie_firqe(0) <= csr.wdata(16); -- fast interrupt channel 0
|
csr.mie_firqe(0) <= csr.wdata(16); -- fast interrupt channel 0
|
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1
|
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1
|
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2
|
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2
|
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3
|
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3
|
end if;
|
end if;
|
if (execute_engine.i_reg(23 downto 20) = csr_mtvec_c(3 downto 0)) then -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
if (execute_engine.i_reg(23 downto 20) = csr_mtvec_c(3 downto 0)) then -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- machine trap handling --
|
-- machine trap handling --
|
if (execute_engine.i_reg(27 downto 20) = csr_mscratch_c(7 downto 0)) then -- R/W: mscratch - machine scratch register
|
if (execute_engine.i_reg(27 downto 20) = csr_mscratch_c(7 downto 0)) then -- R/W: mscratch - machine scratch register
|
csr.mscratch <= csr.wdata;
|
csr.mscratch <= csr.wdata;
|
end if;
|
end if;
|
|
|
-- machine physical memory protection (pmp) --
|
-- machine physical memory protection (pmp) --
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
-- pmpcfg --
|
-- pmpcfg --
|
if (execute_engine.i_reg(27 downto 24) = csr_pmpcfg0_c(7 downto 4)) then
|
if (execute_engine.i_reg(27 downto 24) = csr_pmpcfg0_c(7 downto 4)) then
|
if (PMP_NUM_REGIONS >= 1) then
|
if (PMP_NUM_REGIONS >= 1) then
|
if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg0_c(3 downto 0)) then -- pmpcfg0
|
if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg0_c(3 downto 0)) then -- pmpcfg0
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
if ((j+1) <= PMP_NUM_REGIONS) then
|
if ((j+1) <= PMP_NUM_REGIONS) then
|
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
|
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
|
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R
|
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R
|
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W
|
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W
|
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X
|
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X
|
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(0+j)(5) <= '0'; -- reserved
|
csr.pmpcfg(0+j)(5) <= '0'; -- reserved
|
csr.pmpcfg(0+j)(6) <= '0'; -- reserved
|
csr.pmpcfg(0+j)(6) <= '0'; -- reserved
|
csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L
|
csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L
|
end if;
|
end if;
|
end if;
|
end if;
|
end loop; -- j (bytes in CSR)
|
end loop; -- j (bytes in CSR)
|
end if;
|
end if;
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 5) then
|
if (PMP_NUM_REGIONS >= 5) then
|
if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg1_c(3 downto 0)) then -- pmpcfg1
|
if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg1_c(3 downto 0)) then -- pmpcfg1
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
if ((j+1+4) <= PMP_NUM_REGIONS) then
|
if ((j+1+4) <= PMP_NUM_REGIONS) then
|
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
|
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
|
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R
|
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R
|
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W
|
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W
|
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X
|
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X
|
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(4+j)(5) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(5) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(6) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(6) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L
|
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L
|
end if;
|
end if;
|
end if;
|
end if;
|
end loop; -- j (bytes in CSR)
|
end loop; -- j (bytes in CSR)
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
-- pmpaddr --
|
-- pmpaddr --
|
if (execute_engine.i_reg(27 downto 24) = csr_pmpaddr0_c(7 downto 4)) then
|
if (execute_engine.i_reg(27 downto 24) = csr_pmpaddr0_c(7 downto 4)) then
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
if (execute_engine.i_reg(23 downto 20) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
if (execute_engine.i_reg(23 downto 20) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
csr.pmpaddr(i) <= csr.wdata(31 downto 1) & '0'; -- min granularity is 8 bytes -> bit zero cannot be configured
|
csr.pmpaddr(i) <= csr.wdata(31 downto 1) & '0'; -- min granularity is 8 bytes -> bit zero cannot be configured
|
end if;
|
end if;
|
end loop; -- i (CSRs)
|
end loop; -- i (CSRs)
|
end if;
|
end if;
|
end if; -- implement PMP at all?
|
end if; -- implement PMP at all?
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSRs that can be written by application and hardware (application access)
|
-- CSRs that can be written by application and hardware (application access)
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.we = '1') then -- manual update
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.we = '1') then -- manual update
|
|
|
-- machine CSRs --
|
-- machine CSRs --
|
if (execute_engine.i_reg(31 downto 28) = csr_mstatus_c(11 downto 8)) then
|
if (execute_engine.i_reg(31 downto 28) = csr_mstatus_c(11 downto 8)) then
|
|
|
-- machine trap setup --
|
-- machine trap setup --
|
if (execute_engine.i_reg(27 downto 20) = csr_mstatus_c(7 downto 0)) then -- R/W: mstatus - machine status register
|
if (execute_engine.i_reg(27 downto 20) = csr_mstatus_c(7 downto 0)) then -- R/W: mstatus - machine status register
|
csr.mstatus_mie <= csr.wdata(03);
|
csr.mstatus_mie <= csr.wdata(03);
|
csr.mstatus_mpie <= csr.wdata(07);
|
csr.mstatus_mpie <= csr.wdata(07);
|
--
|
--
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- machine trap handling --
|
-- machine trap handling --
|
if (execute_engine.i_reg(27 downto 24) = csr_mepc_c(7 downto 4)) then
|
if (execute_engine.i_reg(27 downto 24) = csr_mepc_c(7 downto 4)) then
|
if (execute_engine.i_reg(23 downto 20) = csr_mepc_c(3 downto 0)) then -- R/W: mepc - machine exception program counter
|
if (execute_engine.i_reg(23 downto 20) = csr_mepc_c(3 downto 0)) then -- R/W: mepc - machine exception program counter
|
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
|
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
|
end if;
|
end if;
|
if (execute_engine.i_reg(23 downto 20) = csr_mcause_c(3 downto 0)) then -- R/W: mcause - machine trap cause
|
if (execute_engine.i_reg(23 downto 20) = csr_mcause_c(3 downto 0)) then -- R/W: mcause - machine trap cause
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
|
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
|
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
|
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
|
end if;
|
end if;
|
if (execute_engine.i_reg(23 downto 20) = csr_mtval_c(3 downto 0)) then -- R/W: mtval - machine bad address or instruction
|
if (execute_engine.i_reg(23 downto 20) = csr_mtval_c(3 downto 0)) then -- R/W: mtval - machine bad address or instruction
|
csr.mtval <= csr.wdata;
|
csr.mtval <= csr.wdata;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSRs that can be written by application and hardware (hardware access)
|
-- CSRs that can be written by application and hardware (hardware access)
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
else -- hardware update
|
else -- hardware update
|
|
|
-- mepc & mtval: machine exception PC & machine trap value register --
|
-- mepc & mtval: machine exception PC & machine trap value register --
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (is mcause(31))
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (is mcause(31))
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mtval <= (others => '0'); -- mtval is zero for interrupts
|
csr.mtval <= (others => '0'); -- mtval is zero for interrupts
|
else -- for EXCEPTIONS (according to their priority)
|
else -- for EXCEPTIONS (according to their priority)
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instruction access error OR
|
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instruction access error OR
|
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction address OR
|
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction address OR
|
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR
|
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR
|
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- environment call
|
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- environment call
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction
|
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction
|
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself
|
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself
|
else -- load/store misalignments/access errors
|
else -- load/store misalignments/access errors
|
csr.mtval <= mar_i; -- faulting data access address
|
csr.mtval <= mar_i; -- faulting data access address
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- mstatus: context switch --
|
-- mstatus: context switch --
|
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
|
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
|
-- trap ID code --
|
-- trap ID code --
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
|
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
|
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
|
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
|
--
|
--
|
csr.mstatus_mie <= '0'; -- disable interrupts
|
csr.mstatus_mie <= '0'; -- disable interrupts
|
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
|
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
|
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
|
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
|
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
|
end if;
|
end if;
|
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception
|
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception
|
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
|
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
|
csr.mstatus_mpie <= '1';
|
csr.mstatus_mpie <= '1';
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
|
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
|
csr.mstatus_mpp <= priv_mode_u_c;
|
csr.mstatus_mpp <= priv_mode_u_c;
|
end if;
|
end if;
|
end if;
|
end if;
|
-- user mode NOT implemented --
|
-- user mode NOT implemented --
|
if (CPU_EXTENSION_RISCV_U = false) then
|
if (CPU_EXTENSION_RISCV_U = false) then
|
csr.privilege <= priv_mode_m_c;
|
csr.privilege <= priv_mode_m_c;
|
csr.mstatus_mpp <= priv_mode_m_c;
|
csr.mstatus_mpp <= priv_mode_m_c;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process csr_write_access;
|
end process csr_write_access;
|
|
|
|
|
-- Control and Status Registers Read Access -----------------------------------------------
|
-- Control and Status Registers Read Access -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_read_access: process(clk_i)
|
csr_read_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
csr.rdata <= (others => '0'); -- default
|
csr.rdata <= (others => '0'); -- default
|
csr.re <= csr.re_nxt; -- read access?
|
csr.re <= csr.re_nxt; -- read access?
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
|
|
-- machine trap setup --
|
-- machine trap setup --
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
|
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
|
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
|
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
|
when csr_misa_c => -- R/-: misa - ISA and extensions
|
when csr_misa_c => -- R/-: misa - ISA and extensions
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension
|
csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension
|
csr.rdata(23) <= '1'; -- X CPU extension (non-std extensions)
|
csr.rdata(23) <= '1'; -- X CPU extension (non-std extensions)
|
csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
|
csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
|
csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
|
csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
|
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
|
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
|
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
|
csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
|
csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
|
--
|
--
|
csr.rdata(16) <= csr.mie_firqe(0); -- fast interrupt channel 0
|
csr.rdata(16) <= csr.mie_firqe(0); -- fast interrupt channel 0
|
csr.rdata(17) <= csr.mie_firqe(1); -- fast interrupt channel 1
|
csr.rdata(17) <= csr.mie_firqe(1); -- fast interrupt channel 1
|
csr.rdata(18) <= csr.mie_firqe(2); -- fast interrupt channel 2
|
csr.rdata(18) <= csr.mie_firqe(2); -- fast interrupt channel 2
|
csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3
|
csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
|
|
-- machine trap handling --
|
-- machine trap handling --
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
csr.rdata <= csr.mscratch;
|
csr.rdata <= csr.mscratch;
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
when csr_mcause_c => -- R/-: mcause - machine trap cause
|
when csr_mcause_c => -- R/-: mcause - machine trap cause
|
csr.rdata <= csr.mcause;
|
csr.rdata <= csr.mcause;
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
csr.rdata <= csr.mtval;
|
csr.rdata <= csr.mtval;
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
|
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
|
csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
|
csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
|
csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
|
csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
|
--
|
--
|
csr.rdata(16) <= trap_ctrl.irq_buf(interrupt_firq_0_c);
|
csr.rdata(16) <= trap_ctrl.irq_buf(interrupt_firq_0_c);
|
csr.rdata(17) <= trap_ctrl.irq_buf(interrupt_firq_1_c);
|
csr.rdata(17) <= trap_ctrl.irq_buf(interrupt_firq_1_c);
|
csr.rdata(18) <= trap_ctrl.irq_buf(interrupt_firq_2_c);
|
csr.rdata(18) <= trap_ctrl.irq_buf(interrupt_firq_2_c);
|
csr.rdata(19) <= trap_ctrl.irq_buf(interrupt_firq_3_c);
|
csr.rdata(19) <= trap_ctrl.irq_buf(interrupt_firq_3_c);
|
|
|
-- physical memory protection --
|
-- physical memory protection --
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - physical memory protection configuration register 0
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - physical memory protection configuration register 0
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
if (PMP_NUM_REGIONS >= 1) then
|
if (PMP_NUM_REGIONS >= 1) then
|
csr.rdata(07 downto 00) <= csr.pmpcfg(0);
|
csr.rdata(07 downto 00) <= csr.pmpcfg(0);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 2) then
|
if (PMP_NUM_REGIONS >= 2) then
|
csr.rdata(15 downto 08) <= csr.pmpcfg(1);
|
csr.rdata(15 downto 08) <= csr.pmpcfg(1);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 3) then
|
if (PMP_NUM_REGIONS >= 3) then
|
csr.rdata(23 downto 16) <= csr.pmpcfg(2);
|
csr.rdata(23 downto 16) <= csr.pmpcfg(2);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 4) then
|
if (PMP_NUM_REGIONS >= 4) then
|
csr.rdata(31 downto 24) <= csr.pmpcfg(3);
|
csr.rdata(31 downto 24) <= csr.pmpcfg(3);
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - physical memory protection configuration register 1
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - physical memory protection configuration register 1
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
if (PMP_NUM_REGIONS >= 5) then
|
if (PMP_NUM_REGIONS >= 5) then
|
csr.rdata(07 downto 00) <= csr.pmpcfg(4);
|
csr.rdata(07 downto 00) <= csr.pmpcfg(4);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 6) then
|
if (PMP_NUM_REGIONS >= 6) then
|
csr.rdata(15 downto 08) <= csr.pmpcfg(5);
|
csr.rdata(15 downto 08) <= csr.pmpcfg(5);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 7) then
|
if (PMP_NUM_REGIONS >= 7) then
|
csr.rdata(23 downto 16) <= csr.pmpcfg(6);
|
csr.rdata(23 downto 16) <= csr.pmpcfg(6);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 8) then
|
if (PMP_NUM_REGIONS >= 8) then
|
csr.rdata(31 downto 24) <= csr.pmpcfg(7);
|
csr.rdata(31 downto 24) <= csr.pmpcfg(7);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when csr_pmpaddr0_c => -- R/W: pmpaddr0 - physical memory protection address register 0
|
when csr_pmpaddr0_c => -- R/W: pmpaddr0 - physical memory protection address register 0
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 1) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 1) then
|
csr.rdata <= csr.pmpaddr(0);
|
csr.rdata <= csr.pmpaddr(0);
|
if (csr.pmpcfg(0)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(0)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr1_c => -- R/W: pmpaddr1 - physical memory protection address register 1
|
when csr_pmpaddr1_c => -- R/W: pmpaddr1 - physical memory protection address register 1
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 2) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 2) then
|
csr.rdata <= csr.pmpaddr(1);
|
csr.rdata <= csr.pmpaddr(1);
|
if (csr.pmpcfg(1)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(1)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr2_c => -- R/W: pmpaddr2 - physical memory protection address register 2
|
when csr_pmpaddr2_c => -- R/W: pmpaddr2 - physical memory protection address register 2
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 3) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 3) then
|
csr.rdata <= csr.pmpaddr(2);
|
csr.rdata <= csr.pmpaddr(2);
|
if (csr.pmpcfg(2)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(2)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr3_c => -- R/W: pmpaddr3 - physical memory protection address register 3
|
when csr_pmpaddr3_c => -- R/W: pmpaddr3 - physical memory protection address register 3
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 4) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 4) then
|
csr.rdata <= csr.pmpaddr(3);
|
csr.rdata <= csr.pmpaddr(3);
|
if (csr.pmpcfg(3)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(3)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr4_c => -- R/W: pmpaddr4 - physical memory protection address register 4
|
when csr_pmpaddr4_c => -- R/W: pmpaddr4 - physical memory protection address register 4
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 5) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 5) then
|
csr.rdata <= csr.pmpaddr(4);
|
csr.rdata <= csr.pmpaddr(4);
|
if (csr.pmpcfg(4)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(4)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr5_c => -- R/W: pmpaddr5 - physical memory protection address register 5
|
when csr_pmpaddr5_c => -- R/W: pmpaddr5 - physical memory protection address register 5
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 6) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 6) then
|
csr.rdata <= csr.pmpaddr(5);
|
csr.rdata <= csr.pmpaddr(5);
|
if (csr.pmpcfg(5)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(5)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr6_c => -- R/W: pmpaddr6 - physical memory protection address register 6
|
when csr_pmpaddr6_c => -- R/W: pmpaddr6 - physical memory protection address register 6
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 7) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 7) then
|
csr.rdata <= csr.pmpaddr(6);
|
csr.rdata <= csr.pmpaddr(6);
|
if (csr.pmpcfg(6)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(6)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr7_c => -- R/W: pmpaddr7 - physical memory protection address register 7
|
when csr_pmpaddr7_c => -- R/W: pmpaddr7 - physical memory protection address register 7
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 8) then
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 8) then
|
csr.rdata <= csr.pmpaddr(7);
|
csr.rdata <= csr.pmpaddr(7);
|
if (csr.pmpcfg(7)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(7)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
else -- mode = NAPOT
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- counters and timers --
|
-- counters and timers --
|
when csr_cycle_c | csr_mcycle_c => -- R/(W): [m]cycle: Cycle counter LOW
|
when csr_cycle_c | csr_mcycle_c => -- R/(W): [m]cycle: Cycle counter LOW
|
csr.rdata <= csr.mcycle(31 downto 0);
|
csr.rdata <= csr.mcycle(31 downto 0);
|
when csr_time_c => -- R/-: time: System time LOW (from MTIME unit)
|
when csr_time_c => -- R/-: time: System time LOW (from MTIME unit)
|
csr.rdata <= time_i(31 downto 0);
|
csr.rdata <= time_i(31 downto 0);
|
when csr_instret_c | csr_minstret_c => -- R/(W): [m]instret: Instructions-retired counter LOW
|
when csr_instret_c | csr_minstret_c => -- R/(W): [m]instret: Instructions-retired counter LOW
|
csr.rdata <= csr.minstret(31 downto 0);
|
csr.rdata <= csr.minstret(31 downto 0);
|
when csr_cycleh_c | csr_mcycleh_c => -- R/(W): [m]cycleh: Cycle counter HIGH
|
when csr_cycleh_c | csr_mcycleh_c => -- R/(W): [m]cycleh: Cycle counter HIGH
|
csr.rdata <= csr.mcycleh(31 downto 0);
|
csr.rdata <= csr.mcycleh(31 downto 0);
|
when csr_timeh_c => -- R/-: timeh: System time HIGH (from MTIME unit)
|
when csr_timeh_c => -- R/-: timeh: System time HIGH (from MTIME unit)
|
csr.rdata <= time_i(63 downto 32);
|
csr.rdata <= time_i(63 downto 32);
|
when csr_instreth_c | csr_minstreth_c => -- R/(W): [m]instreth: Instructions-retired counter HIGH
|
when csr_instreth_c | csr_minstreth_c => -- R/(W): [m]instreth: Instructions-retired counter HIGH
|
csr.rdata <= csr.minstreth(31 downto 0);
|
csr.rdata <= csr.minstreth(31 downto 0);
|
|
|
-- machine information registers --
|
-- machine information registers --
|
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
|
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
|
csr.rdata <= (others => '0');
|
csr.rdata <= (others => '0');
|
when csr_marchid_c => -- R/-: marchid - architecture ID
|
when csr_marchid_c => -- R/-: marchid - architecture ID
|
csr.rdata <= (others => '0');
|
csr.rdata <= (others => '0');
|
when csr_mimpid_c => -- R/-: mimpid - implementation ID / NEORV32 hardware version
|
when csr_mimpid_c => -- R/-: mimpid - implementation ID / NEORV32 hardware version
|
csr.rdata <= hw_version_c;
|
csr.rdata <= hw_version_c;
|
when csr_mhartid_c => -- R/-: mhartid - hardware thread ID
|
when csr_mhartid_c => -- R/-: mhartid - hardware thread ID
|
csr.rdata <= HW_THREAD_ID;
|
csr.rdata <= HW_THREAD_ID;
|
|
|
-- custom machine read-only CSRs --
|
-- custom machine read-only CSRs --
|
when csr_mzext_c => -- R/-: mzext
|
when csr_mzext_c => -- R/-: mzext
|
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr CPU extension
|
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr CPU extension
|
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei CPU extension
|
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei CPU extension
|
|
|
-- undefined/unavailable --
|
-- undefined/unavailable --
|
when others =>
|
when others =>
|
csr.rdata <= (others => '0'); -- not implemented
|
csr.rdata <= (others => '0'); -- not implemented
|
|
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process csr_read_access;
|
end process csr_read_access;
|
|
|
-- CSR read data output --
|
-- CSR read data output --
|
csr_rdata_o <= csr.rdata;
|
csr_rdata_o <= csr.rdata;
|
|
|
-- CPU's current privilege level --
|
-- CPU's current privilege level --
|
priv_mode_o <= csr.privilege;
|
priv_mode_o <= csr.privilege;
|
|
|
-- PMP output --
|
-- PMP output --
|
pmp_output: process(csr)
|
pmp_output: process(csr)
|
begin
|
begin
|
pmp_addr_o <= (others => (others => '0'));
|
pmp_addr_o <= (others => (others => '0'));
|
pmp_ctrl_o <= (others => (others => '0'));
|
pmp_ctrl_o <= (others => (others => '0'));
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
pmp_addr_o(i) <= csr.pmpaddr(i) & "00";
|
pmp_addr_o(i) <= csr.pmpaddr(i) & "00";
|
pmp_ctrl_o(i) <= csr.pmpcfg(i);
|
pmp_ctrl_o(i) <= csr.pmpcfg(i);
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
end process pmp_output;
|
end process pmp_output;
|
|
|
|
|
-- RISC-V Counter CSRs --------------------------------------------------------------------
|
-- RISC-V Counter CSRs --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_counters: process(rstn_i, clk_i)
|
csr_counters: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
csr.mcycle <= (others => '0');
|
csr.mcycle <= (others => '0');
|
csr.minstret <= (others => '0');
|
csr.minstret <= (others => '0');
|
csr.mcycleh <= (others => '0');
|
csr.mcycleh <= (others => '0');
|
csr.minstreth <= (others => '0');
|
csr.minstreth <= (others => '0');
|
mcycle_msb <= '0';
|
mcycle_msb <= '0';
|
minstret_msb <= '0';
|
minstret_msb <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
|
|
-- mcycle (cycle) --
|
-- mcycle (cycle) --
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access
|
csr.mcycle(31 downto 0) <= csr.wdata;
|
csr.mcycle(31 downto 0) <= csr.wdata;
|
csr.mcycle(32) <= '0';
|
csr.mcycle(32) <= '0';
|
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode)
|
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode)
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
end if;
|
end if;
|
|
|
-- mcycleh (cycleh) --
|
-- mcycleh (cycleh) --
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycleh_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycleh_c) then -- write access
|
csr.mcycleh <= csr.wdata(csr.mcycleh'left downto 0);
|
csr.mcycleh <= csr.wdata(csr.mcycleh'left downto 0);
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
end if;
|
end if;
|
|
|
-- minstret (instret) --
|
-- minstret (instret) --
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access
|
csr.minstret(31 downto 0) <= csr.wdata;
|
csr.minstret(31 downto 0) <= csr.wdata;
|
csr.minstret(32) <= '0';
|
csr.minstret(32) <= '0';
|
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
|
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
end if;
|
end if;
|
|
|
-- minstreth (instreth) --
|
-- minstreth (instreth) --
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstreth_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstreth_c) then -- write access
|
csr.minstreth <= csr.wdata(csr.minstreth'left downto 0);
|
csr.minstreth <= csr.wdata(csr.minstreth'left downto 0);
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process csr_counters;
|
end process csr_counters;
|
|
|
|
|
end neorv32_cpu_control_rtl;
|
end neorv32_cpu_control_rtl;
|
|
|