-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Control >> #
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-- # << NEORV32 - CPU Control >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an #
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-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an #
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-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction #
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-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction #
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-- # words) and an execute engine (responsible for actually executing the instructions), a trap #
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-- # words) and an execute engine (responsible for actually executing the instructions), a trap #
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-- # handling controller and the RISC-V status and control register set (CSRs). #
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-- # handling controller and the RISC-V status and control register set (CSRs). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_control is
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entity neorv32_cpu_control is
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_USE : boolean := false -- implement physical memory protection?
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- status input --
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-- status input --
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alu_wait_i : in std_ulogic; -- wait for ALU
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alu_wait_i : in std_ulogic; -- wait for ALU
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bus_i_wait_i : in std_ulogic; -- wait for bus
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bus_i_wait_i : in std_ulogic; -- wait for bus
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bus_d_wait_i : in std_ulogic; -- wait for bus
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bus_d_wait_i : in std_ulogic; -- wait for bus
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-- data input --
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-- data input --
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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-- data output --
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-- data output --
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- machine software interrupt
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msw_irq_i : in std_ulogic; -- machine software interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(3 downto 0);
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firq_i : in std_ulogic_vector(3 downto 0);
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- physical memory protection --
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-- physical memory protection --
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pmp_addr_o : out pmp_addr_if_t; -- addresses
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pmp_addr_o : out pmp_addr_if_t; -- addresses
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_store_i : in std_ulogic -- bus error on store data access
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be_store_i : in std_ulogic -- bus error on store data access
|
);
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);
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end neorv32_cpu_control;
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end neorv32_cpu_control;
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|
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architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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|
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-- instruction fetch enginge --
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-- instruction fetch enginge --
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type fetch_engine_state_t is (IFETCH_RESET, IFETCH_REQUEST, IFETCH_ISSUE);
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type fetch_engine_state_t is (IFETCH_RESET, IFETCH_REQUEST, IFETCH_ISSUE);
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type fetch_engine_t is record
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type fetch_engine_t is record
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state : fetch_engine_state_t;
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state : fetch_engine_state_t;
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state_nxt : fetch_engine_state_t;
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state_nxt : fetch_engine_state_t;
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state_prev : fetch_engine_state_t;
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pc : std_ulogic_vector(data_width_c-1 downto 0);
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pc : std_ulogic_vector(data_width_c-1 downto 0);
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pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
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pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
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reset : std_ulogic;
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reset : std_ulogic;
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bus_err_ack : std_ulogic;
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bus_err_ack : std_ulogic;
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end record;
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end record;
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signal fetch_engine : fetch_engine_t;
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signal fetch_engine : fetch_engine_t;
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|
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-- instrucion prefetch buffer (IPB, real FIFO) --
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-- instrucion prefetch buffer (IPB, real FIFO) --
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type ipb_data_fifo_t is array (0 to ipb_entries_c-1) of std_ulogic_vector(2+31 downto 0);
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type ipb_data_fifo_t is array (0 to ipb_entries_c-1) of std_ulogic_vector(2+31 downto 0);
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type ipb_t is record
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type ipb_t is record
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wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data
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wdata : std_ulogic_vector(2+31 downto 0); -- write status (bus_error, align_error) + 32-bit instruction data
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we : std_ulogic; -- trigger write
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we : std_ulogic; -- trigger write
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free : std_ulogic; -- free entry available?
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free : std_ulogic; -- free entry available?
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clear : std_ulogic; -- clear all entries
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clear : std_ulogic; -- clear all entries
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--
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--
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rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data
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rdata : std_ulogic_vector(2+31 downto 0); -- read data: status (bus_error, align_error) + 32-bit instruction data
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re : std_ulogic; -- read enable
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re : std_ulogic; -- read enable
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avail : std_ulogic; -- data available?
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avail : std_ulogic; -- data available?
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--
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--
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w_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- write pointer
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w_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- write pointer
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r_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- read pointer
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r_pnt : std_ulogic_vector(index_size_f(ipb_entries_c) downto 0); -- read pointer
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match : std_ulogic;
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match : std_ulogic;
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empty : std_ulogic;
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empty : std_ulogic;
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full : std_ulogic;
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full : std_ulogic;
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--
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--
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data : ipb_data_fifo_t; -- fifo memory
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data : ipb_data_fifo_t; -- fifo memory
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end record;
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end record;
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signal ipb : ipb_t;
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signal ipb : ipb_t;
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|
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-- pre-decoder --
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-- pre-decoder --
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signal ci_instr16 : std_ulogic_vector(15 downto 0);
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signal ci_instr16 : std_ulogic_vector(15 downto 0);
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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signal ci_illegal : std_ulogic;
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signal ci_illegal : std_ulogic;
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|
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-- instruction issue enginge --
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-- instruction issue enginge --
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type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);
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type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);
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type issue_engine_t is record
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type issue_engine_t is record
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state : issue_engine_state_t;
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state : issue_engine_state_t;
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state_nxt : issue_engine_state_t;
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state_nxt : issue_engine_state_t;
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align : std_ulogic;
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align : std_ulogic;
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align_nxt : std_ulogic;
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align_nxt : std_ulogic;
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buf : std_ulogic_vector(2+15 downto 0);
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buf : std_ulogic_vector(2+15 downto 0);
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buf_nxt : std_ulogic_vector(2+15 downto 0);
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buf_nxt : std_ulogic_vector(2+15 downto 0);
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end record;
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end record;
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signal issue_engine : issue_engine_t;
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signal issue_engine : issue_engine_t;
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|
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-- instruction issue interface --
|
-- instruction issue interface --
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type cmd_issue_t is record
|
type cmd_issue_t is record
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data : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction
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data : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction
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valid : std_ulogic; -- data word is valid when set
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valid : std_ulogic; -- data word is valid when set
|
end record;
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end record;
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signal cmd_issue : cmd_issue_t;
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signal cmd_issue : cmd_issue_t;
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|
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-- instruction execution engine --
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-- instruction execution engine --
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, FENCE_OP, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, FENCE_OP, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
|
type execute_engine_t is record
|
type execute_engine_t is record
|
state : execute_engine_state_t;
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state : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
|
|
state_prev : execute_engine_state_t;
|
--
|
--
|
i_reg : std_ulogic_vector(31 downto 0);
|
i_reg : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
|
i_reg_nxt : std_ulogic_vector(31 downto 0);
|
i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction
|
i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction
|
--
|
--
|
is_ci : std_ulogic; -- current instruction is de-compressed instruction
|
is_ci : std_ulogic; -- current instruction is de-compressed instruction
|
is_ci_nxt : std_ulogic;
|
is_ci_nxt : std_ulogic;
|
is_cp_op : std_ulogic; -- current instruction is a co-processor operation
|
is_cp_op : std_ulogic; -- current instruction is a co-processor operation
|
is_cp_op_nxt : std_ulogic;
|
is_cp_op_nxt : std_ulogic;
|
--
|
--
|
branch_taken : std_ulogic; -- branch condition fullfilled
|
branch_taken : std_ulogic; -- branch condition fullfilled
|
pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
|
pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
|
pc_mux_sel : std_ulogic_vector(1 downto 0); -- source select for PC update
|
pc_mux_sel : std_ulogic_vector(1 downto 0); -- source select for PC update
|
pc_we : std_ulogic; -- PC update enabled
|
pc_we : std_ulogic; -- PC update enabled
|
next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
|
next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
|
last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
|
last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
|
--
|
--
|
sleep : std_ulogic; -- CPU in sleep mode
|
sleep : std_ulogic; -- CPU in sleep mode
|
sleep_nxt : std_ulogic;
|
sleep_nxt : std_ulogic;
|
if_rst : std_ulogic; -- instruction fetch was reset
|
if_rst : std_ulogic; -- instruction fetch was reset
|
if_rst_nxt : std_ulogic;
|
if_rst_nxt : std_ulogic;
|
end record;
|
end record;
|
signal execute_engine : execute_engine_t;
|
signal execute_engine : execute_engine_t;
|
|
|
-- trap controller --
|
-- trap controller --
|
type trap_ctrl_t is record
|
type trap_ctrl_t is record
|
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
|
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
|
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
|
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
|
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
cause : std_ulogic_vector(5 downto 0); -- trap ID for mcause CSR
|
cause : std_ulogic_vector(5 downto 0); -- trap ID for mcause CSR
|
cause_nxt : std_ulogic_vector(5 downto 0);
|
cause_nxt : std_ulogic_vector(5 downto 0);
|
--
|
--
|
env_start : std_ulogic; -- start trap handler env
|
env_start : std_ulogic; -- start trap handler env
|
env_start_ack : std_ulogic; -- start of trap handler acknowledged
|
env_start_ack : std_ulogic; -- start of trap handler acknowledged
|
env_end : std_ulogic; -- end trap handler env
|
env_end : std_ulogic; -- end trap handler env
|
--
|
--
|
instr_be : std_ulogic; -- instruction fetch bus error
|
instr_be : std_ulogic; -- instruction fetch bus error
|
instr_ma : std_ulogic; -- instruction fetch misaligned address
|
instr_ma : std_ulogic; -- instruction fetch misaligned address
|
instr_il : std_ulogic; -- illegal instruction
|
instr_il : std_ulogic; -- illegal instruction
|
env_call : std_ulogic;
|
env_call : std_ulogic;
|
break_point : std_ulogic;
|
break_point : std_ulogic;
|
end record;
|
end record;
|
signal trap_ctrl : trap_ctrl_t;
|
signal trap_ctrl : trap_ctrl_t;
|
|
|
-- atomic operations controller --
|
-- atomic operations controller --
|
type atomic_ctrl_t is record
|
type atomic_ctrl_t is record
|
env_start : std_ulogic; -- begin atomic operations
|
env_start : std_ulogic; -- begin atomic operations
|
env_end : std_ulogic; -- end atomic operations
|
env_end : std_ulogic; -- end atomic operations
|
env_end_ff : std_ulogic; -- end atomic operations dealyed
|
env_end_ff : std_ulogic; -- end atomic operations dealyed
|
env_abort : std_ulogic; -- atomic operations abort (results in failure)
|
env_abort : std_ulogic; -- atomic operations abort (results in failure)
|
lock : std_ulogic; -- lock status
|
lock : std_ulogic; -- lock status
|
end record;
|
end record;
|
signal atomic_ctrl : atomic_ctrl_t;
|
signal atomic_ctrl : atomic_ctrl_t;
|
|
|
-- CPU main control bus --
|
-- CPU main control bus --
|
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
|
|
-- fast instruction fetch access --
|
-- fast instruction fetch access --
|
signal bus_fast_ir : std_ulogic;
|
signal bus_fast_ir : std_ulogic;
|
|
|
-- RISC-V control and status registers (CSRs) --
|
-- RISC-V control and status registers (CSRs) --
|
type pmp_ctrl_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
|
type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
|
type pmp_addr_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
|
type pmp_ctrl_rd_t is array (0 to 63) of std_ulogic_vector(7 downto 0);
|
|
type pmp_addr_rd_t is array (0 to 63) of std_ulogic_vector(data_width_c-1 downto 0);
|
|
type mhpmevent_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
|
|
type mhpmcnt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0);
|
|
type mhpmcnth_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0);
|
|
type mhpmevent_rd_t is array (0 to 29) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
|
|
type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(32 downto 0);
|
|
type mhpmcnth_rd_t is array (0 to 29) of std_ulogic_vector(31 downto 0);
|
type csr_t is record
|
type csr_t is record
|
addr : std_ulogic_vector(11 downto 0); -- csr address
|
addr : std_ulogic_vector(11 downto 0); -- csr address
|
we : std_ulogic; -- csr write enable
|
we : std_ulogic; -- csr write enable
|
we_nxt : std_ulogic;
|
we_nxt : std_ulogic;
|
re : std_ulogic; -- csr read enable
|
re : std_ulogic; -- csr read enable
|
re_nxt : std_ulogic;
|
re_nxt : std_ulogic;
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
--
|
--
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
|
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
--
|
--
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
|
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
--
|
--
|
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
|
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
|
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
|
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
|
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
|
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
|
|
mcounteren_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounteren.hpmx: allow mhpmcounterx[h] access from user-mode
|
--
|
--
|
mcountinhibit_cy : std_ulogic; -- mcounterinhibit.cy: enable auto-increment
|
mcountinhibit_cy : std_ulogic; -- mcounterinhibit.cy: enable auto-increment for [m]cycle[h]
|
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment
|
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]
|
|
mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]
|
--
|
--
|
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs
|
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs
|
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ
|
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ
|
--
|
--
|
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
|
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
|
priv_m_mode : std_ulogic; -- CPU in M-mode
|
priv_m_mode : std_ulogic; -- CPU in M-mode
|
priv_u_mode : std_ulogic; -- CPU in u-mode
|
priv_u_mode : std_ulogic; -- CPU in u-mode
|
--
|
--
|
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
|
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
|
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
|
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
|
|
--
|
|
mhpmevent : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)
|
|
mhpmevent_rd : mhpmevent_rd_t; -- mhpmevent*: actual read data
|
|
--
|
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
|
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
|
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
|
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
|
|
--
|
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
|
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
|
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
|
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
|
|
--
|
|
mhpmcounter : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit
|
|
mhpmcounterh : mhpmcnth_t; -- mhpmcounter*h (R/W)
|
|
mhpmcounter_rd : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data
|
|
mhpmcounterh_rd : mhpmcnth_rd_t; -- mhpmcounter*h (R/W): actual read data
|
|
--
|
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
|
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
|
|
pmpcfg_rd : pmp_ctrl_rd_t; -- physical memory protection - actual read data
|
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
|
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
|
|
pmpaddr_rd : pmp_addr_rd_t; -- physical memory protection - actual read data
|
end record;
|
end record;
|
signal csr : csr_t;
|
signal csr : csr_t;
|
|
|
|
-- counter low-to-high-word carry --
|
signal mcycle_msb : std_ulogic;
|
signal mcycle_msb : std_ulogic;
|
signal minstret_msb : std_ulogic;
|
signal minstret_msb : std_ulogic;
|
|
signal mhpmcounter_msb : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
|
|
|
|
-- (hpm) counter events --
|
|
signal cnt_event, cnt_event_nxt : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
|
|
signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
|
|
|
-- illegal instruction check --
|
-- illegal instruction check --
|
signal illegal_opcode_lsbs : std_ulogic; -- if opcode != rv32
|
signal illegal_opcode_lsbs : std_ulogic; -- if opcode != rv32
|
signal illegal_instruction : std_ulogic;
|
signal illegal_instruction : std_ulogic;
|
signal illegal_register : std_ulogic; -- only for E-extension
|
signal illegal_register : std_ulogic; -- only for E-extension
|
signal illegal_compressed : std_ulogic; -- only fir C-extension
|
signal illegal_compressed : std_ulogic; -- only fir C-extension
|
|
|
-- access (privilege) check --
|
-- access (privilege) check --
|
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
|
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
|
|
|
begin
|
begin
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Fetch (always fetches aligned 32-bit chunks of data)
|
-- Instruction Fetch (always fetches aligned 32-bit chunks of data)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
fetch_engine_fsm_sync: process(rstn_i, clk_i)
|
fetch_engine_fsm_sync: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
fetch_engine.state <= IFETCH_RESET;
|
fetch_engine.state <= IFETCH_RESET;
|
|
fetch_engine.state_prev <= IFETCH_RESET;
|
fetch_engine.pc <= (others => '0');
|
fetch_engine.pc <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (fetch_engine.reset = '1') then
|
if (fetch_engine.reset = '1') then
|
fetch_engine.state <= IFETCH_RESET;
|
fetch_engine.state <= IFETCH_RESET;
|
else
|
else
|
fetch_engine.state <= fetch_engine.state_nxt;
|
fetch_engine.state <= fetch_engine.state_nxt;
|
end if;
|
end if;
|
|
fetch_engine.state_prev <= fetch_engine.state;
|
fetch_engine.pc <= fetch_engine.pc_nxt;
|
fetch_engine.pc <= fetch_engine.pc_nxt;
|
end if;
|
end if;
|
end process fetch_engine_fsm_sync;
|
end process fetch_engine_fsm_sync;
|
|
|
-- PC output --
|
-- PC output --
|
fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned
|
fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned
|
|
|
|
|
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
|
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
bus_fast_ir <= '0';
|
bus_fast_ir <= '0';
|
fetch_engine.state_nxt <= fetch_engine.state;
|
fetch_engine.state_nxt <= fetch_engine.state;
|
fetch_engine.pc_nxt <= fetch_engine.pc;
|
fetch_engine.pc_nxt <= fetch_engine.pc;
|
fetch_engine.bus_err_ack <= '0';
|
fetch_engine.bus_err_ack <= '0';
|
|
|
-- instruction prefetch buffer interface --
|
-- instruction prefetch buffer interface --
|
ipb.we <= '0';
|
ipb.we <= '0';
|
ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
|
ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
|
ipb.clear <= '0';
|
ipb.clear <= '0';
|
|
|
-- state machine --
|
-- state machine --
|
case fetch_engine.state is
|
case fetch_engine.state is
|
|
|
when IFETCH_RESET => -- reset engine and prefetch buffer, get appilcation PC
|
when IFETCH_RESET => -- reset engine and prefetch buffer, get appilcation PC
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
|
fetch_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
fetch_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
ipb.clear <= '1'; -- clear prefetch buffer
|
ipb.clear <= '1'; -- clear prefetch buffer
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
|
|
when IFETCH_REQUEST => -- output current PC to bus system and request 32-bit (aligned!) instruction data
|
when IFETCH_REQUEST => -- output current PC to bus system and request 32-bit (aligned!) instruction data
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (ipb.free = '1') then -- free entry in buffer?
|
if (ipb.free = '1') then -- free entry in buffer?
|
bus_fast_ir <= '1'; -- fast instruction fetch request
|
bus_fast_ir <= '1'; -- fast instruction fetch request
|
fetch_engine.state_nxt <= IFETCH_ISSUE;
|
fetch_engine.state_nxt <= IFETCH_ISSUE;
|
end if;
|
end if;
|
|
|
when IFETCH_ISSUE => -- store instruction data to prefetch buffer
|
when IFETCH_ISSUE => -- store instruction data to prefetch buffer
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
|
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
|
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
|
ipb.we <= '1';
|
ipb.we <= '1';
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
end if;
|
end if;
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
fetch_engine.state_nxt <= IFETCH_RESET;
|
fetch_engine.state_nxt <= IFETCH_RESET;
|
|
|
end case;
|
end case;
|
end process fetch_engine_fsm_comb;
|
end process fetch_engine_fsm_comb;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Prefetch Buffer
|
-- Instruction Prefetch Buffer
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
|
-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
instr_prefetch_buffer: process(clk_i)
|
instr_prefetch_buffer: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- write port --
|
-- write port --
|
if (ipb.clear = '1') then
|
if (ipb.clear = '1') then
|
ipb.w_pnt <= (others => '0');
|
ipb.w_pnt <= (others => '0');
|
elsif (ipb.we = '1') then
|
elsif (ipb.we = '1') then
|
ipb.w_pnt <= std_ulogic_vector(unsigned(ipb.w_pnt) + 1);
|
ipb.w_pnt <= std_ulogic_vector(unsigned(ipb.w_pnt) + 1);
|
end if;
|
end if;
|
if (ipb.we = '1') then -- write data
|
if (ipb.we = '1') then -- write data
|
ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata;
|
ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata;
|
end if;
|
end if;
|
-- read port --
|
-- read port --
|
if (ipb.clear = '1') then
|
if (ipb.clear = '1') then
|
ipb.r_pnt <= (others => '0');
|
ipb.r_pnt <= (others => '0');
|
elsif (ipb.re = '1') then
|
elsif (ipb.re = '1') then
|
ipb.r_pnt <= std_ulogic_vector(unsigned(ipb.r_pnt) + 1);
|
ipb.r_pnt <= std_ulogic_vector(unsigned(ipb.r_pnt) + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process instr_prefetch_buffer;
|
end process instr_prefetch_buffer;
|
|
|
-- async read --
|
-- async read --
|
ipb.rdata <= ipb.data(to_integer(unsigned(ipb.r_pnt(ipb.r_pnt'left-1 downto 0))));
|
ipb.rdata <= ipb.data(to_integer(unsigned(ipb.r_pnt(ipb.r_pnt'left-1 downto 0))));
|
|
|
-- status --
|
-- status --
|
ipb.match <= '1' when (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
|
ipb.match <= '1' when (ipb.r_pnt(ipb.r_pnt'left-1 downto 0) = ipb.w_pnt(ipb.w_pnt'left-1 downto 0)) else '0';
|
ipb.full <= '1' when (ipb.r_pnt(ipb.r_pnt'left) /= ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
|
ipb.full <= '1' when (ipb.r_pnt(ipb.r_pnt'left) /= ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
|
ipb.empty <= '1' when (ipb.r_pnt(ipb.r_pnt'left) = ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
|
ipb.empty <= '1' when (ipb.r_pnt(ipb.r_pnt'left) = ipb.w_pnt(ipb.w_pnt'left)) and (ipb.match = '1') else '0';
|
ipb.free <= not ipb.full;
|
ipb.free <= not ipb.full;
|
ipb.avail <= not ipb.empty;
|
ipb.avail <= not ipb.empty;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction)
|
-- Instruction Issue (recoding of compressed instructions and 32-bit instruction word construction)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Issue Engine FSM Sync ------------------------------------------------------------------
|
-- Issue Engine FSM Sync ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
issue_engine.state <= ISSUE_ACTIVE;
|
issue_engine.state <= ISSUE_ACTIVE;
|
issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary
|
issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary
|
issue_engine.buf <= (others => '0');
|
issue_engine.buf <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (ipb.clear = '1') then
|
if (ipb.clear = '1') then
|
if (CPU_EXTENSION_RISCV_C = true) then
|
if (CPU_EXTENSION_RISCV_C = true) then
|
if (execute_engine.pc(1) = '1') then -- branch to unaligned address?
|
if (execute_engine.pc(1) = '1') then -- branch to unaligned address?
|
issue_engine.state <= ISSUE_REALIGN;
|
issue_engine.state <= ISSUE_REALIGN;
|
issue_engine.align <= '1'; -- aligned on 16-bit boundary
|
issue_engine.align <= '1'; -- aligned on 16-bit boundary
|
else
|
else
|
issue_engine.state <= issue_engine.state_nxt;
|
issue_engine.state <= issue_engine.state_nxt;
|
issue_engine.align <= '0'; -- aligned on 32-bit boundary
|
issue_engine.align <= '0'; -- aligned on 32-bit boundary
|
end if;
|
end if;
|
else
|
else
|
issue_engine.state <= issue_engine.state_nxt;
|
issue_engine.state <= issue_engine.state_nxt;
|
issue_engine.align <= '0'; -- always aligned on 32-bit boundaries
|
issue_engine.align <= '0'; -- always aligned on 32-bit boundaries
|
end if;
|
end if;
|
else
|
else
|
issue_engine.state <= issue_engine.state_nxt;
|
issue_engine.state <= issue_engine.state_nxt;
|
issue_engine.align <= issue_engine.align_nxt;
|
issue_engine.align <= issue_engine.align_nxt;
|
end if;
|
end if;
|
issue_engine.buf <= issue_engine.buf_nxt;
|
issue_engine.buf <= issue_engine.buf_nxt;
|
end if;
|
end if;
|
end process issue_engine_fsm_sync;
|
end process issue_engine_fsm_sync;
|
|
|
|
|
-- Issue Engine FSM Comb ------------------------------------------------------------------
|
-- Issue Engine FSM Comb ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
|
issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
issue_engine.state_nxt <= issue_engine.state;
|
issue_engine.state_nxt <= issue_engine.state;
|
issue_engine.align_nxt <= issue_engine.align;
|
issue_engine.align_nxt <= issue_engine.align;
|
issue_engine.buf_nxt <= issue_engine.buf;
|
issue_engine.buf_nxt <= issue_engine.buf;
|
|
|
-- instruction prefetch buffer interface defaults --
|
-- instruction prefetch buffer interface defaults --
|
ipb.re <= '0';
|
ipb.re <= '0';
|
|
|
-- instruction issue interface defaults --
|
-- instruction issue interface defaults --
|
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
|
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
|
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
|
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
|
cmd_issue.valid <= '0';
|
cmd_issue.valid <= '0';
|
|
|
-- state machine --
|
-- state machine --
|
case issue_engine.state is
|
case issue_engine.state is
|
|
|
when ISSUE_ACTIVE => -- issue instruction if available
|
when ISSUE_ACTIVE => -- issue instruction if available
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (ipb.avail = '1') then -- instructions available?
|
if (ipb.avail = '1') then -- instructions available?
|
|
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
|
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
|
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
|
cmd_issue.valid <= '1';
|
cmd_issue.valid <= '1';
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
|
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
|
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
|
ipb.re <= '1';
|
ipb.re <= '1';
|
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
|
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
|
else -- compressed
|
else -- compressed
|
ipb.re <= '1';
|
ipb.re <= '1';
|
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
issue_engine.align_nxt <= '1';
|
issue_engine.align_nxt <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
else -- begin check in HIGH instruction half-word
|
else -- begin check in HIGH instruction half-word
|
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
|
if (execute_engine.state = DISPATCH) then -- ready to issue new command?
|
cmd_issue.valid <= '1';
|
cmd_issue.valid <= '1';
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
|
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
|
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
|
ipb.re <= '1';
|
ipb.re <= '1';
|
cmd_issue.data <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
|
cmd_issue.data <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
|
else -- compressed
|
else -- compressed
|
-- do not read from ipb here!
|
-- do not read from ipb here!
|
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
|
issue_engine.align_nxt <= '0';
|
issue_engine.align_nxt <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address
|
when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
|
if (ipb.avail = '1') then -- instructions available?
|
if (ipb.avail = '1') then -- instructions available?
|
ipb.re <= '1';
|
ipb.re <= '1';
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
end if;
|
end if;
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
|
|
end case;
|
end case;
|
end process issue_engine_fsm_comb;
|
end process issue_engine_fsm_comb;
|
|
|
-- 16-bit instructions: half-word select --
|
-- 16-bit instructions: half-word select --
|
ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
|
ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
|
|
|
|
|
-- Compressed Instructions Recoding -------------------------------------------------------
|
-- Compressed Instructions Recoding -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_decompressor_inst_true:
|
neorv32_cpu_decompressor_inst_true:
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
port map (
|
port map (
|
-- instruction input --
|
-- instruction input --
|
ci_instr16_i => ci_instr16, -- compressed instruction input
|
ci_instr16_i => ci_instr16, -- compressed instruction input
|
-- instruction output --
|
-- instruction output --
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_decompressor_inst_false:
|
neorv32_cpu_decompressor_inst_false:
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
ci_instr32 <= (others => '0');
|
ci_instr32 <= (others => '0');
|
ci_illegal <= '0';
|
ci_illegal <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Execution
|
-- Instruction Execution
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Immediate Generator --------------------------------------------------------------------
|
-- Immediate Generator --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
imm_gen: process(execute_engine.i_reg, clk_i)
|
imm_gen: process(execute_engine.i_reg, clk_i)
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
begin
|
begin
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (execute_engine.state = BRANCH) then -- next_PC as immediate for jump-and-link operations (=return address)
|
if (execute_engine.state = BRANCH) then -- next_PC as immediate for jump-and-link operations (=return address)
|
imm_o <= execute_engine.next_pc;
|
imm_o <= execute_engine.next_pc;
|
else -- "normal" immediate from instruction
|
else -- "normal" immediate from instruction
|
case opcode_v is -- save some bits here, LSBs are always 11 for rv32
|
case opcode_v is -- save some bits here, LSBs are always 11 for rv32
|
when opcode_store_c => -- S-immediate
|
when opcode_store_c => -- S-immediate
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(00) <= execute_engine.i_reg(07);
|
imm_o(00) <= execute_engine.i_reg(07);
|
when opcode_branch_c => -- B-immediate
|
when opcode_branch_c => -- B-immediate
|
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(11) <= execute_engine.i_reg(07);
|
imm_o(11) <= execute_engine.i_reg(07);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(00) <= '0';
|
imm_o(00) <= '0';
|
when opcode_lui_c | opcode_auipc_c => -- U-immediate
|
when opcode_lui_c | opcode_auipc_c => -- U-immediate
|
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
|
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(11 downto 00) <= (others => '0');
|
imm_o(11 downto 00) <= (others => '0');
|
when opcode_jal_c => -- J-immediate
|
when opcode_jal_c => -- J-immediate
|
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
imm_o(11) <= execute_engine.i_reg(20);
|
imm_o(11) <= execute_engine.i_reg(20);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(00) <= '0';
|
imm_o(00) <= '0';
|
when opcode_atomic_c => -- atomic memory access
|
when opcode_atomic_c => -- atomic memory access
|
imm_o <= (others => '0'); -- effective address is addr = reg + 0 = reg
|
imm_o <= (others => '0'); -- effective address is addr = reg + 0 = reg
|
when others => -- I-immediate
|
when others => -- I-immediate
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(00) <= execute_engine.i_reg(20);
|
imm_o(00) <= execute_engine.i_reg(20);
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process imm_gen;
|
end process imm_gen;
|
|
|
|
|
-- Branch Condition Check -----------------------------------------------------------------
|
-- Branch Condition Check -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
branch_check: process(execute_engine.i_reg, cmp_i)
|
branch_check: process(execute_engine.i_reg, cmp_i)
|
begin
|
begin
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
when funct3_beq_c => -- branch if equal
|
when funct3_beq_c => -- branch if equal
|
execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c);
|
execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c);
|
when funct3_bne_c => -- branch if not equal
|
when funct3_bne_c => -- branch if not equal
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c);
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c);
|
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
execute_engine.branch_taken <= cmp_i(alu_cmp_less_c);
|
execute_engine.branch_taken <= cmp_i(alu_cmp_less_c);
|
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
|
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c);
|
execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c);
|
when others => -- undefined
|
when others => -- undefined
|
execute_engine.branch_taken <= '0';
|
execute_engine.branch_taken <= '0';
|
end case;
|
end case;
|
end process branch_check;
|
end process branch_check;
|
|
|
|
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- for registers that DO require a specific reset state --
|
-- for registers that DO require a specific reset state --
|
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.sleep <= '0';
|
execute_engine.sleep <= '0';
|
execute_engine.if_rst <= '1'; -- instruction fetch is reset after system reset
|
execute_engine.if_rst <= '1'; -- instruction fetch is reset after system reset
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- PC update --
|
-- PC update --
|
if (execute_engine.pc_we = '1') then
|
if (execute_engine.pc_we = '1') then
|
case execute_engine.pc_mux_sel is
|
case execute_engine.pc_mux_sel is
|
when "00" => execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment
|
when "00" => execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment
|
when "01" => execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch
|
when "01" => execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch
|
when "10" => execute_engine.pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
|
when "10" => execute_engine.pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
|
when others => execute_engine.pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit
|
when others => execute_engine.pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit
|
end case;
|
end case;
|
end if;
|
end if;
|
--
|
--
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
execute_engine.if_rst <= execute_engine.if_rst_nxt;
|
execute_engine.if_rst <= execute_engine.if_rst_nxt;
|
end if;
|
end if;
|
end process execute_engine_fsm_sync_rst;
|
end process execute_engine_fsm_sync_rst;
|
|
|
|
|
-- for registers that do NOT require a specific reset state --
|
-- for registers that do NOT require a specific reset state --
|
execute_engine_fsm_sync: process(clk_i)
|
execute_engine_fsm_sync: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
|
execute_engine.state_prev <= execute_engine.state;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
|
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
|
-- next PC (next linear instruction) --
|
-- next PC (next linear instruction) --
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.is_ci = '1') then -- compressed instruction?
|
if (execute_engine.is_ci = '1') then -- compressed instruction?
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 2);
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 2);
|
else
|
else
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
end if;
|
end if;
|
end if;
|
end if;
|
-- PC & IR of last "executed" instruction --
|
-- PC & IR of last "executed" instruction --
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
execute_engine.last_pc <= execute_engine.pc;
|
execute_engine.last_pc <= execute_engine.pc;
|
execute_engine.i_reg_last <= execute_engine.i_reg;
|
execute_engine.i_reg_last <= execute_engine.i_reg;
|
end if;
|
end if;
|
-- main control bus --
|
-- main control bus --
|
ctrl <= ctrl_nxt;
|
ctrl <= ctrl_nxt;
|
end if;
|
end if;
|
end process execute_engine_fsm_sync;
|
end process execute_engine_fsm_sync;
|
|
|
-- CSR access address --
|
-- CSR access address --
|
csr.addr <= execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c);
|
csr.addr <= execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c);
|
|
|
-- PC output --
|
-- PC output --
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- PC for ALU ops
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- PC for ALU ops
|
|
|
|
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, atomic_ctrl, bus_fast_ir, execute_engine, csr)
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, atomic_ctrl, bus_fast_ir, execute_engine, csr)
|
begin
|
begin
|
-- signals from execute engine --
|
-- signals from execute engine --
|
ctrl_o <= ctrl;
|
ctrl_o <= ctrl;
|
-- current privilege level --
|
-- current privilege level --
|
ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege;
|
ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege;
|
-- register addresses --
|
-- register addresses --
|
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
-- fast bus access requests --
|
-- fast bus access requests --
|
ctrl_o(ctrl_bus_if_c) <= bus_fast_ir;
|
ctrl_o(ctrl_bus_if_c) <= bus_fast_ir;
|
-- bus error control --
|
-- bus error control --
|
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
|
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
|
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
|
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
|
-- instruction's function blocks (for co-processors) --
|
-- instruction's function blocks (for co-processors) --
|
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
|
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
|
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
|
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
|
-- locked bus operation (for atomica memory operations) --
|
-- locked bus operation (for atomica memory operations) --
|
ctrl_o(ctrl_bus_lock_c) <= atomic_ctrl.lock; -- (bus) lock status
|
ctrl_o(ctrl_bus_lock_c) <= atomic_ctrl.lock; -- (bus) lock status
|
end process ctrl_output;
|
end process ctrl_output;
|
|
|
|
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
execute_engine_fsm_comb: process(execute_engine, fetch_engine, cmd_issue, trap_ctrl, csr, ctrl, csr_acc_valid,
|
execute_engine_fsm_comb: process(execute_engine, fetch_engine, cmd_issue, trap_ctrl, csr, ctrl, csr_acc_valid,
|
alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
|
alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
|
variable alu_immediate_v : std_ulogic;
|
variable alu_immediate_v : std_ulogic;
|
variable rs1_is_r0_v : std_ulogic;
|
variable rs1_is_r0_v : std_ulogic;
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
variable is_atomic_lr_v : std_ulogic;
|
variable is_atomic_lr_v : std_ulogic;
|
variable is_atomic_sc_v : std_ulogic;
|
variable is_atomic_sc_v : std_ulogic;
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op;
|
execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op;
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
execute_engine.sleep_nxt <= execute_engine.sleep;
|
execute_engine.sleep_nxt <= execute_engine.sleep;
|
execute_engine.if_rst_nxt <= execute_engine.if_rst;
|
execute_engine.if_rst_nxt <= execute_engine.if_rst;
|
--
|
--
|
execute_engine.pc_mux_sel <= (others => '0');
|
execute_engine.pc_mux_sel <= (others => '0');
|
execute_engine.pc_we <= '0';
|
execute_engine.pc_we <= '0';
|
|
|
-- instruction dispatch --
|
-- instruction dispatch --
|
fetch_engine.reset <= '0';
|
fetch_engine.reset <= '0';
|
|
|
-- trap environment control --
|
-- trap environment control --
|
trap_ctrl.env_start_ack <= '0';
|
trap_ctrl.env_start_ack <= '0';
|
trap_ctrl.env_end <= '0';
|
trap_ctrl.env_end <= '0';
|
|
|
-- exception trigger --
|
-- exception trigger --
|
trap_ctrl.instr_be <= '0';
|
trap_ctrl.instr_be <= '0';
|
trap_ctrl.instr_ma <= '0';
|
trap_ctrl.instr_ma <= '0';
|
trap_ctrl.env_call <= '0';
|
trap_ctrl.env_call <= '0';
|
trap_ctrl.break_point <= '0';
|
trap_ctrl.break_point <= '0';
|
illegal_compressed <= '0';
|
illegal_compressed <= '0';
|
|
|
-- CSR access --
|
-- CSR access --
|
csr.we_nxt <= '0';
|
csr.we_nxt <= '0';
|
csr.re_nxt <= '0';
|
csr.re_nxt <= '0';
|
|
|
-- atomic operations control --
|
-- atomic operations control --
|
atomic_ctrl.env_start <= '0';
|
atomic_ctrl.env_start <= '0';
|
atomic_ctrl.env_end <= '0';
|
atomic_ctrl.env_end <= '0';
|
atomic_ctrl.env_abort <= '0';
|
atomic_ctrl.env_abort <= '0';
|
|
|
-- CONTROL DEFAULTS --
|
-- CONTROL DEFAULTS --
|
ctrl_nxt <= (others => '0'); -- default: all off
|
ctrl_nxt <= (others => '0'); -- default: all off
|
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
|
else -- branches
|
else -- branches
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
|
end if;
|
end if;
|
-- memory access --
|
-- memory access --
|
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
|
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
|
-- alu.shifter --
|
-- alu.shifter --
|
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
|
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
|
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
|
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
|
-- ALU main control --
|
-- ALU main control --
|
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
|
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB
|
|
|
-- is immediate ALU operation? --
|
-- is immediate ALU operation? --
|
alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1);
|
alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1);
|
|
|
-- is rs1 == r0? --
|
-- is rs1 == r0? --
|
rs1_is_r0_v := not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
|
rs1_is_r0_v := not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c));
|
|
|
-- is atomic load-reservate/store-conditional? --
|
-- is atomic load-reservate/store-conditional? --
|
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
|
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
|
is_atomic_lr_v := not execute_engine.i_reg(instr_funct5_lsb_c);
|
is_atomic_lr_v := not execute_engine.i_reg(instr_funct5_lsb_c);
|
is_atomic_sc_v := execute_engine.i_reg(instr_funct5_lsb_c);
|
is_atomic_sc_v := execute_engine.i_reg(instr_funct5_lsb_c);
|
else
|
else
|
is_atomic_lr_v := '0';
|
is_atomic_lr_v := '0';
|
is_atomic_sc_v := '0';
|
is_atomic_sc_v := '0';
|
end if;
|
end if;
|
|
|
|
|
-- state machine --
|
-- state machine --
|
case execute_engine.state is
|
case execute_engine.state is
|
|
|
when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) ((and to init r0 with zero if it is a physical register))
|
when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) ((and to init r0 with zero if it is a physical register))
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- set reg_file's r0 to zero --
|
-- set reg_file's r0 to zero --
|
if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero?
|
if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero?
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read)
|
ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- force RF write access and force rd=r0
|
ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- force RF write access and force rd=r0
|
end if;
|
end if;
|
--
|
--
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
|
|
|
|
when DISPATCH => -- Get new command from instruction issue engine
|
when DISPATCH => -- Get new command from instruction issue engine
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC
|
-- IR update --
|
-- IR update --
|
execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate a de-compressed instruction beeing executed
|
execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate a de-compressed instruction beeing executed
|
execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0);
|
execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0);
|
--
|
--
|
if (cmd_issue.valid = '1') then -- instruction available?
|
if (cmd_issue.valid = '1') then -- instruction available?
|
-- IR update - exceptions --
|
-- IR update - exceptions --
|
trap_ctrl.instr_ma <= cmd_issue.data(33); -- misaligned instruction fetch address
|
trap_ctrl.instr_ma <= cmd_issue.data(33); -- misaligned instruction fetch address
|
trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instruction fetch
|
trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instruction fetch
|
illegal_compressed <= cmd_issue.data(35); -- invalid decompressed instruction
|
illegal_compressed <= cmd_issue.data(35); -- invalid decompressed instruction
|
-- PC update --
|
-- PC update --
|
execute_engine.if_rst_nxt <= '0';
|
execute_engine.if_rst_nxt <= '0';
|
execute_engine.pc_we <= not execute_engine.if_rst; -- update PC with linear next_pc if there was NO non-linear PC modification
|
execute_engine.pc_we <= not execute_engine.if_rst; -- update PC with linear next_pc if there was NO non-linear PC modification
|
-- any reason to go to trap state? --
|
-- any reason to go to trap state? --
|
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((cmd_issue.data(33) or cmd_issue.data(34)) = '1') then
|
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((cmd_issue.data(33) or cmd_issue.data(34)) = '1') then
|
execute_engine.state_nxt <= TRAP;
|
execute_engine.state_nxt <= TRAP;
|
else
|
else
|
execute_engine.state_nxt <= EXECUTE;
|
execute_engine.state_nxt <= EXECUTE;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
|
when TRAP => -- Start trap environment (also used as cpu sleep state)
|
when TRAP => -- Start trap environment (also used as cpu sleep state)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.pc_mux_sel <= "10"; -- csr.mtvec (trap)
|
execute_engine.pc_mux_sel <= "10"; -- csr.mtvec (trap)
|
fetch_engine.reset <= '1';
|
|
execute_engine.if_rst_nxt <= '1'; -- this will be a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this will be a non-linear PC modification
|
if (trap_ctrl.env_start = '1') then -- trap triggered?
|
if (trap_ctrl.env_start = '1') then -- trap triggered?
|
trap_ctrl.env_start_ack <= '1';
|
trap_ctrl.env_start_ack <= '1';
|
|
fetch_engine.reset <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.sleep_nxt <= '0'; -- waky waky
|
execute_engine.sleep_nxt <= '0'; -- waky waky
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
end if;
|
end if;
|
|
|
|
|
when EXECUTE => -- Decode and execute instruction (control has to be here for excatly 1 cyle in any case!)
|
when EXECUTE => -- Decode and execute instruction (control has to be here for excatly 1 cyle in any case!)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
|
case opcode_v is
|
case opcode_v is
|
|
|
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
|
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
|
|
-- ALU arithmetic operation type and ADD/SUB --
|
-- ALU arithmetic operation type and ADD/SUB --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_slt_c;
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_slt_c;
|
else
|
else
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c;
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c;
|
end if;
|
end if;
|
|
|
-- ADD/SUB --
|
-- ADD/SUB --
|
if ((alu_immediate_v = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) or -- not an immediate op and funct7.6 set => SUB
|
if ((alu_immediate_v = '0') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) or -- not an immediate op and funct7.6 set => SUB
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or -- SLT operation
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or -- SLT operation
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then -- SLTU operation
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then -- SLTU operation
|
ctrl_nxt(ctrl_alu_addsub_c) <= '1'; -- SUB/SLT
|
ctrl_nxt(ctrl_alu_addsub_c) <= '1'; -- SUB/SLT
|
else
|
else
|
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
|
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
|
end if;
|
end if;
|
|
|
-- ALU logic operation --
|
-- ALU logic operation --
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding)
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding)
|
when funct3_xor_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_xor_c; -- XOR(I)
|
when funct3_xor_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_xor_c; -- XOR(I)
|
when funct3_or_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_or_c; -- OR(I)
|
when funct3_or_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_or_c; -- OR(I)
|
when others => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I)
|
when others => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I)
|
end case;
|
end case;
|
|
|
-- co-processor (cp) access? --
|
-- co-processor (cp) access? --
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- just in case a mul/div operation
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- just in case a mul/div operation
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV CP op?
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV CP op?
|
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
|
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
-- ALU operation - function select --
|
-- ALU operation - function select --
|
else
|
else
|
execute_engine.is_cp_op_nxt <= '0'; -- no CP operation
|
execute_engine.is_cp_op_nxt <= '0'; -- no CP operation
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.func operation (re-coding)
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.func operation (re-coding)
|
when funct3_xor_c | funct3_or_c | funct3_and_c => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c;
|
when funct3_xor_c | funct3_or_c | funct3_and_c => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c;
|
when funct3_sll_c | funct3_sr_c => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c;
|
when funct3_sll_c | funct3_sr_c => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c;
|
when others => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c;
|
when others => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- multi cycle alu operation? --
|
-- multi cycle alu operation? --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
|
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV CP op?
|
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV CP op?
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
else -- single cycle ALU operation
|
else -- single cycle ALU operation
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only)
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only)
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
|
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
|
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
|
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
|
else -- AUIPC
|
else -- AUIPC
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- actual ALU operation = ADD
|
end if;
|
end if;
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
|
|
when opcode_load_c | opcode_store_c | opcode_atomic_c => -- load/store / atomic memory access
|
when opcode_load_c | opcode_store_c | opcode_atomic_c => -- load/store / atomic memory access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_bus_mo_we_c) <= '1'; -- write to MAR and MDO (MDO only relevant for store)
|
ctrl_nxt(ctrl_bus_mo_we_c) <= '1'; -- write to MAR and MDO (MDO only relevant for store)
|
--
|
--
|
if (CPU_EXTENSION_RISCV_A = false) or (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') then -- atomic (A) extension disabled or normal load/store
|
if (CPU_EXTENSION_RISCV_A = false) or (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') then -- atomic (A) extension disabled or normal load/store
|
execute_engine.state_nxt <= LOADSTORE_0;
|
execute_engine.state_nxt <= LOADSTORE_0;
|
else -- atomic operation
|
else -- atomic operation
|
atomic_ctrl.env_start <= not execute_engine.i_reg(instr_funct5_lsb_c); -- LR: start LOCKED memory access environment
|
atomic_ctrl.env_start <= not execute_engine.i_reg(instr_funct5_lsb_c); -- LR: start LOCKED memory access environment
|
if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c) or -- store-conditional
|
if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c) or -- store-conditional
|
(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) then -- load-reservate
|
(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) then -- load-reservate
|
execute_engine.state_nxt <= LOADSTORE_0;
|
execute_engine.state_nxt <= LOADSTORE_0;
|
else -- unimplemented (atomic) instruction
|
else -- unimplemented (atomic) instruction
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register)
|
when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- compute target address --
|
-- compute target address --
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- actual ALU operation = ADD
|
if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR
|
if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base)
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base)
|
else -- JAL / branch
|
else -- JAL / branch
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
|
end if;
|
end if;
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
|
--
|
--
|
execute_engine.state_nxt <= BRANCH;
|
execute_engine.state_nxt <= BRANCH;
|
|
|
when opcode_fence_c => -- fence operations
|
when opcode_fence_c => -- fence operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= FENCE_OP;
|
execute_engine.state_nxt <= FENCE_OP;
|
|
|
when opcode_syscsr_c => -- system/csr access
|
when opcode_syscsr_c => -- system/csr access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
csr.re_nxt <= csr_acc_valid; -- always read CSR if valid access, only relevant for CSR-instructions
|
csr.re_nxt <= csr_acc_valid; -- always read CSR if valid access, only relevant for CSR-instructions
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
|
execute_engine.state_nxt <= SYS_ENV;
|
execute_engine.state_nxt <= SYS_ENV;
|
else -- CSR access
|
else -- CSR access
|
execute_engine.state_nxt <= CSR_ACCESS;
|
execute_engine.state_nxt <= CSR_ACCESS;
|
end if;
|
end if;
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
|
end case;
|
end case;
|
|
|
|
|
when SYS_ENV => -- system environment operation - execution
|
when SYS_ENV => -- system environment operation - execution
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.pc_mux_sel <= "11"; -- csr.mepc (only relevant for MRET)
|
execute_engine.pc_mux_sel <= "11"; -- csr.mepc (only relevant for MRET)
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
when funct12_ecall_c => -- ECALL
|
when funct12_ecall_c => -- ECALL
|
trap_ctrl.env_call <= '1';
|
trap_ctrl.env_call <= '1';
|
when funct12_ebreak_c => -- EBREAK
|
when funct12_ebreak_c => -- EBREAK
|
trap_ctrl.break_point <= '1';
|
trap_ctrl.break_point <= '1';
|
when funct12_mret_c => -- MRET
|
when funct12_mret_c => -- MRET
|
trap_ctrl.env_end <= '1';
|
trap_ctrl.env_end <= '1';
|
execute_engine.pc_we <= '1'; -- update PC from MEPC
|
execute_engine.pc_we <= '1'; -- update PC from MEPC
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
when funct12_wfi_c => -- WFI
|
when funct12_wfi_c => -- WFI
|
execute_engine.sleep_nxt <= '1'; -- good night
|
execute_engine.sleep_nxt <= '1'; -- good night
|
when others => -- undefined
|
when others => -- undefined
|
NULL;
|
NULL;
|
end case;
|
end case;
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
|
|
|
when CSR_ACCESS => -- read & write status and control register (CSR)
|
when CSR_ACCESS => -- read & write status and control register (CSR)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- CSR write access --
|
-- CSR write access --
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I)
|
when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I)
|
csr.we_nxt <= csr_acc_valid; -- always write CSR if valid access
|
csr.we_nxt <= csr_acc_valid; -- always write CSR if valid access
|
when funct3_csrrs_c | funct3_csrrsi_c | funct3_csrrc_c | funct3_csrrci_c => -- CSRRS(I) / CSRRC(I)
|
when funct3_csrrs_c | funct3_csrrsi_c | funct3_csrrc_c | funct3_csrrci_c => -- CSRRS(I) / CSRRC(I)
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1/imm is not zero and if valid access
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1/imm is not zero and if valid access
|
when others => -- invalid
|
when others => -- invalid
|
csr.we_nxt <= '0';
|
csr.we_nxt <= '0';
|
end case;
|
end case;
|
-- register file write back --
|
-- register file write back --
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
|
|
|
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (shifter or CP) to finish
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (shifter or CP) to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
|
-- cp access or alu shift? --
|
-- cp access or alu shift? --
|
if (execute_engine.is_cp_op = '1') then
|
if (execute_engine.is_cp_op = '1') then
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
else
|
else
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c;
|
end if;
|
end if;
|
-- wait for result --
|
-- wait for result --
|
if (alu_wait_i = '0') then
|
if (alu_wait_i = '0') then
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
when BRANCH => -- update PC for taken branches and jumps
|
when BRANCH => -- update PC for taken branches and jumps
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- get and store return address (only relevant for jump-and-link operations) --
|
-- get and store return address (only relevant for jump-and-link operations) --
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (next_pc from immediate generator = return address)
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (next_pc from immediate generator = return address)
|
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
|
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
|
-- destination address --
|
-- destination address --
|
execute_engine.pc_mux_sel <= "01"; -- alu.add = branch/jump destination
|
execute_engine.pc_mux_sel <= "01"; -- alu.add = branch/jump destination
|
if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
|
if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
|
execute_engine.pc_we <= '1'; -- update PC
|
execute_engine.pc_we <= '1'; -- update PC
|
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
else
|
else
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
when FENCE_OP => -- fence operations - execution
|
when FENCE_OP => -- fence operations - execution
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC = "refetch" next instruction (only relevant for fence.i)
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC = "refetch" next instruction (only relevant for fence.i)
|
-- FENCE.I --
|
-- FENCE.I --
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) and (CPU_EXTENSION_RISCV_Zifencei = true) then
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) and (CPU_EXTENSION_RISCV_Zifencei = true) then
|
execute_engine.pc_we <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
end if;
|
end if;
|
-- FENCE --
|
-- FENCE --
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
end if;
|
end if;
|
|
|
|
|
when LOADSTORE_0 => -- trigger memory request
|
when LOADSTORE_0 => -- trigger memory request
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') then -- normal load or atomic load-reservate
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') then -- normal load or atomic load-reservate
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
else -- store
|
else -- store
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
|
end if;
|
end if;
|
execute_engine.state_nxt <= LOADSTORE_1;
|
execute_engine.state_nxt <= LOADSTORE_1;
|
|
|
|
|
when LOADSTORE_1 => -- memory latency
|
when LOADSTORE_1 => -- memory latency
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
|
execute_engine.state_nxt <= LOADSTORE_2;
|
execute_engine.state_nxt <= LOADSTORE_2;
|
|
|
|
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- ALU control (only relevant for atomic memory operations) --
|
-- ALU control (only relevant for atomic memory operations) --
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_atomic_c; -- atomic.SC: result comes from "atomic co-processor"
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_atomic_c; -- atomic.SC: result comes from "atomic co-processor"
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
end if;
|
end if;
|
-- register file write-back --
|
-- register file write-back --
|
ctrl_nxt(ctrl_rf_in_mux_lsb_c) <= '0'; -- RF input = ALU.res or MEM
|
ctrl_nxt(ctrl_rf_in_mux_lsb_c) <= '0'; -- RF input = ALU.res or MEM
|
if (is_atomic_sc_v = '1') then
|
if (is_atomic_sc_v = '1') then
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU.res (only relevant for atomic.SC)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU.res (only relevant for atomic.SC)
|
else
|
else
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
|
end if;
|
end if;
|
--
|
--
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load operations)
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load operations)
|
-- wait for memory response --
|
-- wait for memory response --
|
if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception
|
if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception
|
atomic_ctrl.env_abort <= '1'; -- LOCKED (atomic) memory access environment failed (forces SC result to be non-zero => failure)
|
atomic_ctrl.env_abort <= '1'; -- LOCKED (atomic) memory access environment failed (forces SC result to be non-zero => failure)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= is_atomic_sc_v; -- SC failes: allow write back of non-zero result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= is_atomic_sc_v; -- SC failes: allow write back of non-zero result
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') or (is_atomic_sc_v = '1') then -- load / load-reservate / store conditional
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') or (is_atomic_sc_v = '1') then -- load / load-reservate / store conditional
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
end if;
|
end if;
|
atomic_ctrl.env_end <= '1'; -- normal end of LOCKED (atomic) memory access environment
|
atomic_ctrl.env_end <= '1'; -- normal end of LOCKED (atomic) memory access environment
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
|
end case;
|
end case;
|
end process execute_engine_fsm_comb;
|
end process execute_engine_fsm_comb;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Invalid Instruction / CSR access check
|
-- Invalid Instruction / CSR access check
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Illegal CSR Access Check ---------------------------------------------------------------
|
-- Illegal CSR Access Check ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
invalid_csr_access_check: process(execute_engine.i_reg, csr)
|
invalid_csr_access_check: process(execute_engine.i_reg, csr)
|
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
|
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
|
|
variable csr_mcounteren_hpm_v : std_ulogic_vector(28 downto 0); -- max 29 HPM counters
|
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
|
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
|
begin
|
begin
|
-- is this CSR instruction really going to write/read to/from a CSR? --
|
-- is this CSR instruction really going to write/read to/from a CSR? --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
|
csr_wacc_v := '1'; -- always write CSR
|
csr_wacc_v := '1'; -- always write CSR
|
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
|
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
|
else
|
else
|
csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
|
csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
|
-- csr_racc_v := '1'; -- always read CSR
|
-- csr_racc_v := '1'; -- always read CSR
|
end if;
|
end if;
|
|
|
|
-- low privilege level access to hpm counters? --
|
|
csr_mcounteren_hpm_v := (others => '0');
|
|
csr_mcounteren_hpm_v(HPM_NUM_CNTS-1 downto 0) := csr.mcounteren_hpm(HPM_NUM_CNTS-1 downto 0);
|
|
|
-- check CSR access --
|
-- check CSR access --
|
case csr.addr is
|
case csr.addr is
|
-- standard read/write CSRs --
|
-- standard read/write CSRs --
|
when csr_mstatus_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mstatus_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mstatush_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mstatush_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_misa_c => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
|
when csr_misa_c => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
|
when csr_mie_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mie_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mtvec_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mtvec_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mscratch_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mscratch_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mepc_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mepc_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcause_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcause_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcounteren_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcounteren_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mtval_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mtval_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mip_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mip_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
--
|
--
|
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
|
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only
|
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
|
--
|
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only
|
--
|
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 2)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c |
|
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 3)) and csr.priv_m_mode; -- M-mode only
|
csr_pmpaddr8_c | csr_pmpaddr9_c | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
|
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 4)) and csr.priv_m_mode; -- M-mode only
|
csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c |
|
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only
|
csr_pmpaddr24_c | csr_pmpaddr25_c | csr_pmpaddr26_c | csr_pmpaddr27_c | csr_pmpaddr28_c | csr_pmpaddr29_c | csr_pmpaddr30_c | csr_pmpaddr31_c |
|
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 6)) and csr.priv_m_mode; -- M-mode only
|
csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c |
|
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 7)) and csr.priv_m_mode; -- M-mode only
|
csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
|
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 8)) and csr.priv_m_mode; -- M-mode only
|
csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
|
|
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
|
|
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
--
|
--
|
when csr_mcountinhibit_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcountinhibit_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
--
|
--
|
|
when csr_mhpmevent3_c | csr_mhpmevent4_c | csr_mhpmevent5_c | csr_mhpmevent6_c | csr_mhpmevent7_c | csr_mhpmevent8_c |
|
|
csr_mhpmevent9_c | csr_mhpmevent10_c | csr_mhpmevent11_c | csr_mhpmevent12_c | csr_mhpmevent13_c | csr_mhpmevent14_c |
|
|
csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
|
|
csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
|
|
csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c =>
|
|
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
|
--
|
when csr_mcycle_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcycle_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_minstret_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_minstret_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
--
|
--
|
|
when csr_mhpmcounter3_c | csr_mhpmcounter4_c | csr_mhpmcounter5_c | csr_mhpmcounter6_c | csr_mhpmcounter7_c | csr_mhpmcounter8_c |
|
|
csr_mhpmcounter9_c | csr_mhpmcounter10_c | csr_mhpmcounter11_c | csr_mhpmcounter12_c | csr_mhpmcounter13_c | csr_mhpmcounter14_c |
|
|
csr_mhpmcounter15_c | csr_mhpmcounter16_c | csr_mhpmcounter17_c | csr_mhpmcounter18_c | csr_mhpmcounter19_c | csr_mhpmcounter20_c |
|
|
csr_mhpmcounter21_c | csr_mhpmcounter22_c | csr_mhpmcounter23_c | csr_mhpmcounter24_c | csr_mhpmcounter25_c | csr_mhpmcounter26_c |
|
|
csr_mhpmcounter27_c | csr_mhpmcounter28_c | csr_mhpmcounter29_c | csr_mhpmcounter30_c | csr_mhpmcounter31_c =>
|
|
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
|
--
|
when csr_mcycleh_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcycleh_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_minstreth_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_minstreth_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
|
--
|
|
when csr_mhpmcounter3h_c | csr_mhpmcounter4h_c | csr_mhpmcounter5h_c | csr_mhpmcounter6h_c | csr_mhpmcounter7h_c | csr_mhpmcounter8h_c |
|
|
csr_mhpmcounter9h_c | csr_mhpmcounter10h_c | csr_mhpmcounter11h_c | csr_mhpmcounter12h_c | csr_mhpmcounter13h_c | csr_mhpmcounter14h_c |
|
|
csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c |
|
|
csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c |
|
|
csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c =>
|
|
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
|
|
-- standard read-only CSRs --
|
-- standard read-only CSRs --
|
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
|
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
|
when csr_time_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
|
when csr_time_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
|
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
|
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
|
--
|
--
|
|
when csr_hpmcounter3_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(0)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter4_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(1)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter5_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(2)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter6_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(3)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter7_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(4)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter8_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(5)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter9_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(6)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter10_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(7)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter11_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(8)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter12_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(9)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter13_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter14_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter15_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter16_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(13)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter17_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(14)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter18_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(15)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter19_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(16)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter20_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(17)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter21_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(18)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter22_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(19)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter23_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(20)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter24_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(21)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter25_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(22)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter26_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(23)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter27_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(24)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter28_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(25)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter29_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(26)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter30_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(27)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter31_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(28)); -- M-mode, U-mode if authorized, read-only
|
|
--
|
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
|
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
|
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
|
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
|
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
|
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
|
--
|
--
|
|
when csr_hpmcounter3h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(0)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter4h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(1)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter5h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(2)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter6h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(3)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter7h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(4)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter8h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(5)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter9h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(6)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter10h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(7)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter11h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(8)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter12h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(9)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter13h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter14h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter15h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter16h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(13)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter17h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(14)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter18h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(15)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter19h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(16)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter20h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(17)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter21h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(18)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter22h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(19)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter23h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(20)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter24h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(21)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter25h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(22)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter26h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(23)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter27h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(24)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter28h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(25)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter29h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(26)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter30h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(27)); -- M-mode, U-mode if authorized, read-only
|
|
when csr_hpmcounter31h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(28)); -- M-mode, U-mode if authorized, read-only
|
|
--
|
when csr_mvendorid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_mvendorid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_marchid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_marchid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_mimpid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_mimpid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_mhartid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_mhartid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
-- custom read-only CSRs --
|
-- custom read-only CSRs --
|
when csr_mzext_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
when csr_mzext_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
|
--
|
--
|
when others => csr_acc_valid <= '0'; -- invalid access
|
when others => csr_acc_valid <= '0'; -- invalid access
|
end case;
|
end case;
|
end process invalid_csr_access_check;
|
end process invalid_csr_access_check;
|
|
|
|
|
-- Illegal Instruction Check --------------------------------------------------------------
|
-- Illegal Instruction Check --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
illegal_instruction_check: process(execute_engine, csr_acc_valid)
|
illegal_instruction_check: process(execute_engine, csr_acc_valid)
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
begin
|
begin
|
-- illegal instructions are checked in the EXECUTE stage
|
-- illegal instructions are checked in the EXECUTE stage
|
-- the execute engine should not commit any illegal instruction
|
-- the execute engine should not commit any illegal instruction
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
-- defaults --
|
-- defaults --
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
illegal_register <= '0';
|
illegal_register <= '0';
|
|
|
-- check opcode for rv32 --
|
-- check opcode for rv32 --
|
if (execute_engine.i_reg(instr_opcode_lsb_c+1 downto instr_opcode_lsb_c) = "11") then
|
if (execute_engine.i_reg(instr_opcode_lsb_c+1 downto instr_opcode_lsb_c) = "11") then
|
illegal_opcode_lsbs <= '0';
|
illegal_opcode_lsbs <= '0';
|
else
|
else
|
illegal_opcode_lsbs <= '1';
|
illegal_opcode_lsbs <= '1';
|
end if;
|
end if;
|
|
|
-- check instructions --
|
-- check instructions --
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
|
case opcode_v is
|
case opcode_v is
|
|
|
-- OPCODE check sufficient: LUI, UIPC, JAL --
|
-- OPCODE check sufficient: LUI, UIPC, JAL --
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and (execute_engine.i_reg(instr_rd_msb_c) = '1') then
|
if (CPU_EXTENSION_RISCV_E = true) and (execute_engine.i_reg(instr_rd_msb_c) = '1') then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_alui_c => -- check ALUI funct7
|
when opcode_alui_c => -- check ALUI funct7
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
else
|
else
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_load_c => -- check LOAD funct3
|
when opcode_load_c => -- check LOAD funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lbu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_store_c => -- check STORE funct3
|
when opcode_store_c => -- check STORE funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_branch_c => -- check BRANCH funct3
|
when opcode_branch_c => -- check BRANCH funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bge_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bltu_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_jalr_c => -- check JALR funct3
|
when opcode_jalr_c => -- check JALR funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_alu_c => -- check ALU funct3 & funct7
|
when opcode_alu_c => -- check ALU funct3 & funct7
|
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
|
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
|
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
|
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and -- ADD/SUB or SRA/SRL check
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000") and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
else
|
else
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) and
|
if (CPU_EXTENSION_RISCV_E = true) and
|
((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
illegal_register <= '1';
|
illegal_register <= '1';
|
end if;
|
end if;
|
|
|
when opcode_fence_c => -- fence instructions --
|
when opcode_fence_c => -- fence instructions --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
|
when opcode_syscsr_c => -- check system instructions --
|
when opcode_syscsr_c => -- check system instructions --
|
-- CSR access --
|
-- CSR access --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c) then
|
-- valid CSR access? --
|
-- valid CSR access? --
|
if (csr_acc_valid = '1') then
|
if (csr_acc_valid = '1') then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) then
|
if (CPU_EXTENSION_RISCV_E = true) then
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
else -- reg-imm CSR
|
else -- reg-imm CSR
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- ecall, ebreak, mret, wfi --
|
-- ecall, ebreak, mret, wfi --
|
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
|
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
|
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
|
when opcode_atomic_c => -- atomic instructions --
|
when opcode_atomic_c => -- atomic instructions --
|
if (CPU_EXTENSION_RISCV_A = true) and -- atomic memory operations (A extension) enabled
|
if (CPU_EXTENSION_RISCV_A = true) and -- atomic memory operations (A extension) enabled
|
((execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) or -- LR
|
((execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) or -- LR
|
(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c)) then -- SC
|
(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c)) then -- SC
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
|
when others => -- undefined instruction -> illegal!
|
when others => -- undefined instruction -> illegal!
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
|
|
end case;
|
end case;
|
else
|
else
|
illegal_opcode_lsbs <= '0';
|
illegal_opcode_lsbs <= '0';
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
illegal_register <= '0';
|
illegal_register <= '0';
|
end if;
|
end if;
|
end process illegal_instruction_check;
|
end process illegal_instruction_check;
|
|
|
-- any illegal condition? --
|
-- any illegal condition? --
|
trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
|
trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Exception and Interrupt (= Trap) Control
|
-- Exception and Interrupt (= Trap) Control
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Trap Controller ------------------------------------------------------------------------
|
-- Trap Controller ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_controller: process(rstn_i, clk_i)
|
trap_controller: process(rstn_i, clk_i)
|
variable mode_m_v, mode_u_v : std_ulogic;
|
variable mode_m_v, mode_u_v : std_ulogic;
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.cause <= trap_reset_c;
|
trap_ctrl.cause <= trap_reset_c;
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
-- exception buffer: misaligned load/store/instruction address
|
-- exception buffer: misaligned load/store/instruction address
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
|
-- exception buffer: load/store/instruction bus access error
|
-- exception buffer: load/store/instruction bus access error
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
-- exception buffer: illegal instruction / env call / break point
|
-- exception buffer: illegal instruction / env call / break point
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
-- interrupt buffer: machine software/external/timer interrupt
|
-- interrupt buffer: machine software/external/timer interrupt
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c)));
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
|
-- interrupt buffer: custom fast interrupts
|
-- interrupt buffer: custom fast interrupts
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c) or csr.mip_clear(interrupt_firq_0_c)));
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c) or csr.mip_clear(interrupt_firq_0_c)));
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not (trap_ctrl.irq_ack(interrupt_firq_1_c) or csr.mip_clear(interrupt_firq_1_c)));
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not (trap_ctrl.irq_ack(interrupt_firq_1_c) or csr.mip_clear(interrupt_firq_1_c)));
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not (trap_ctrl.irq_ack(interrupt_firq_2_c) or csr.mip_clear(interrupt_firq_2_c)));
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not (trap_ctrl.irq_ack(interrupt_firq_2_c) or csr.mip_clear(interrupt_firq_2_c)));
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not (trap_ctrl.irq_ack(interrupt_firq_3_c) or csr.mip_clear(interrupt_firq_3_c)));
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not (trap_ctrl.irq_ack(interrupt_firq_3_c) or csr.mip_clear(interrupt_firq_3_c)));
|
-- trap control --
|
-- trap control --
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- clear interrupt with interrupt ACK mask
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
end if;
|
end if;
|
else -- trap waiting to get started
|
else -- trap waiting to get started
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process trap_controller;
|
end process trap_controller;
|
|
|
-- any exception/interrupt? --
|
-- any exception/interrupt? --
|
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
|
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
|
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
|
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
|
|
|
-- current pending interrupts (for CSR.MIP register) --
|
-- current pending interrupts (for CSR.MIP register) --
|
csr.mip_status <= trap_ctrl.irq_buf;
|
csr.mip_status <= trap_ctrl.irq_buf;
|
|
|
|
|
-- Trap Priority Detector -----------------------------------------------------------------
|
-- Trap Priority Encoder ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_priority: process(trap_ctrl)
|
trap_priority: process(trap_ctrl)
|
begin
|
begin
|
-- defaults --
|
-- defaults --
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
|
|
-- the following traps are caused by *asynchronous* exceptions (= interrupts)
|
-- the following traps are caused by *asynchronous* exceptions (= interrupts)
|
-- here we do need a specific acknowledge mask since several sources can trigger at once
|
-- here we do need a specific acknowledge mask since several sources can trigger at once
|
|
|
-- interrupt: 1.11 machine external interrupt --
|
-- interrupt: 1.11 machine external interrupt --
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
|
|
-- interrupt: 1.3 machine SW interrupt --
|
-- interrupt: 1.3 machine SW interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
|
|
-- interrupt: 1.7 machine timer interrupt --
|
-- interrupt: 1.7 machine timer interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
|
|
|
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
|
|
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_1_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq1_c;
|
trap_ctrl.cause_nxt <= trap_firq1_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_1_c) <= '1';
|
|
|
-- interrupt: 1.18 fast interrupt channel 2 --
|
-- interrupt: 1.18 fast interrupt channel 2 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_2_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq2_c;
|
trap_ctrl.cause_nxt <= trap_firq2_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_2_c) <= '1';
|
|
|
-- interrupt: 1.19 fast interrupt channel 3 --
|
-- interrupt: 1.19 fast interrupt channel 3 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq3_c;
|
trap_ctrl.cause_nxt <= trap_firq3_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
|
|
|
|
|
-- the following traps are caused by *synchronous* exceptions (= classic exceptions)
|
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions)
|
-- here we do not need a specific acknowledge mask since only one exception (the one
|
-- here we do not need a specific acknowledge mask since only one exception (the one
|
-- with highest priority) is evaluated at once
|
-- with highest priority) is evaluated at once
|
|
|
-- exception: 0.1 instruction access fault --
|
-- exception: 0.1 instruction access fault --
|
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_iba_c;
|
trap_ctrl.cause_nxt <= trap_iba_c;
|
|
|
-- exception: 0.2 illegal instruction --
|
-- exception: 0.2 illegal instruction --
|
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_iil_c;
|
trap_ctrl.cause_nxt <= trap_iil_c;
|
|
|
-- exception: 0.0 instruction address misaligned --
|
-- exception: 0.0 instruction address misaligned --
|
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_ima_c;
|
trap_ctrl.cause_nxt <= trap_ima_c;
|
|
|
|
|
-- exception: 0.11 environment call from M-mode --
|
-- exception: 0.11 environment call from M-mode --
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_menv_c;
|
trap_ctrl.cause_nxt <= trap_menv_c;
|
|
|
-- exception: 0.8 environment call from U-mode --
|
-- exception: 0.8 environment call from U-mode --
|
elsif (trap_ctrl.exc_buf(exception_u_envcall_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_u_envcall_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_uenv_c;
|
trap_ctrl.cause_nxt <= trap_uenv_c;
|
|
|
-- exception: 0.3 breakpoint --
|
-- exception: 0.3 breakpoint --
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_brk_c;
|
trap_ctrl.cause_nxt <= trap_brk_c;
|
|
|
|
|
-- exception: 0.6 store address misaligned -
|
-- exception: 0.6 store address misaligned -
|
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_sma_c;
|
trap_ctrl.cause_nxt <= trap_sma_c;
|
|
|
-- exception: 0.4 load address misaligned --
|
-- exception: 0.4 load address misaligned --
|
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_lma_c;
|
trap_ctrl.cause_nxt <= trap_lma_c;
|
|
|
-- exception: 0.7 store access fault --
|
-- exception: 0.7 store access fault --
|
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_sbe_c;
|
trap_ctrl.cause_nxt <= trap_sbe_c;
|
|
|
-- exception: 0.5 load access fault --
|
-- exception: 0.5 load access fault --
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_lbe_c;
|
trap_ctrl.cause_nxt <= trap_lbe_c;
|
|
|
-- undefined / not implemented --
|
-- not implemented --
|
else
|
else
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
end if;
|
end if;
|
end process trap_priority;
|
end process trap_priority;
|
|
|
|
|
-- Atomic Operation Controller ------------------------------------------------------------
|
-- Atomic Operation Controller ------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
atomics_controller: process(rstn_i, clk_i)
|
atomics_controller: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
atomic_ctrl.lock <= '0';
|
atomic_ctrl.lock <= '0';
|
atomic_ctrl.env_end_ff <= '0';
|
atomic_ctrl.env_end_ff <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (atomic_ctrl.env_end_ff = '1') or -- normal termination
|
if (atomic_ctrl.env_end_ff = '1') or -- normal termination
|
(atomic_ctrl.env_abort = '1') or -- fast termination (error)
|
(atomic_ctrl.env_abort = '1') or -- fast termination (error)
|
(trap_ctrl.env_start = '1') then -- triggered trap -> failure
|
(trap_ctrl.env_start = '1') then -- triggered trap -> failure
|
atomic_ctrl.lock <= '0';
|
atomic_ctrl.lock <= '0';
|
elsif (atomic_ctrl.env_start = '1') then
|
elsif (atomic_ctrl.env_start = '1') then
|
atomic_ctrl.lock <= '1';
|
atomic_ctrl.lock <= '1';
|
end if;
|
end if;
|
atomic_ctrl.env_end_ff <= atomic_ctrl.env_end;
|
atomic_ctrl.env_end_ff <= atomic_ctrl.env_end;
|
else
|
else
|
atomic_ctrl.lock <= '0';
|
atomic_ctrl.lock <= '0';
|
atomic_ctrl.env_end_ff <= '0';
|
atomic_ctrl.env_end_ff <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process atomics_controller;
|
end process atomics_controller;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Control and Status Registers (CSRs)
|
-- Control and Status Registers (CSRs)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Control and Status Registers Write Data ------------------------------------------------
|
-- Control and Status Registers Write Data ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
|
csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
|
variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
|
variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
|
begin
|
begin
|
-- CSR operand source --
|
-- CSR operand source --
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
|
csr_operand_v := (others => '0');
|
csr_operand_v := (others => '0');
|
csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
|
csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
|
else -- register
|
else -- register
|
csr_operand_v := rs1_i;
|
csr_operand_v := rs1_i;
|
end if;
|
end if;
|
-- tiny ALU for CSR write operations --
|
-- tiny ALU for CSR write operations --
|
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
|
when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
|
when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
|
when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
|
when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
|
when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
|
when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
|
end case;
|
end case;
|
end process csr_write_data;
|
end process csr_write_data;
|
|
|
|
|
-- Control and Status Registers Write Access ----------------------------------------------
|
-- Control and Status Registers Write Access ----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_write_access: process(rstn_i, clk_i)
|
csr_write_access: process(rstn_i, clk_i)
|
|
variable pmpaddr_v : std_ulogic_vector(6 downto 0);
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
csr.we <= '0';
|
csr.we <= '0';
|
--
|
--
|
csr.mstatus_mie <= '0';
|
csr.mstatus_mie <= '0';
|
csr.mstatus_mpie <= '0';
|
csr.mstatus_mpie <= '0';
|
csr.mstatus_mpp <= priv_mode_m_c; -- start in MACHINE mode
|
csr.mstatus_mpp <= priv_mode_m_c; -- start in MACHINE mode
|
csr.privilege <= priv_mode_m_c; -- start in MACHINE mode
|
csr.privilege <= priv_mode_m_c; -- start in MACHINE mode
|
csr.mie_msie <= '0';
|
csr.mie_msie <= '0';
|
csr.mie_meie <= '0';
|
csr.mie_meie <= '0';
|
csr.mie_mtie <= '0';
|
csr.mie_mtie <= '0';
|
csr.mie_firqe <= (others => '0');
|
csr.mie_firqe <= (others => '0');
|
csr.mtvec <= (others => '0');
|
csr.mtvec <= (others => '0');
|
csr.mscratch <= x"19880704"; -- :)
|
csr.mscratch <= x"19880704"; -- :)
|
csr.mepc <= (others => '0');
|
csr.mepc <= (others => '0');
|
-- mcause = TRAP_CODE_RESET (hardware reset, 0x80000000)
|
-- mcause = TRAP_CODE_RESET (hardware reset, "non-maskable interrupt")
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mcause(csr.mcause'left) <= trap_reset_c(trap_reset_c'left);
|
csr.mcause(csr.mcause'left) <= trap_reset_c(trap_reset_c'left);
|
csr.mcause(trap_reset_c'left-1 downto 0) <= trap_reset_c(trap_reset_c'left-1 downto 0);
|
csr.mcause(trap_reset_c'left-1 downto 0) <= trap_reset_c(trap_reset_c'left-1 downto 0);
|
--
|
--
|
csr.mtval <= (others => '0');
|
csr.mtval <= (others => '0');
|
csr.mip_clear <= (others => '0');
|
csr.mip_clear <= (others => '0');
|
|
--
|
csr.pmpcfg <= (others => (others => '0'));
|
csr.pmpcfg <= (others => (others => '0'));
|
csr.pmpaddr <= (others => (others => '1'));
|
csr.pmpaddr <= (others => (others => '1'));
|
--
|
--
|
|
csr.mhpmevent <= (others => (others => '0'));
|
|
--
|
csr.mcounteren_cy <= '0';
|
csr.mcounteren_cy <= '0';
|
csr.mcounteren_tm <= '0';
|
csr.mcounteren_tm <= '0';
|
csr.mcounteren_ir <= '0';
|
csr.mcounteren_ir <= '0';
|
|
csr.mcounteren_hpm <= (others => '0');
|
|
--
|
csr.mcountinhibit_cy <= '0';
|
csr.mcountinhibit_cy <= '0';
|
csr.mcountinhibit_ir <= '0';
|
csr.mcountinhibit_ir <= '0';
|
--
|
csr.mcountinhibit_hpm <= (others => '0');
|
csr.mcycle <= (others => '0');
|
|
csr.minstret <= (others => '0');
|
|
csr.mcycleh <= (others => '0');
|
|
csr.minstreth <= (others => '0');
|
|
mcycle_msb <= '0';
|
|
minstret_msb <= '0';
|
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- write access? --
|
-- write access? --
|
csr.we <= csr.we_nxt;
|
csr.we <= csr.we_nxt;
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
|
|
-- defaults --
|
-- defaults --
|
csr.mip_clear <= (others => '0');
|
csr.mip_clear <= (others => '0');
|
|
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSR access by application software
|
-- CSR access by application software
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
if (csr.we = '1') then -- manual update
|
if (csr.we = '1') then -- manual update
|
case csr.addr is
|
case csr.addr is
|
|
|
-- machine trap setup --
|
-- machine trap setup --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
csr.mstatus_mie <= csr.wdata(03);
|
csr.mstatus_mie <= csr.wdata(03);
|
csr.mstatus_mpie <= csr.wdata(07);
|
csr.mstatus_mpie <= csr.wdata(07);
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
|
else -- only machine mode is available
|
else -- only machine mode is available
|
csr.mstatus_mpp <= priv_mode_m_c;
|
csr.mstatus_mpp <= priv_mode_m_c;
|
end if;
|
end if;
|
when csr_mie_c => -- R/W: mie - machine interrupt enable register
|
when csr_mie_c => -- R/W: mie - machine interrupt enable register
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
--
|
--
|
csr.mie_firqe(0) <= csr.wdata(16); -- fast interrupt channel 0
|
csr.mie_firqe(0) <= csr.wdata(16); -- fast interrupt channel 0
|
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1
|
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1
|
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2
|
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2
|
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3
|
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
when csr_mcounteren_c => -- R/W: machine counter enable register
|
when csr_mcounteren_c => -- R/W: machine counter enable register
|
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
|
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
|
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
|
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
|
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
|
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
|
|
csr.mcounteren_hpm <= csr.wdata(csr.mcounteren_hpm'left+3 downto 3); -- enable user-level access to mhpmcounterx[h]
|
|
|
-- machine trap handling --
|
-- machine trap handling --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
csr.mscratch <= csr.wdata;
|
csr.mscratch <= csr.wdata;
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
|
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
|
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
|
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
|
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
|
when csr_mtval_c => -- R/W: mtval - machine bad address/instruction
|
when csr_mtval_c => -- R/W: mtval - machine bad address/instruction
|
csr.mtval <= csr.wdata;
|
csr.mtval <= csr.wdata;
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03);
|
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03);
|
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
|
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
|
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11);
|
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11);
|
--
|
--
|
csr.mip_clear(interrupt_firq_0_c) <= not csr.wdata(16);
|
csr.mip_clear(interrupt_firq_0_c) <= not csr.wdata(16);
|
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17);
|
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17);
|
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18);
|
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18);
|
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19);
|
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19);
|
|
|
-- physical memory protection - configuration --
|
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - PMP configuration register 0
|
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
|
if (PMP_USE = true) and (pmp_num_regions_c >= 1) then
|
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
if ((j+1) <= pmp_num_regions_c) then
|
if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) then
|
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
|
if (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpcfg access
|
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
|
csr.pmpcfg(i)(0) <= csr.wdata((i mod 4)*8+0); -- R (rights.read)
|
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
|
csr.pmpcfg(i)(1) <= csr.wdata((i mod 4)*8+1); -- W (rights.write)
|
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
|
csr.pmpcfg(i)(2) <= csr.wdata((i mod 4)*8+2); -- X (rights.execute)
|
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(i)(3) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_L
|
csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(i)(4) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(0+j)(5) <= '0'; -- reserved
|
csr.pmpcfg(i)(5) <= '0'; -- reserved
|
csr.pmpcfg(0+j)(6) <= '0'; -- reserved
|
csr.pmpcfg(i)(6) <= '0'; -- reserved
|
csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode)
|
csr.pmpcfg(i)(7) <= csr.wdata((i mod 4)*8+7); -- L (locked / rights also enforced in m-mode)
|
end if;
|
|
end if;
|
|
end loop; -- j (bytes in CSR)
|
|
end if;
|
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - PMP configuration register 1
|
|
if (PMP_USE = true) and (pmp_num_regions_c >= 5) then
|
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
|
if ((j+1+4) <= pmp_num_regions_c) then
|
|
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
|
|
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
|
|
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
|
|
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
|
|
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
|
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
|
csr.pmpcfg(4+j)(5) <= '0'; -- reserved
|
|
csr.pmpcfg(4+j)(6) <= '0'; -- reserved
|
|
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode)
|
|
end if;
|
|
end if;
|
end if;
|
end loop; -- j (bytes in CSR)
|
|
end if;
|
end if;
|
|
end loop; -- i (PMP regions)
|
|
|
-- physical memory protection - addresses --
|
-- physical memory protection: R/W: pmpaddr* - PMP address registers --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c |
|
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c |
|
csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c => -- R/W: pmpaddr0..7 - PMP address register 0..7
|
csr_pmpaddr8_c | csr_pmpaddr9_c | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
|
if (PMP_USE = true) then
|
csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c |
|
for i in 0 to pmp_num_regions_c-1 loop
|
csr_pmpaddr24_c | csr_pmpaddr25_c | csr_pmpaddr26_c | csr_pmpaddr27_c | csr_pmpaddr28_c | csr_pmpaddr29_c | csr_pmpaddr30_c | csr_pmpaddr31_c |
|
if (csr.addr(2 downto 0) = std_ulogic_vector(to_unsigned(i, 3))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c |
|
|
csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
|
|
csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
|
|
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
|
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
|
pmpaddr_v := std_ulogic_vector(unsigned(csr_pmpaddr0_c(6 downto 0)) + i); -- adapt to *non-aligned* base address (csr_pmpaddr0_c)
|
|
if (csr.addr(6 downto 0) = pmpaddr_v) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
csr.pmpaddr(i) <= csr.wdata;
|
csr.pmpaddr(i) <= csr.wdata;
|
csr.pmpaddr(i)(index_size_f(pmp_min_granularity_c)-4 downto 0) <= (others => '1');
|
csr.pmpaddr(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
|
end if;
|
|
end loop; -- i (CSRs)
|
|
end if;
|
end if;
|
|
end loop; -- i (PMP regions)
|
|
|
-- machine counter setup --
|
-- machine counter setup --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register
|
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register
|
csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
|
csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
|
csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
|
csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
|
|
csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter
|
|
|
|
-- machine performance-monitoring event selector --
|
|
-- --------------------------------------------------------------------
|
|
when csr_mhpmevent3_c | csr_mhpmevent4_c | csr_mhpmevent5_c | csr_mhpmevent6_c | csr_mhpmevent7_c | csr_mhpmevent8_c |
|
|
csr_mhpmevent9_c | csr_mhpmevent10_c | csr_mhpmevent11_c | csr_mhpmevent12_c | csr_mhpmevent13_c | csr_mhpmevent14_c |
|
|
csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
|
|
csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
|
|
csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c => -- R/W: mhpmevent* - machine performance-monitoring event selector
|
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
|
if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then
|
|
csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0);
|
|
end if;
|
|
end loop; -- i (CSRs)
|
|
|
-- undefined --
|
-- undefined --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when others =>
|
when others =>
|
NULL;
|
NULL;
|
|
|
end case;
|
end case;
|
|
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSR access by hardware
|
-- CSR access by hardware
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
else
|
else
|
|
|
-- mcause, mepc, mtval: machine trap cause, PC and value register --
|
-- mcause, mepc, mtval: machine trap cause, PC and value register --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
-- trap cause ID code --
|
-- trap cause ID code --
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
|
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
|
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
|
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
|
-- trap PC --
|
-- trap PC --
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
else -- for EXCEPTIONS
|
else -- for EXCEPTIONS
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
end if;
|
end if;
|
-- trap value --
|
-- trap value --
|
case trap_ctrl.cause is
|
case trap_ctrl.cause is
|
when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
|
when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
when trap_brk_c => -- breakpoint
|
when trap_brk_c => -- breakpoint
|
csr.mtval <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- address of breakpoint instruction
|
csr.mtval <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- address of breakpoint instruction
|
when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
|
when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
|
csr.mtval <= mar_i; -- faulting data access address
|
csr.mtval <= mar_i; -- faulting data access address
|
when trap_iil_c => -- illegal instruction
|
when trap_iil_c => -- illegal instruction
|
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
|
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
|
when others => -- everything else including interrupts
|
when others => -- everything else including interrupts
|
csr.mtval <= (others => '0');
|
csr.mtval <= (others => '0');
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- mstatus: context switch --
|
-- mstatus: context switch --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
|
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
|
csr.mstatus_mie <= '0'; -- disable interrupts
|
csr.mstatus_mie <= '0'; -- disable interrupts
|
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
|
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
|
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
|
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
|
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
|
end if;
|
end if;
|
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception
|
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception
|
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
|
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
|
csr.mstatus_mpie <= '1';
|
csr.mstatus_mpie <= '1';
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
|
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
|
csr.mstatus_mpp <= priv_mode_m_c;
|
csr.mstatus_mpp <= priv_mode_m_c;
|
end if;
|
end if;
|
end if;
|
end if;
|
-- user mode NOT implemented --
|
-- user mode NOT implemented --
|
if (CPU_EXTENSION_RISCV_U = false) then
|
if (CPU_EXTENSION_RISCV_U = false) then
|
csr.privilege <= priv_mode_m_c;
|
csr.privilege <= priv_mode_m_c;
|
csr.mstatus_mpp <= priv_mode_m_c;
|
csr.mstatus_mpp <= priv_mode_m_c;
|
end if;
|
end if;
|
|
|
end if; -- hardware csr access
|
end if; -- hardware csr access
|
|
|
-- --------------------------------------------------------------------------------
|
end if;
|
-- Counter CSRs (each counter is split in two 32-bit counters)
|
end if;
|
-- --------------------------------------------------------------------------------
|
end process csr_write_access;
|
|
|
|
-- decode privilege mode --
|
|
csr.priv_m_mode <= '1' when (csr.privilege = priv_mode_m_c) or (CPU_EXTENSION_RISCV_U = false) else '0';
|
|
csr.priv_u_mode <= '1' when (csr.privilege = priv_mode_u_c) and (CPU_EXTENSION_RISCV_U = true) else '0';
|
|
|
|
-- PMP configuration output to bus unit --
|
|
pmp_output: process(csr)
|
|
begin
|
|
pmp_addr_o <= (others => (others => '0'));
|
|
pmp_ctrl_o <= (others => (others => '0'));
|
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
|
pmp_addr_o(i) <= csr.pmpaddr(i) & "11";
|
|
pmp_addr_o(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
|
|
pmp_ctrl_o(i) <= csr.pmpcfg(i);
|
|
end loop; -- i
|
|
end process pmp_output;
|
|
|
|
-- PMP read dummy --
|
|
pmp_rd_dummy: process(csr)
|
|
begin
|
|
csr.pmpcfg_rd <= (others => (others => '0'));
|
|
csr.pmpaddr_rd <= (others => (others => '0'));
|
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
|
csr.pmpcfg_rd(i) <= csr.pmpcfg(i);
|
|
csr.pmpaddr_rd(i) <= csr.pmpaddr(i);
|
|
if (csr.pmpcfg(i)(4 downto 3) = "00") then -- mode = off
|
|
csr.pmpaddr_rd(i)(index_size_f(PMP_MIN_GRANULARITY)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
|
end if;
|
|
end loop; -- i
|
|
end process pmp_rd_dummy;
|
|
|
|
|
|
-- Control and Status Registers - Counters ------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
csr_counters: process(clk_i)
|
|
begin
|
|
-- Counter CSRs (each counter is split into two 32-bit counters)
|
|
if rising_edge(clk_i) then
|
|
|
-- [m]cycle --
|
-- [m]cycle --
|
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
|
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
|
csr.mcycle <= '0' & csr.wdata;
|
csr.mcycle <= '0' & csr.wdata;
|
mcycle_msb <= '0';
|
mcycle_msb <= '0';
|
elsif (csr.mcountinhibit_cy = '0') and (execute_engine.sleep = '0') then -- non-inhibited automatic update (if CPU is not in sleep mode)
|
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
end if;
|
end if;
|
|
|
-- [m]cycleh --
|
-- [m]cycleh --
|
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
|
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
|
csr.mcycleh <= csr.wdata;
|
csr.mcycleh <= csr.wdata;
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update (continued)
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update (continued)
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
end if;
|
end if;
|
|
|
-- [m]instret --
|
-- [m]instret --
|
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
|
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
|
csr.minstret <= '0' & csr.wdata;
|
csr.minstret <= '0' & csr.wdata;
|
minstret_msb <= '0';
|
minstret_msb <= '0';
|
elsif (csr.mcountinhibit_ir = '0') and (execute_engine.state = EXECUTE) then -- non-inhibited automatic update (if CPU actually executes an instruction)
|
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
end if;
|
end if;
|
|
|
-- [m]instreth --
|
-- [m]instreth --
|
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
|
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
|
csr.minstreth <= csr.wdata;
|
csr.minstreth <= csr.wdata;
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update (continued)
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update (continued)
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
end if;
|
end if;
|
|
|
|
-- [machine] high performance counters --
|
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
|
-- [m]hpmcounter* --
|
|
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3_c) + i)) then -- write access
|
|
csr.mhpmcounter(i) <= '0' & csr.wdata;
|
|
mhpmcounter_msb(i) <= '0';
|
|
elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
|
|
csr.mhpmcounter(i) <= std_ulogic_vector(unsigned(csr.mhpmcounter(i)) + 1);
|
|
mhpmcounter_msb(i) <= csr.mhpmcounter(i)(csr.mhpmcounter(i)'left);
|
|
end if;
|
|
|
|
-- [m]hpmcounter*h --
|
|
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
|
|
csr.mhpmcounterh(i) <= csr.wdata;
|
|
elsif ((mhpmcounter_msb(i) xor csr.mhpmcounter(i)(csr.mhpmcounter(i)'left)) = '1') then -- automatic update (continued)
|
|
csr.mhpmcounterh(i) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)) + 1);
|
end if;
|
end if;
|
|
end loop; -- i
|
|
|
end if;
|
end if;
|
end process csr_write_access;
|
end process csr_counters;
|
|
|
-- decode privilege mode --
|
-- hpm read dummy --
|
csr.priv_m_mode <= '1' when (csr.privilege = priv_mode_m_c) or (CPU_EXTENSION_RISCV_U = false) else '0';
|
hpm_rd_dummy: process(csr)
|
csr.priv_u_mode <= '1' when (csr.privilege = priv_mode_u_c) and (CPU_EXTENSION_RISCV_U = true) else '0';
|
begin
|
|
csr.mhpmevent_rd <= (others => (others => '0'));
|
|
csr.mhpmcounter_rd <= (others => (others => '0'));
|
|
csr.mhpmcounterh_rd <= (others => (others => '0'));
|
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
|
csr.mhpmevent_rd(i) <= csr.mhpmevent(i);
|
|
csr.mhpmcounter_rd(i) <= csr.mhpmcounter(i);
|
|
csr.mhpmcounterh_rd(i) <= csr.mhpmcounterh(i);
|
|
end loop; -- i
|
|
end process hpm_rd_dummy;
|
|
|
-- PMP configuration output to bus unit --
|
|
pmp_output: process(csr)
|
-- (HPM) Counter Event Control ------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
hpmcnt_ctrl: process(clk_i)
|
begin
|
begin
|
pmp_addr_o <= (others => (others => '0'));
|
if rising_edge(clk_i) then
|
pmp_ctrl_o <= (others => (others => '0'));
|
cnt_event <= cnt_event_nxt;
|
if (PMP_USE = true) then
|
hpmcnt_trigger <= (others => '0'); -- default
|
for i in 0 to pmp_num_regions_c-1 loop
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
pmp_addr_o(i) <= csr.pmpaddr(i) & "11";
|
-- enabled selected triggers by ANDing events and configuration bits --
|
pmp_addr_o(i)(index_size_f(pmp_min_granularity_c)-4 downto 0) <= (others => '1');
|
-- OR everything to see if counter should increment --
|
pmp_ctrl_o(i) <= csr.pmpcfg(i);
|
-- AND with inverted sleep flag to increment only when CPU is awake --
|
|
hpmcnt_trigger(i) <= (or_all_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0))) and (not execute_engine.sleep);
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
end process pmp_output;
|
end process hpmcnt_ctrl;
|
|
|
|
-- counter event trigger - RISC-V specific --
|
|
cnt_event_nxt(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle
|
|
cnt_event_nxt(hpmcnt_event_never_c) <= '0'; -- undefined (never)
|
|
cnt_event_nxt(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction
|
|
|
|
-- counter event trigger - custom / NEORV32-specific --
|
|
cnt_event_nxt(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction
|
|
cnt_event_nxt(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle
|
|
cnt_event_nxt(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle
|
|
|
|
cnt_event_nxt(hpmcnt_event_load_c) <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_rd_c) = '1') else '0'; -- load operation
|
|
cnt_event_nxt(hpmcnt_event_store_c) <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_wr_c) = '1') else '0'; -- store operation
|
|
cnt_event_nxt(hpmcnt_event_wait_ls_c) <= '1' when (execute_engine.state = LOADSTORE_2) and (execute_engine.state_prev = LOADSTORE_2) else '0'; -- load/store memory wait cycle
|
|
|
|
cnt_event_nxt(hpmcnt_event_jump_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') else '0'; -- jump (unconditional)
|
|
cnt_event_nxt(hpmcnt_event_branch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken)
|
|
cnt_event_nxt(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional)
|
|
|
|
cnt_event_nxt(hpmcnt_event_trap_c) <= '1' when (trap_ctrl.env_start_ack = '1') else '0'; -- entered trap
|
|
cnt_event_nxt(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation
|
|
|
|
|
-- Control and Status Registers Read Access -----------------------------------------------
|
-- Control and Status Registers Read Access -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_read_access: process(clk_i)
|
csr_read_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
csr.re <= csr.re_nxt; -- read access?
|
csr.re <= csr.re_nxt; -- read access?
|
csr.rdata <= (others => '0'); -- default output
|
csr.rdata <= (others => '0'); -- default output
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
|
case csr.addr is
|
case csr.addr is
|
|
|
-- machine trap setup --
|
-- machine trap setup --
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(06) <= '1' and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- UBE: CPU/Processor is BIG-ENDIAN (in user-mode)
|
csr.rdata(06) <= '1' and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- UBE: CPU/Processor is BIG-ENDIAN (in user-mode)
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
|
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
|
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
|
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
|
when csr_mstatush_c => -- R/-: mstatush - machine status register - high part
|
when csr_mstatush_c => -- R/-: mstatush - machine status register - high part
|
csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN (in machine-mode)
|
csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN (in machine-mode)
|
when csr_misa_c => -- R/-: misa - ISA and extensions
|
when csr_misa_c => -- R/-: misa - ISA and extensions
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension
|
csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension
|
csr.rdata(23) <= '1'; -- X CPU extension (non-std extensions)
|
csr.rdata(23) <= '1'; -- X CPU extension (non-std extensions)
|
csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
|
csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
|
csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
|
csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
|
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
|
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
|
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
|
csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
|
csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
|
--
|
--
|
csr.rdata(16) <= csr.mie_firqe(0); -- fast interrupt channel 0
|
csr.rdata(16) <= csr.mie_firqe(0); -- fast interrupt channel 0
|
csr.rdata(17) <= csr.mie_firqe(1); -- fast interrupt channel 1
|
csr.rdata(17) <= csr.mie_firqe(1); -- fast interrupt channel 1
|
csr.rdata(18) <= csr.mie_firqe(2); -- fast interrupt channel 2
|
csr.rdata(18) <= csr.mie_firqe(2); -- fast interrupt channel 2
|
csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3
|
csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
when csr_mcounteren_c => -- R/W: machine counter enable register
|
when csr_mcounteren_c => -- R/W: machine counter enable register
|
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
|
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
|
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
|
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
|
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
|
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
|
|
csr.rdata(csr.mcounteren_hpm'left+3 downto 3) <= csr.mcounteren_hpm; -- enable user-level access to hpmcounterx[h]
|
|
|
-- machine trap handling --
|
-- machine trap handling --
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
csr.rdata <= csr.mscratch;
|
csr.rdata <= csr.mscratch;
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
csr.rdata <= csr.mcause;
|
csr.rdata <= csr.mcause;
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
csr.rdata <= csr.mtval;
|
csr.rdata <= csr.mtval;
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
|
csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
|
csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
|
csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
|
csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
|
csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
|
--
|
--
|
csr.rdata(16) <= csr.mip_status(interrupt_firq_0_c);
|
csr.rdata(16) <= csr.mip_status(interrupt_firq_0_c);
|
csr.rdata(17) <= csr.mip_status(interrupt_firq_1_c);
|
csr.rdata(17) <= csr.mip_status(interrupt_firq_1_c);
|
csr.rdata(18) <= csr.mip_status(interrupt_firq_2_c);
|
csr.rdata(18) <= csr.mip_status(interrupt_firq_2_c);
|
csr.rdata(19) <= csr.mip_status(interrupt_firq_3_c);
|
csr.rdata(19) <= csr.mip_status(interrupt_firq_3_c);
|
|
|
-- physical memory protection - configuration --
|
-- physical memory protection - configuration --
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - physical memory protection configuration register 0
|
when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0
|
if (PMP_USE = true) then
|
when csr_pmpcfg1_c => csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); -- R/W: pmpcfg1
|
if (pmp_num_regions_c >= 1) then
|
when csr_pmpcfg2_c => csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); -- R/W: pmpcfg2
|
csr.rdata(07 downto 00) <= csr.pmpcfg(0);
|
when csr_pmpcfg3_c => csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); -- R/W: pmpcfg3
|
end if;
|
when csr_pmpcfg4_c => csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); -- R/W: pmpcfg4
|
if (pmp_num_regions_c >= 2) then
|
when csr_pmpcfg5_c => csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); -- R/W: pmpcfg5
|
csr.rdata(15 downto 08) <= csr.pmpcfg(1);
|
when csr_pmpcfg6_c => csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); -- R/W: pmpcfg6
|
end if;
|
when csr_pmpcfg7_c => csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); -- R/W: pmpcfg7
|
if (pmp_num_regions_c >= 3) then
|
when csr_pmpcfg8_c => csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); -- R/W: pmpcfg8
|
csr.rdata(23 downto 16) <= csr.pmpcfg(2);
|
when csr_pmpcfg9_c => csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); -- R/W: pmpcfg9
|
end if;
|
when csr_pmpcfg10_c => csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); -- R/W: pmpcfg10
|
if (pmp_num_regions_c >= 4) then
|
when csr_pmpcfg11_c => csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); -- R/W: pmpcfg11
|
csr.rdata(31 downto 24) <= csr.pmpcfg(3);
|
when csr_pmpcfg12_c => csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); -- R/W: pmpcfg12
|
end if;
|
when csr_pmpcfg13_c => csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); -- R/W: pmpcfg13
|
end if;
|
when csr_pmpcfg14_c => csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); -- R/W: pmpcfg14
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - physical memory protection configuration register 1
|
when csr_pmpcfg15_c => csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); -- R/W: pmpcfg15
|
if (PMP_USE = true) then
|
|
if (pmp_num_regions_c >= 5) then
|
|
csr.rdata(07 downto 00) <= csr.pmpcfg(4);
|
|
end if;
|
|
if (pmp_num_regions_c >= 6) then
|
|
csr.rdata(15 downto 08) <= csr.pmpcfg(5);
|
|
end if;
|
|
if (pmp_num_regions_c >= 7) then
|
|
csr.rdata(23 downto 16) <= csr.pmpcfg(6);
|
|
end if;
|
|
if (pmp_num_regions_c >= 8) then
|
|
csr.rdata(31 downto 24) <= csr.pmpcfg(7);
|
|
end if;
|
|
end if;
|
|
|
|
-- physical memory protection - addresses --
|
-- physical memory protection - addresses --
|
when csr_pmpaddr0_c => -- R/W: pmpaddr0 - physical memory protection address register 0
|
when csr_pmpaddr0_c => csr.rdata <= csr.pmpaddr_rd(00); -- R/W: pmpaddr0
|
if (PMP_USE = true) and (pmp_num_regions_c >= 1) then
|
when csr_pmpaddr1_c => csr.rdata <= csr.pmpaddr_rd(01); -- R/W: pmpaddr1
|
csr.rdata <= csr.pmpaddr(0);
|
when csr_pmpaddr2_c => csr.rdata <= csr.pmpaddr_rd(02); -- R/W: pmpaddr2
|
if (csr.pmpcfg(0)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr3_c => csr.rdata <= csr.pmpaddr_rd(03); -- R/W: pmpaddr3
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr4_c => csr.rdata <= csr.pmpaddr_rd(04); -- R/W: pmpaddr4
|
end if;
|
when csr_pmpaddr5_c => csr.rdata <= csr.pmpaddr_rd(05); -- R/W: pmpaddr5
|
end if;
|
when csr_pmpaddr6_c => csr.rdata <= csr.pmpaddr_rd(06); -- R/W: pmpaddr6
|
when csr_pmpaddr1_c => -- R/W: pmpaddr1 - physical memory protection address register 1
|
when csr_pmpaddr7_c => csr.rdata <= csr.pmpaddr_rd(07); -- R/W: pmpaddr7
|
if (PMP_USE = true) and (pmp_num_regions_c >= 2) then
|
when csr_pmpaddr8_c => csr.rdata <= csr.pmpaddr_rd(08); -- R/W: pmpaddr8
|
csr.rdata <= csr.pmpaddr(1);
|
when csr_pmpaddr9_c => csr.rdata <= csr.pmpaddr_rd(09); -- R/W: pmpaddr9
|
if (csr.pmpcfg(1)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr10_c => csr.rdata <= csr.pmpaddr_rd(10); -- R/W: pmpaddr10
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr11_c => csr.rdata <= csr.pmpaddr_rd(11); -- R/W: pmpaddr11
|
end if;
|
when csr_pmpaddr12_c => csr.rdata <= csr.pmpaddr_rd(12); -- R/W: pmpaddr12
|
end if;
|
when csr_pmpaddr13_c => csr.rdata <= csr.pmpaddr_rd(13); -- R/W: pmpaddr13
|
when csr_pmpaddr2_c => -- R/W: pmpaddr2 - physical memory protection address register 2
|
when csr_pmpaddr14_c => csr.rdata <= csr.pmpaddr_rd(14); -- R/W: pmpaddr14
|
if (PMP_USE = true) and (pmp_num_regions_c >= 3) then
|
when csr_pmpaddr15_c => csr.rdata <= csr.pmpaddr_rd(15); -- R/W: pmpaddr15
|
csr.rdata <= csr.pmpaddr(2);
|
when csr_pmpaddr16_c => csr.rdata <= csr.pmpaddr_rd(16); -- R/W: pmpaddr16
|
if (csr.pmpcfg(2)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr17_c => csr.rdata <= csr.pmpaddr_rd(17); -- R/W: pmpaddr17
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr18_c => csr.rdata <= csr.pmpaddr_rd(18); -- R/W: pmpaddr18
|
end if;
|
when csr_pmpaddr19_c => csr.rdata <= csr.pmpaddr_rd(19); -- R/W: pmpaddr19
|
end if;
|
when csr_pmpaddr20_c => csr.rdata <= csr.pmpaddr_rd(20); -- R/W: pmpaddr20
|
when csr_pmpaddr3_c => -- R/W: pmpaddr3 - physical memory protection address register 3
|
when csr_pmpaddr21_c => csr.rdata <= csr.pmpaddr_rd(21); -- R/W: pmpaddr21
|
if (PMP_USE = true) and (pmp_num_regions_c >= 4) then
|
when csr_pmpaddr22_c => csr.rdata <= csr.pmpaddr_rd(22); -- R/W: pmpaddr22
|
csr.rdata <= csr.pmpaddr(3);
|
when csr_pmpaddr23_c => csr.rdata <= csr.pmpaddr_rd(23); -- R/W: pmpaddr23
|
if (csr.pmpcfg(3)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr24_c => csr.rdata <= csr.pmpaddr_rd(24); -- R/W: pmpaddr24
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr25_c => csr.rdata <= csr.pmpaddr_rd(25); -- R/W: pmpaddr25
|
end if;
|
when csr_pmpaddr26_c => csr.rdata <= csr.pmpaddr_rd(26); -- R/W: pmpaddr26
|
end if;
|
when csr_pmpaddr27_c => csr.rdata <= csr.pmpaddr_rd(27); -- R/W: pmpaddr27
|
when csr_pmpaddr4_c => -- R/W: pmpaddr4 - physical memory protection address register 4
|
when csr_pmpaddr28_c => csr.rdata <= csr.pmpaddr_rd(28); -- R/W: pmpaddr28
|
if (PMP_USE = true) and (pmp_num_regions_c >= 5) then
|
when csr_pmpaddr29_c => csr.rdata <= csr.pmpaddr_rd(29); -- R/W: pmpaddr29
|
csr.rdata <= csr.pmpaddr(4);
|
when csr_pmpaddr30_c => csr.rdata <= csr.pmpaddr_rd(30); -- R/W: pmpaddr30
|
if (csr.pmpcfg(4)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr31_c => csr.rdata <= csr.pmpaddr_rd(31); -- R/W: pmpaddr31
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr32_c => csr.rdata <= csr.pmpaddr_rd(32); -- R/W: pmpaddr32
|
end if;
|
when csr_pmpaddr33_c => csr.rdata <= csr.pmpaddr_rd(33); -- R/W: pmpaddr33
|
end if;
|
when csr_pmpaddr34_c => csr.rdata <= csr.pmpaddr_rd(34); -- R/W: pmpaddr34
|
when csr_pmpaddr5_c => -- R/W: pmpaddr5 - physical memory protection address register 5
|
when csr_pmpaddr35_c => csr.rdata <= csr.pmpaddr_rd(35); -- R/W: pmpaddr35
|
if (PMP_USE = true) and (pmp_num_regions_c >= 6) then
|
when csr_pmpaddr36_c => csr.rdata <= csr.pmpaddr_rd(36); -- R/W: pmpaddr36
|
csr.rdata <= csr.pmpaddr(5);
|
when csr_pmpaddr37_c => csr.rdata <= csr.pmpaddr_rd(37); -- R/W: pmpaddr37
|
if (csr.pmpcfg(5)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr38_c => csr.rdata <= csr.pmpaddr_rd(38); -- R/W: pmpaddr38
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr39_c => csr.rdata <= csr.pmpaddr_rd(39); -- R/W: pmpaddr39
|
end if;
|
when csr_pmpaddr40_c => csr.rdata <= csr.pmpaddr_rd(40); -- R/W: pmpaddr40
|
end if;
|
when csr_pmpaddr41_c => csr.rdata <= csr.pmpaddr_rd(41); -- R/W: pmpaddr41
|
when csr_pmpaddr6_c => -- R/W: pmpaddr6 - physical memory protection address register 6
|
when csr_pmpaddr42_c => csr.rdata <= csr.pmpaddr_rd(42); -- R/W: pmpaddr42
|
if (PMP_USE = true) and (pmp_num_regions_c >= 7) then
|
when csr_pmpaddr43_c => csr.rdata <= csr.pmpaddr_rd(43); -- R/W: pmpaddr43
|
csr.rdata <= csr.pmpaddr(6);
|
when csr_pmpaddr44_c => csr.rdata <= csr.pmpaddr_rd(44); -- R/W: pmpaddr44
|
if (csr.pmpcfg(6)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr45_c => csr.rdata <= csr.pmpaddr_rd(45); -- R/W: pmpaddr45
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr46_c => csr.rdata <= csr.pmpaddr_rd(46); -- R/W: pmpaddr46
|
end if;
|
when csr_pmpaddr47_c => csr.rdata <= csr.pmpaddr_rd(47); -- R/W: pmpaddr47
|
end if;
|
when csr_pmpaddr48_c => csr.rdata <= csr.pmpaddr_rd(48); -- R/W: pmpaddr48
|
when csr_pmpaddr7_c => -- R/W: pmpaddr7 - physical memory protection address register 7
|
when csr_pmpaddr49_c => csr.rdata <= csr.pmpaddr_rd(49); -- R/W: pmpaddr49
|
if (PMP_USE = true) and (pmp_num_regions_c >= 8) then
|
when csr_pmpaddr50_c => csr.rdata <= csr.pmpaddr_rd(50); -- R/W: pmpaddr50
|
csr.rdata <= csr.pmpaddr(7);
|
when csr_pmpaddr51_c => csr.rdata <= csr.pmpaddr_rd(51); -- R/W: pmpaddr51
|
if (csr.pmpcfg(7)(4 downto 3) = "00") then -- mode = off
|
when csr_pmpaddr52_c => csr.rdata <= csr.pmpaddr_rd(52); -- R/W: pmpaddr52
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
when csr_pmpaddr53_c => csr.rdata <= csr.pmpaddr_rd(53); -- R/W: pmpaddr53
|
end if;
|
when csr_pmpaddr54_c => csr.rdata <= csr.pmpaddr_rd(54); -- R/W: pmpaddr54
|
end if;
|
when csr_pmpaddr55_c => csr.rdata <= csr.pmpaddr_rd(55); -- R/W: pmpaddr55
|
|
when csr_pmpaddr56_c => csr.rdata <= csr.pmpaddr_rd(56); -- R/W: pmpaddr56
|
|
when csr_pmpaddr57_c => csr.rdata <= csr.pmpaddr_rd(57); -- R/W: pmpaddr57
|
|
when csr_pmpaddr58_c => csr.rdata <= csr.pmpaddr_rd(58); -- R/W: pmpaddr58
|
|
when csr_pmpaddr59_c => csr.rdata <= csr.pmpaddr_rd(59); -- R/W: pmpaddr59
|
|
when csr_pmpaddr60_c => csr.rdata <= csr.pmpaddr_rd(60); -- R/W: pmpaddr60
|
|
when csr_pmpaddr61_c => csr.rdata <= csr.pmpaddr_rd(61); -- R/W: pmpaddr61
|
|
when csr_pmpaddr62_c => csr.rdata <= csr.pmpaddr_rd(62); -- R/W: pmpaddr62
|
|
when csr_pmpaddr63_c => csr.rdata <= csr.pmpaddr_rd(63); -- R/W: pmpaddr63
|
|
|
-- machine counter setup --
|
-- machine counter setup --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register
|
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register
|
csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter
|
csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter
|
csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter
|
csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter
|
|
csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter
|
|
|
|
-- machine performance-monitoring event selector --
|
|
when csr_mhpmevent3_c => csr.rdata(csr.mhpmevent_rd(00)'left downto 0) <= csr.mhpmevent_rd(00); -- R/W: mhpmevent3
|
|
when csr_mhpmevent4_c => csr.rdata(csr.mhpmevent_rd(01)'left downto 0) <= csr.mhpmevent_rd(01); -- R/W: mhpmevent4
|
|
when csr_mhpmevent5_c => csr.rdata(csr.mhpmevent_rd(02)'left downto 0) <= csr.mhpmevent_rd(02); -- R/W: mhpmevent5
|
|
when csr_mhpmevent6_c => csr.rdata(csr.mhpmevent_rd(03)'left downto 0) <= csr.mhpmevent_rd(03); -- R/W: mhpmevent6
|
|
when csr_mhpmevent7_c => csr.rdata(csr.mhpmevent_rd(04)'left downto 0) <= csr.mhpmevent_rd(04); -- R/W: mhpmevent7
|
|
when csr_mhpmevent8_c => csr.rdata(csr.mhpmevent_rd(05)'left downto 0) <= csr.mhpmevent_rd(05); -- R/W: mhpmevent8
|
|
when csr_mhpmevent9_c => csr.rdata(csr.mhpmevent_rd(06)'left downto 0) <= csr.mhpmevent_rd(06); -- R/W: mhpmevent9
|
|
when csr_mhpmevent10_c => csr.rdata(csr.mhpmevent_rd(07)'left downto 0) <= csr.mhpmevent_rd(07); -- R/W: mhpmevent10
|
|
when csr_mhpmevent11_c => csr.rdata(csr.mhpmevent_rd(08)'left downto 0) <= csr.mhpmevent_rd(08); -- R/W: mhpmevent11
|
|
when csr_mhpmevent12_c => csr.rdata(csr.mhpmevent_rd(09)'left downto 0) <= csr.mhpmevent_rd(09); -- R/W: mhpmevent12
|
|
when csr_mhpmevent13_c => csr.rdata(csr.mhpmevent_rd(10)'left downto 0) <= csr.mhpmevent_rd(10); -- R/W: mhpmevent13
|
|
when csr_mhpmevent14_c => csr.rdata(csr.mhpmevent_rd(11)'left downto 0) <= csr.mhpmevent_rd(11); -- R/W: mhpmevent14
|
|
when csr_mhpmevent15_c => csr.rdata(csr.mhpmevent_rd(12)'left downto 0) <= csr.mhpmevent_rd(12); -- R/W: mhpmevent15
|
|
when csr_mhpmevent16_c => csr.rdata(csr.mhpmevent_rd(13)'left downto 0) <= csr.mhpmevent_rd(13); -- R/W: mhpmevent16
|
|
when csr_mhpmevent17_c => csr.rdata(csr.mhpmevent_rd(14)'left downto 0) <= csr.mhpmevent_rd(14); -- R/W: mhpmevent17
|
|
when csr_mhpmevent18_c => csr.rdata(csr.mhpmevent_rd(15)'left downto 0) <= csr.mhpmevent_rd(15); -- R/W: mhpmevent18
|
|
when csr_mhpmevent19_c => csr.rdata(csr.mhpmevent_rd(16)'left downto 0) <= csr.mhpmevent_rd(16); -- R/W: mhpmevent19
|
|
when csr_mhpmevent20_c => csr.rdata(csr.mhpmevent_rd(17)'left downto 0) <= csr.mhpmevent_rd(17); -- R/W: mhpmevent20
|
|
when csr_mhpmevent21_c => csr.rdata(csr.mhpmevent_rd(18)'left downto 0) <= csr.mhpmevent_rd(18); -- R/W: mhpmevent21
|
|
when csr_mhpmevent22_c => csr.rdata(csr.mhpmevent_rd(19)'left downto 0) <= csr.mhpmevent_rd(19); -- R/W: mhpmevent22
|
|
when csr_mhpmevent23_c => csr.rdata(csr.mhpmevent_rd(20)'left downto 0) <= csr.mhpmevent_rd(20); -- R/W: mhpmevent23
|
|
when csr_mhpmevent24_c => csr.rdata(csr.mhpmevent_rd(21)'left downto 0) <= csr.mhpmevent_rd(21); -- R/W: mhpmevent24
|
|
when csr_mhpmevent25_c => csr.rdata(csr.mhpmevent_rd(22)'left downto 0) <= csr.mhpmevent_rd(22); -- R/W: mhpmevent25
|
|
when csr_mhpmevent26_c => csr.rdata(csr.mhpmevent_rd(23)'left downto 0) <= csr.mhpmevent_rd(23); -- R/W: mhpmevent26
|
|
when csr_mhpmevent27_c => csr.rdata(csr.mhpmevent_rd(24)'left downto 0) <= csr.mhpmevent_rd(24); -- R/W: mhpmevent27
|
|
when csr_mhpmevent28_c => csr.rdata(csr.mhpmevent_rd(25)'left downto 0) <= csr.mhpmevent_rd(25); -- R/W: mhpmevent28
|
|
when csr_mhpmevent29_c => csr.rdata(csr.mhpmevent_rd(26)'left downto 0) <= csr.mhpmevent_rd(26); -- R/W: mhpmevent29
|
|
when csr_mhpmevent30_c => csr.rdata(csr.mhpmevent_rd(27)'left downto 0) <= csr.mhpmevent_rd(27); -- R/W: mhpmevent30
|
|
when csr_mhpmevent31_c => csr.rdata(csr.mhpmevent_rd(28)'left downto 0) <= csr.mhpmevent_rd(28); -- R/W: mhpmevent31
|
|
|
-- counters and timers --
|
-- counters and timers --
|
when csr_cycle_c | csr_mcycle_c => -- R/(W): [m]cycle: Cycle counter LOW
|
when csr_cycle_c | csr_mcycle_c => -- (R)/(W): [m]cycle: Cycle counter LOW
|
csr.rdata <= csr.mcycle(31 downto 0);
|
csr.rdata <= csr.mcycle(31 downto 0);
|
when csr_time_c => -- R/-: time: System time LOW (from MTIME unit)
|
when csr_time_c => -- (R)/-: time: System time LOW (from MTIME unit)
|
csr.rdata <= time_i(31 downto 0);
|
csr.rdata <= time_i(31 downto 0);
|
when csr_instret_c | csr_minstret_c => -- R/(W): [m]instret: Instructions-retired counter LOW
|
when csr_instret_c | csr_minstret_c => -- (R)/(W): [m]instret: Instructions-retired counter LOW
|
csr.rdata <= csr.minstret(31 downto 0);
|
csr.rdata <= csr.minstret(31 downto 0);
|
when csr_cycleh_c | csr_mcycleh_c => -- R/(W): [m]cycleh: Cycle counter HIGH
|
when csr_cycleh_c | csr_mcycleh_c => -- (R)/(W): [m]cycleh: Cycle counter HIGH
|
csr.rdata <= csr.mcycleh(31 downto 0);
|
csr.rdata <= csr.mcycleh(31 downto 0);
|
when csr_timeh_c => -- R/-: timeh: System time HIGH (from MTIME unit)
|
when csr_timeh_c => -- (R)/-: timeh: System time HIGH (from MTIME unit)
|
csr.rdata <= time_i(63 downto 32);
|
csr.rdata <= time_i(63 downto 32);
|
when csr_instreth_c | csr_minstreth_c => -- R/(W): [m]instreth: Instructions-retired counter HIGH
|
when csr_instreth_c | csr_minstreth_c => -- (R)/(W): [m]instreth: Instructions-retired counter HIGH
|
csr.rdata <= csr.minstreth(31 downto 0);
|
csr.rdata <= csr.minstreth(31 downto 0);
|
|
|
|
-- hardware performance counters --
|
|
when csr_hpmcounter3_c | csr_mhpmcounter3_c => csr.rdata <= csr.mhpmcounter_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3 - low
|
|
when csr_hpmcounter4_c | csr_mhpmcounter4_c => csr.rdata <= csr.mhpmcounter_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4 - low
|
|
when csr_hpmcounter5_c | csr_mhpmcounter5_c => csr.rdata <= csr.mhpmcounter_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5 - low
|
|
when csr_hpmcounter6_c | csr_mhpmcounter6_c => csr.rdata <= csr.mhpmcounter_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6 - low
|
|
when csr_hpmcounter7_c | csr_mhpmcounter7_c => csr.rdata <= csr.mhpmcounter_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7 - low
|
|
when csr_hpmcounter8_c | csr_mhpmcounter8_c => csr.rdata <= csr.mhpmcounter_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8 - low
|
|
when csr_hpmcounter9_c | csr_mhpmcounter9_c => csr.rdata <= csr.mhpmcounter_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9 - low
|
|
when csr_hpmcounter10_c | csr_mhpmcounter10_c => csr.rdata <= csr.mhpmcounter_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10 - low
|
|
when csr_hpmcounter11_c | csr_mhpmcounter11_c => csr.rdata <= csr.mhpmcounter_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11 - low
|
|
when csr_hpmcounter12_c | csr_mhpmcounter12_c => csr.rdata <= csr.mhpmcounter_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12 - low
|
|
when csr_hpmcounter13_c | csr_mhpmcounter13_c => csr.rdata <= csr.mhpmcounter_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13 - low
|
|
when csr_hpmcounter14_c | csr_mhpmcounter14_c => csr.rdata <= csr.mhpmcounter_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14 - low
|
|
when csr_hpmcounter15_c | csr_mhpmcounter15_c => csr.rdata <= csr.mhpmcounter_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15 - low
|
|
when csr_hpmcounter16_c | csr_mhpmcounter16_c => csr.rdata <= csr.mhpmcounter_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16 - low
|
|
when csr_hpmcounter17_c | csr_mhpmcounter17_c => csr.rdata <= csr.mhpmcounter_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17 - low
|
|
when csr_hpmcounter18_c | csr_mhpmcounter18_c => csr.rdata <= csr.mhpmcounter_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18 - low
|
|
when csr_hpmcounter19_c | csr_mhpmcounter19_c => csr.rdata <= csr.mhpmcounter_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19 - low
|
|
when csr_hpmcounter20_c | csr_mhpmcounter20_c => csr.rdata <= csr.mhpmcounter_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20 - low
|
|
when csr_hpmcounter21_c | csr_mhpmcounter21_c => csr.rdata <= csr.mhpmcounter_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21 - low
|
|
when csr_hpmcounter22_c | csr_mhpmcounter22_c => csr.rdata <= csr.mhpmcounter_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22 - low
|
|
when csr_hpmcounter23_c | csr_mhpmcounter23_c => csr.rdata <= csr.mhpmcounter_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23 - low
|
|
when csr_hpmcounter24_c | csr_mhpmcounter24_c => csr.rdata <= csr.mhpmcounter_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24 - low
|
|
when csr_hpmcounter25_c | csr_mhpmcounter25_c => csr.rdata <= csr.mhpmcounter_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25 - low
|
|
when csr_hpmcounter26_c | csr_mhpmcounter26_c => csr.rdata <= csr.mhpmcounter_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26 - low
|
|
when csr_hpmcounter27_c | csr_mhpmcounter27_c => csr.rdata <= csr.mhpmcounter_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27 - low
|
|
when csr_hpmcounter28_c | csr_mhpmcounter28_c => csr.rdata <= csr.mhpmcounter_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28 - low
|
|
when csr_hpmcounter29_c | csr_mhpmcounter29_c => csr.rdata <= csr.mhpmcounter_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29 - low
|
|
when csr_hpmcounter30_c | csr_mhpmcounter30_c => csr.rdata <= csr.mhpmcounter_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30 - low
|
|
when csr_hpmcounter31_c | csr_mhpmcounter31_c => csr.rdata <= csr.mhpmcounter_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31 - low
|
|
|
|
when csr_hpmcounter3h_c | csr_mhpmcounter3h_c => csr.rdata <= csr.mhpmcounterh_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3h - high
|
|
when csr_hpmcounter4h_c | csr_mhpmcounter4h_c => csr.rdata <= csr.mhpmcounterh_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4h - high
|
|
when csr_hpmcounter5h_c | csr_mhpmcounter5h_c => csr.rdata <= csr.mhpmcounterh_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5h - high
|
|
when csr_hpmcounter6h_c | csr_mhpmcounter6h_c => csr.rdata <= csr.mhpmcounterh_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6h - high
|
|
when csr_hpmcounter7h_c | csr_mhpmcounter7h_c => csr.rdata <= csr.mhpmcounterh_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7h - high
|
|
when csr_hpmcounter8h_c | csr_mhpmcounter8h_c => csr.rdata <= csr.mhpmcounterh_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8h - high
|
|
when csr_hpmcounter9h_c | csr_mhpmcounter9h_c => csr.rdata <= csr.mhpmcounterh_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9h - high
|
|
when csr_hpmcounter10h_c | csr_mhpmcounter10h_c => csr.rdata <= csr.mhpmcounterh_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10h - high
|
|
when csr_hpmcounter11h_c | csr_mhpmcounter11h_c => csr.rdata <= csr.mhpmcounterh_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11h - high
|
|
when csr_hpmcounter12h_c | csr_mhpmcounter12h_c => csr.rdata <= csr.mhpmcounterh_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12h - high
|
|
when csr_hpmcounter13h_c | csr_mhpmcounter13h_c => csr.rdata <= csr.mhpmcounterh_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13h - high
|
|
when csr_hpmcounter14h_c | csr_mhpmcounter14h_c => csr.rdata <= csr.mhpmcounterh_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14h - high
|
|
when csr_hpmcounter15h_c | csr_mhpmcounter15h_c => csr.rdata <= csr.mhpmcounterh_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15h - high
|
|
when csr_hpmcounter16h_c | csr_mhpmcounter16h_c => csr.rdata <= csr.mhpmcounterh_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16h - high
|
|
when csr_hpmcounter17h_c | csr_mhpmcounter17h_c => csr.rdata <= csr.mhpmcounterh_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17h - high
|
|
when csr_hpmcounter18h_c | csr_mhpmcounter18h_c => csr.rdata <= csr.mhpmcounterh_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18h - high
|
|
when csr_hpmcounter19h_c | csr_mhpmcounter19h_c => csr.rdata <= csr.mhpmcounterh_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19h - high
|
|
when csr_hpmcounter20h_c | csr_mhpmcounter20h_c => csr.rdata <= csr.mhpmcounterh_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20h - high
|
|
when csr_hpmcounter21h_c | csr_mhpmcounter21h_c => csr.rdata <= csr.mhpmcounterh_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21h - high
|
|
when csr_hpmcounter22h_c | csr_mhpmcounter22h_c => csr.rdata <= csr.mhpmcounterh_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22h - high
|
|
when csr_hpmcounter23h_c | csr_mhpmcounter23h_c => csr.rdata <= csr.mhpmcounterh_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23h - high
|
|
when csr_hpmcounter24h_c | csr_mhpmcounter24h_c => csr.rdata <= csr.mhpmcounterh_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24h - high
|
|
when csr_hpmcounter25h_c | csr_mhpmcounter25h_c => csr.rdata <= csr.mhpmcounterh_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25h - high
|
|
when csr_hpmcounter26h_c | csr_mhpmcounter26h_c => csr.rdata <= csr.mhpmcounterh_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26h - high
|
|
when csr_hpmcounter27h_c | csr_mhpmcounter27h_c => csr.rdata <= csr.mhpmcounterh_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27h - high
|
|
when csr_hpmcounter28h_c | csr_mhpmcounter28h_c => csr.rdata <= csr.mhpmcounterh_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28h - high
|
|
when csr_hpmcounter29h_c | csr_mhpmcounter29h_c => csr.rdata <= csr.mhpmcounterh_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29h - high
|
|
when csr_hpmcounter30h_c | csr_mhpmcounter30h_c => csr.rdata <= csr.mhpmcounterh_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30h - high
|
|
when csr_hpmcounter31h_c | csr_mhpmcounter31h_c => csr.rdata <= csr.mhpmcounterh_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31h - high
|
|
|
-- machine information registers --
|
-- machine information registers --
|
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
|
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
|
csr.rdata <= (others => '0');
|
csr.rdata <= (others => '0');
|
when csr_marchid_c => -- R/-: marchid - arch ID
|
when csr_marchid_c => -- R/-: marchid - arch ID
|
csr.rdata(4 downto 0) <= "10011"; -- official RISC-V open-source arch ID
|
csr.rdata(4 downto 0) <= "10011"; -- official RISC-V open-source arch ID
|
when csr_mimpid_c => -- R/-: mimpid - implementation ID
|
when csr_mimpid_c => -- R/-: mimpid - implementation ID
|
csr.rdata <= hw_version_c; -- NEORV32 hardware version
|
csr.rdata <= hw_version_c; -- NEORV32 hardware version
|
when csr_mhartid_c => -- R/-: mhartid - hardware thread ID
|
when csr_mhartid_c => -- R/-: mhartid - hardware thread ID
|
csr.rdata <= HW_THREAD_ID;
|
csr.rdata <= HW_THREAD_ID;
|
|
|
-- custom machine read-only CSRs --
|
-- custom machine read-only CSRs --
|
when csr_mzext_c => -- R/-: mzext - available Z* extensions
|
when csr_mzext_c => -- R/-: mzext - available Z* extensions
|
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
|
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
|
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
|
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
|
csr.rdata(2) <= bool_to_ulogic_f(PMP_USE); -- RISC-V physical memory protection
|
|
|
|
-- undefined/unavailable --
|
-- undefined/unavailable --
|
when others =>
|
when others =>
|
csr.rdata <= (others => '0'); -- not implemented
|
csr.rdata <= (others => '0'); -- not implemented
|
|
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process csr_read_access;
|
end process csr_read_access;
|
|
|
-- CSR read data output --
|
-- CSR read data output --
|
csr_rdata_o <= csr.rdata;
|
csr_rdata_o <= csr.rdata;
|
|
|
|
|
end neorv32_cpu_control_rtl;
|
end neorv32_cpu_control_rtl;
|
|
|