-- #################################################################################################
|
-- #################################################################################################
|
-- # << NEORV32 - CPU Co-Processor: MULDIV unit >> #
|
-- # << NEORV32 - CPU Co-Processor: MULDIV unit >> #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
|
-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
|
-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+8 cycles latency #
|
-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+8 cycles latency #
|
-- # Divider core (unsigned) uses serial algorithm. -> 32+8 cycles latency #
|
-- # Divider core (unsigned) uses serial algorithm. -> 32+8 cycles latency #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
|
-- # permitted provided that the following conditions are met: #
|
-- # #
|
-- # #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
-- # conditions and the following disclaimer. #
|
-- # conditions and the following disclaimer. #
|
-- # #
|
-- # #
|
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
-- # provided with the distribution. #
|
-- # provided with the distribution. #
|
-- # #
|
-- # #
|
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
-- # endorse or promote products derived from this software without specific prior written #
|
-- # endorse or promote products derived from this software without specific prior written #
|
-- # permission. #
|
-- # permission. #
|
-- # #
|
-- # #
|
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
-- #################################################################################################
|
-- #################################################################################################
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
|
|
|
entity neorv32_cpu_cp_muldiv is
|
entity neorv32_cpu_cp_muldiv is
|
port (
|
port (
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-- global control --
|
-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
|
-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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-- result and status --
|
-- result and status --
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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valid_o : out std_ulogic -- data output valid
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valid_o : out std_ulogic -- data output valid
|
);
|
);
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end neorv32_cpu_cp_muldiv;
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end neorv32_cpu_cp_muldiv;
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|
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
|
|
|
-- controller --
|
-- controller --
|
type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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signal state : state_t;
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signal state : state_t;
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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signal start : std_ulogic;
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signal start : std_ulogic;
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signal operation : std_ulogic;
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signal operation : std_ulogic;
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signal opx, opy : std_ulogic_vector(data_width_c-1 downto 0); -- input operands
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signal opx, opy : std_ulogic_vector(data_width_c-1 downto 0); -- input operands
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signal opx_is_signed : std_ulogic;
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signal opx_is_signed : std_ulogic;
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signal opy_is_signed : std_ulogic;
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signal opy_is_signed : std_ulogic;
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signal div_res_corr : std_ulogic;
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signal div_res_corr : std_ulogic;
|
|
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-- divider core --
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-- divider core --
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signal remainder : std_ulogic_vector(data_width_c-1 downto 0);
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signal remainder : std_ulogic_vector(data_width_c-1 downto 0);
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signal quotient : std_ulogic_vector(data_width_c-1 downto 0);
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signal quotient : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sub : std_ulogic_vector(data_width_c downto 0);
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signal div_sub : std_ulogic_vector(data_width_c downto 0);
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signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sign_comp : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sign_comp : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_res : std_ulogic_vector(data_width_c-1 downto 0);
|
|
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-- multiplier core --
|
-- multiplier core --
|
signal mul_product : std_ulogic_vector(63 downto 0);
|
signal mul_product : std_ulogic_vector(63 downto 0);
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signal mul_do_add : std_ulogic_vector(32 downto 0);
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signal mul_do_add : std_ulogic_vector(32 downto 0);
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signal mul_sign_cycle : std_ulogic;
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signal mul_sign_cycle : std_ulogic;
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signal mul_p_sext : std_ulogic;
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signal mul_p_sext : std_ulogic;
|
|
|
begin
|
begin
|
|
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-- Co-Processor Controller ----------------------------------------------------------------
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-- Co-Processor Controller ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
coprocessor_ctrl: process(rstn_i, clk_i)
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coprocessor_ctrl: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
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state <= IDLE;
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state <= IDLE;
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cp_op <= (others => '0');
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cp_op <= (others => '0');
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opx <= (others => '0');
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opx <= (others => '0');
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opy <= (others => '0');
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opy <= (others => '0');
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cnt <= (others => '0');
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cnt <= (others => '0');
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start <= '0';
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start <= '0';
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valid_o <= '0';
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valid_o <= '0';
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div_res_corr <= '0';
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div_res_corr <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- defaults --
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-- defaults --
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start <= '0';
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start <= '0';
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valid_o <= '0';
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valid_o <= '0';
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|
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-- FSM --
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-- FSM --
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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opx <= rs1_i;
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opx <= rs1_i;
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opy <= rs2_i;
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opy <= rs2_i;
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if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
|
|
cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
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cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
|
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if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
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state <= DECODE;
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state <= DECODE;
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end if;
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end if;
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|
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when DECODE =>
|
when DECODE =>
|
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cnt <= "11111";
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if (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) then -- result sign compensation for div?
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if (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) then -- result sign compensation for div?
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div_res_corr <= opx(opx'left) xor opy(opy'left);
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div_res_corr <= opx(opx'left) xor opy(opy'left);
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else
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else
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div_res_corr <= '0';
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div_res_corr <= '0';
|
end if;
|
end if;
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cnt <= "11111";
|
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if (operation = '1') then -- division
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if (operation = '1') then -- division
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state <= INIT_OPX;
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state <= INIT_OPX;
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else -- multiplication
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else -- multiplication
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start <= '1';
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start <= '1';
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state <= PROCESSING;
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state <= PROCESSING;
|
end if;
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end if;
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|
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when INIT_OPX =>
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when INIT_OPX =>
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if ((opx(opx'left) and opx_is_signed) = '1') then -- signed division?
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if ((opx(opx'left) and opx_is_signed) = '1') then -- signed division?
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opx <= div_sign_comp; -- make positive
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opx <= div_sign_comp; -- make positive
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end if;
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end if;
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state <= INIT_OPY;
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state <= INIT_OPY;
|
|
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when INIT_OPY =>
|
when INIT_OPY =>
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start <= '1';
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start <= '1';
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if ((opy(opy'left) and opy_is_signed) = '1') then -- signed division?
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if ((opy(opy'left) and opy_is_signed) = '1') then -- signed division?
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opy <= div_sign_comp; -- make positive
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opy <= div_sign_comp; -- make positive
|
end if;
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end if;
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state <= PROCESSING;
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state <= PROCESSING;
|
|
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when PROCESSING =>
|
when PROCESSING =>
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cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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if (cnt = "00000") then
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if (cnt = "00000") then
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state <= FINALIZE;
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state <= FINALIZE;
|
end if;
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end if;
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|
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when FINALIZE =>
|
when FINALIZE =>
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state <= COMPLETED;
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state <= COMPLETED;
|
|
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when COMPLETED =>
|
when COMPLETED =>
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valid_o <= '1';
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valid_o <= '1';
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state <= IDLE;
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state <= IDLE;
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end case;
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end case;
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end if;
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end if;
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end process coprocessor_ctrl;
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end process coprocessor_ctrl;
|
|
|
-- operation --
|
-- operation --
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operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0';
|
operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0';
|
|
|
-- opx (rs1) signed? --
|
-- opx (rs1) signed? --
|
opx_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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opx_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
|
|
|
-- opy (rs2) signed? --
|
-- opy (rs2) signed? --
|
opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
|
|
|
|
|
-- Multiplier Core ------------------------------------------------------------------------
|
-- Multiplier Core ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
multiplier_core: process(clk_i)
|
multiplier_core: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (start = '1') then -- start new multiplication
|
if (start = '1') then -- start new multiplication
|
mul_product(63 downto 32) <= (others => (opy(opy'left) and opy_is_signed)); -- sign extension
|
mul_product(63 downto 32) <= (others => (opy(opy'left) and opy_is_signed)); -- sign extension
|
mul_product(31 downto 00) <= opy;
|
mul_product(31 downto 00) <= opy;
|
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
|
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
|
mul_product(63 downto 31) <= mul_do_add(32 downto 0);
|
mul_product(63 downto 31) <= mul_do_add(32 downto 0);
|
mul_product(30 downto 00) <= mul_product(31 downto 1);
|
mul_product(30 downto 00) <= mul_product(31 downto 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process multiplier_core;
|
end process multiplier_core;
|
|
|
-- MUL: do another addition --
|
-- MUL: do another addition --
|
mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opy_is_signed, opx)
|
mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx)
|
begin
|
begin
|
if (mul_product(0) = '1') then
|
if (mul_product(0) = '1') then
|
if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
|
if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
|
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opy'left) and opx_is_signed) & opx));
|
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opy'left) and opx_is_signed) & opx));
|
else
|
else
|
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opy'left) and opx_is_signed) & opx));
|
mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opy'left) and opx_is_signed) & opx));
|
end if;
|
end if;
|
else
|
else
|
mul_do_add <= mul_p_sext & mul_product(63 downto 32);
|
mul_do_add <= mul_p_sext & mul_product(63 downto 32);
|
end if;
|
end if;
|
end process mul_update;
|
end process mul_update;
|
|
|
-- sign control --
|
-- sign control --
|
mul_sign_cycle <= opy_is_signed when (state = FINALIZE) else '0';
|
mul_sign_cycle <= opy_is_signed when (state = FINALIZE) else '0';
|
mul_p_sext <= mul_product(mul_product'left) and opx_is_signed;
|
mul_p_sext <= mul_product(mul_product'left) and opx_is_signed;
|
|
|
|
|
-- Divider Core ---------------------------------------------------------------------------
|
-- Divider Core ---------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
divider_core: process(clk_i)
|
divider_core: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (start = '1') then -- start new division
|
if (start = '1') then -- start new division
|
quotient <= opx;
|
quotient <= opx;
|
remainder <= (others => '0');
|
remainder <= (others => '0');
|
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '1') then -- running?
|
elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '1') then -- running?
|
quotient <= quotient(30 downto 0) & (not div_sub(32));
|
quotient <= quotient(30 downto 0) & (not div_sub(32));
|
if (div_sub(32) = '0') then -- still overflowing
|
if (div_sub(32) = '0') then -- still overflowing
|
remainder <= div_sub(31 downto 0);
|
remainder <= div_sub(31 downto 0);
|
else -- underflow
|
else -- underflow
|
remainder <= remainder(30 downto 0) & quotient(31);
|
remainder <= remainder(30 downto 0) & quotient(31);
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process divider_core;
|
end process divider_core;
|
|
|
-- DIV: try another subtraction --
|
-- DIV: try another subtraction --
|
div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & opy));
|
div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & opy));
|
|
|
-- Div sign compensation --
|
-- Div sign compensation --
|
div_sign_comp_in <= opx when (state = INIT_OPX) else
|
div_sign_comp_in <= opx when (state = INIT_OPX) else
|
opy when (state = INIT_OPY) else
|
opy when (state = INIT_OPY) else
|
quotient when ((cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c)) else remainder;
|
quotient when ((cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c)) else remainder;
|
div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
|
div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
|
|
|
-- result sign correction --
|
-- result sign correction --
|
div_res <= div_sign_comp when (div_res_corr = '1') else div_sign_comp_in;
|
div_res <= div_sign_comp when (div_res_corr = '1') else div_sign_comp_in;
|
|
|
|
|
-- Data Output ----------------------------------------------------------------------------
|
-- Data Output ----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
operation_result: process(clk_i)
|
operation_result: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
case cp_op is
|
case cp_op is
|
when cp_op_mul_c =>
|
when cp_op_mul_c =>
|
res_o <= mul_product(31 downto 00);
|
res_o <= mul_product(31 downto 00);
|
when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
|
when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
|
res_o <= mul_product(63 downto 32);
|
res_o <= mul_product(63 downto 32);
|
when cp_op_div_c =>
|
when cp_op_div_c =>
|
res_o <= div_res;
|
res_o <= div_res;
|
when cp_op_divu_c =>
|
when cp_op_divu_c =>
|
res_o <= quotient;
|
res_o <= quotient;
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when cp_op_rem_c =>
|
when cp_op_rem_c =>
|
res_o <= div_res;
|
res_o <= div_res;
|
when cp_op_remu_c =>
|
when cp_op_remu_c =>
|
res_o <= remainder;
|
res_o <= remainder;
|
when others => -- undefined
|
when others => -- undefined
|
res_o <= (others => '0');
|
res_o <= (others => '0');
|
end case;
|
end case;
|
end if;
|
end if;
|
end process operation_result;
|
end process operation_result;
|
|
|
|
|
end neorv32_cpu_cp_muldiv_rtl;
|
end neorv32_cpu_cp_muldiv_rtl;
|
|
|