-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU General Purpose Data Register File >> #
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-- # << NEORV32 - CPU General Purpose Data Register File >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # General purpose data register file. 32 entries (= 1024 bit) for normal mode (RV32I), #
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-- # General purpose data register file. 32 entries (= 1024 bit) for normal mode (RV32I), #
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-- # 16 entries (= 512 bit) for embedded mode (RV32E) when RISC-V "E" extension is enabled. #
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-- # 16 entries (= 512 bit) for embedded mode (RV32E) when RISC-V "E" extension is enabled. #
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-- # #
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-- # #
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-- # Register zero (r0/x0) is a "normal" physical reg that has to be initialized to zero by the #
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-- # Register zero (r0/x0) is a "normal" physical register that has to be initialized to zero by #
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-- # CPU control system. For normal operations register zero cannot be written. #
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-- # the early boot code. Register zero is always set to zero when written. #
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-- # #
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-- # #
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-- # The register file uses synchronous read accesses and a *single* (multiplexed) address port #
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-- # The register file uses synchronous read accesses and a *single* (multiplexed) address port #
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-- # for writing and reading rs1 and a single read-only port for rs2. Therefore, the whole #
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-- # for writing and reading rd/rs1 and a single read-only port for rs2. Therefore, the whole #
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-- # register file can be mapped to a single true dual-port block RAM. #
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-- # register file can be mapped to a single true-dual-port block RAM. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_regfile is
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entity neorv32_cpu_regfile is
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generic (
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generic (
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CPU_EXTENSION_RISCV_E : boolean -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean -- implement embedded RF extension?
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- data output --
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-- data output --
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
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cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status
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);
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);
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end neorv32_cpu_regfile;
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end neorv32_cpu_regfile;
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architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
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architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
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-- register file --
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-- register file --
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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signal reg_file : reg_file_t;
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signal reg_file : reg_file_t;
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signal reg_file_emb : reg_file_emb_t;
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signal reg_file_emb : reg_file_emb_t;
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signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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begin
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begin
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-- Data Input Mux -------------------------------------------------------------------------
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-- Data Input Mux -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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input_mux: process(rd_is_r0, ctrl_i, alu_i, mem_i)
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input_mux: process(rd_is_r0, ctrl_i, alu_i, mem_i)
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begin
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begin
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if (rd_is_r0 = '1') then -- write zero if accessing x0 to "emulate" it is hardwired to zero
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if (rd_is_r0 = '1') then -- write zero if accessing x0 to "emulate" it is hardwired to zero
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rf_wdata <= (others => '0');
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rf_wdata <= (others => '0');
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else
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else
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if (ctrl_i(ctrl_rf_in_mux_c) = '0') then
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if (ctrl_i(ctrl_rf_in_mux_c) = '0') then
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rf_wdata <= alu_i;
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rf_wdata <= alu_i;
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else
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else
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rf_wdata <= mem_i;
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rf_wdata <= mem_i;
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end if;
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end if;
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end if;
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end if;
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end process input_mux;
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end process input_mux;
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-- check if we are writing to x0 --
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-- check if we are writing to x0 --
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rd_is_r0 <= (not or_reduce_f(dst_addr(4 downto 0))) when (CPU_EXTENSION_RISCV_E = false) else (not or_reduce_f(dst_addr(3 downto 0)));
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rd_is_r0 <= (not or_reduce_f(dst_addr(4 downto 0))) when (CPU_EXTENSION_RISCV_E = false) else (not or_reduce_f(dst_addr(3 downto 0)));
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-- Register File Access -------------------------------------------------------------------
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-- Register File Access -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_access: process(clk_i)
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rf_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- sync read and write
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if rising_edge(clk_i) then -- sync read and write
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_wdata;
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_wdata;
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end if;
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end if;
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rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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else -- embedded register file with 16 entries
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else -- embedded register file with 16 entries
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_wdata;
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_wdata;
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end if;
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end if;
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rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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end if;
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end if;
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end if;
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end if;
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end process rf_access;
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end process rf_access;
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-- access addresses --
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-- access addresses --
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c);
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c);
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opa_addr <= dst_addr when (ctrl_i(ctrl_rf_wb_en_c) = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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opa_addr <= dst_addr when (ctrl_i(ctrl_rf_wb_en_c) = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
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opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
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-- data output --
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-- data output --
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rs1_o <= rs1;
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rs1_o <= rs1;
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rs2_o <= rs2;
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rs2_o <= rs2;
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-- Comparator Unit (for conditional branches) ---------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_opx <= (rs1(rs1'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1;
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cmp_opy <= (rs2(rs2'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2;
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cmp_o(cmp_equal_c) <= '1' when (rs1 = rs2) else '0';
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cmp_o(cmp_less_c) <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0';
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end neorv32_cpu_regfile_rtl;
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end neorv32_cpu_regfile_rtl;
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