-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - General Purpose Timer (GPTMR) >> #
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-- # << NEORV32 - General Purpose Timer (GPTMR) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # 32-bit timer with configurable clock prescaler. The timer fires an interrupt whenever the #
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-- # 32-bit timer with configurable clock prescaler. The timer fires an interrupt whenever the #
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-- # counter register value reaches the programmed threshold value. The timer can operate in #
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-- # counter register value reaches the programmed threshold value. The timer can operate in #
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-- # single-shot mode (count until it reaches THRESHOLD and stop) or in continuous mode (count #
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-- # single-shot mode (count until it reaches THRESHOLD and stop) or in continuous mode (count #
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-- # until it reaches THRESHOLD and auto-reset). #
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-- # until it reaches THRESHOLD and auto-reset). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_gptmr is
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entity neorv32_gptmr is
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- interrupt --
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-- interrupt --
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irq_o : out std_ulogic -- transmission done interrupt
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irq_o : out std_ulogic -- transmission done interrupt
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);
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);
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end neorv32_gptmr;
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end neorv32_gptmr;
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architecture neorv32_gptmr_rtl of neorv32_gptmr is
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architecture neorv32_gptmr_rtl of neorv32_gptmr is
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-- IO space: module base address --
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(gptmr_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(gptmr_size_c); -- low address boundary bit
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-- control register --
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-- control register --
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constant ctrl_en_c : natural := 0; -- r/w: timer enable
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constant ctrl_en_c : natural := 0; -- r/w: timer enable
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constant ctrl_prsc0_c : natural := 1; -- r/w: clock prescaler select bit 0
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constant ctrl_prsc0_c : natural := 1; -- r/w: clock prescaler select bit 0
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constant ctrl_prsc1_c : natural := 2; -- r/w: clock prescaler select bit 1
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constant ctrl_prsc1_c : natural := 2; -- r/w: clock prescaler select bit 1
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constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler select bit 2
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constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler select bit 2
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constant ctrl_mode_c : natural := 4; -- r/w: mode (0=single-shot, 1=continuous)
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constant ctrl_mode_c : natural := 4; -- r/w: mode (0=single-shot, 1=continuous)
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constant ctrl_alarm_c : natural := 5; -- r/c: alarm flag (interrupt), cleared by writing zero
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constant ctrl_alarm_c : natural := 5; -- r/c: alarm flag (interrupt), cleared by writing zero
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--
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--
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signal ctrl : std_ulogic_vector(4 downto 0);
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signal ctrl : std_ulogic_vector(4 downto 0);
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- word write enable
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signal wren : std_ulogic; -- word write enable
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signal rden : std_ulogic; -- read enable
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signal rden : std_ulogic; -- read enable
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-- clock generator --
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-- clock generator --
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signal gptmr_clk_en : std_ulogic;
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signal gptmr_clk_en : std_ulogic;
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-- timer core --
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-- timer core --
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type timer_t is record
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type timer_t is record
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count : std_ulogic_vector(31 downto 0); -- counter register
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count : std_ulogic_vector(31 downto 0); -- counter register
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thres : std_ulogic_vector(31 downto 0); -- threshold value
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thres : std_ulogic_vector(31 downto 0); -- threshold value
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match : std_ulogic; -- count == thres
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match : std_ulogic; -- count == thres
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cnt_we : std_ulogic; -- write access to count
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cnt_we : std_ulogic; -- write access to count
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end record;
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end record;
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signal timer : timer_t;
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signal timer : timer_t;
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-- interrupt generator --
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-- interrupt generator --
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type irq_t is record
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type irq_t is record
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pending : std_ulogic; -- pending interrupt request
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pending : std_ulogic; -- pending interrupt request
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detect : std_ulogic_vector(1 downto 0); -- rising-edge detector
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detect : std_ulogic_vector(1 downto 0); -- rising-edge detector
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clearn : std_ulogic; -- clear/ack IRQ request, active-low
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clearn : std_ulogic; -- clear/ack IRQ request, active-low
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end record;
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end record;
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signal irq : irq_t;
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signal irq : irq_t;
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begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gptmr_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gptmr_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= gptmr_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= gptmr_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i;
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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rden <= acc_en and rden_i;
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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rw_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- bus access acknowledge --
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-- bus access acknowledge --
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ack_o <= rden or wren;
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ack_o <= rden or wren;
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-- write access --
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-- write access --
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irq.clearn <= '1';
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irq.clearn <= '1';
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timer.cnt_we <= '0';
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timer.cnt_we <= '0';
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if (wren = '1') then
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if (wren = '1') then
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if (addr = gptmr_ctrl_addr_c) then -- control register
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if (addr = gptmr_ctrl_addr_c) then -- control register
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ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
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ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
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ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c);
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ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c);
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ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
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ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
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ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
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ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
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ctrl(ctrl_mode_c) <= data_i(ctrl_mode_c);
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ctrl(ctrl_mode_c) <= data_i(ctrl_mode_c);
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irq.clearn <= data_i(ctrl_alarm_c);
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irq.clearn <= data_i(ctrl_alarm_c);
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end if;
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end if;
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if (addr = gptmr_thres_addr_c) then -- threshold register
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if (addr = gptmr_thres_addr_c) then -- threshold register
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timer.thres <= data_i;
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timer.thres <= data_i;
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end if;
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end if;
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if (addr = gptmr_count_addr_c) then -- counter register
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if (addr = gptmr_count_addr_c) then -- counter register
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timer.cnt_we <= '1';
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timer.cnt_we <= '1';
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rden = '1') then
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if (rden = '1') then
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case addr(3 downto 2) is
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case addr(3 downto 2) is
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when "00" => -- control register
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when "00" => -- control register
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data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
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data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
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data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
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data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
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data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
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data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
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data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
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data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
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data_o(ctrl_mode_c) <= ctrl(ctrl_mode_c);
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data_o(ctrl_mode_c) <= ctrl(ctrl_mode_c);
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data_o(ctrl_alarm_c) <= irq.pending;
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data_o(ctrl_alarm_c) <= irq.pending;
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when "01" => -- threshold register
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when "01" => -- threshold register
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data_o <= timer.thres;
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data_o <= timer.thres;
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when others => -- counter register
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when others => -- counter register
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data_o <= timer.count;
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data_o <= timer.count;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process rw_access;
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end process rw_access;
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-- clock generator enable --
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-- clock generator enable --
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clkgen_en_o <= ctrl(ctrl_en_c);
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clkgen_en_o <= ctrl(ctrl_en_c);
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-- clock select --
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-- clock select --
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gptmr_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c))));
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gptmr_clk_en <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c))));
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-- Timer Core -----------------------------------------------------------------------------
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-- Timer Core -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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timer_core: process(clk_i)
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timer_core: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (timer.cnt_we = '1') then -- write access
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if (timer.cnt_we = '1') then -- write access
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timer.count <= data_i;
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timer.count <= data_i;
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elsif (ctrl(ctrl_en_c) = '1') then -- enabled
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elsif (ctrl(ctrl_en_c) = '1') and (gptmr_clk_en = '1') then -- enabled and clock tick
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if (timer.match = '1') then
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if (timer.match = '1') then
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if (ctrl(ctrl_mode_c) = '1') then -- reset counter if continuous mode
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if (ctrl(ctrl_mode_c) = '1') then -- reset counter if continuous mode
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timer.count <= (others => '0');
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timer.count <= (others => '0');
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end if;
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end if;
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else
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else
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timer.count <= std_ulogic_vector(unsigned(timer.count) + 1);
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timer.count <= std_ulogic_vector(unsigned(timer.count) + 1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process timer_core;
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end process timer_core;
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-- counter = threshold? --
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-- counter = threshold? --
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timer.match <= '1' when (timer.count = timer.thres) else '0';
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timer.match <= '1' when (timer.count = timer.thres) else '0';
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-- Interrupt Generator --------------------------------------------------------------------
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-- Interrupt Generator --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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irq_generator: process(clk_i)
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irq_generator: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (ctrl(ctrl_en_c) = '0') then
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if (ctrl(ctrl_en_c) = '0') then
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irq.detect <= "00";
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irq.detect <= "00";
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irq.pending <= '0';
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irq.pending <= '0';
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else
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else
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irq.detect <= irq.detect(0) & timer.match;
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irq.detect <= irq.detect(0) & timer.match;
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if (irq.detect = "01") then -- rising edge
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if (irq.detect = "01") then -- rising edge
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irq.pending <= '1';
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irq.pending <= '1';
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elsif (irq.clearn = '0') then
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elsif (irq.clearn = '0') then
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irq.pending <= '0';
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irq.pending <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process irq_generator;
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end process irq_generator;
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-- IRQ request to CPU --
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-- IRQ request to CPU --
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irq_o <= irq.pending;
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irq_o <= irq.pending;
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end neorv32_gptmr_rtl;
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end neorv32_gptmr_rtl;
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