-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Machine System Timer (MTIME) >> #
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-- # << NEORV32 - Machine System Timer (MTIME) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Compatible to RISC-V spec's mtime & mtimecmp. #
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-- # Compatible to RISC-V spec's mtime & mtimecmp. #
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-- # Write mtime.LO first when updating the system time. System time should be written only at #
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-- # Write mtime.LO first when updating the system time. System time should be written only at #
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-- # system start. RISC-V spec. exception: The MTIME interrupt is ACKed by the processor itself. #
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-- # system start. RISC-V spec. exception: The MTIME interrupt is ACKed by the processor itself. #
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-- # However, the achine time cannot issue a new interrupt until the mtimecmp.HI register is #
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-- # However, the achine time cannot issue a new interrupt until the mtimecmp.HI register is #
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-- # written again. #
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-- # written again. #
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-- # Note: The 64-bit time and compare system is broken and de-coupled into two 32-bit systems. #
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-- # Note: The 64-bit time and compare system is broken and de-coupled into two 32-bit systems. #
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-- # Note: The register of this unit can only be written in WORD MODE. #
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-- # Note: The register of this unit can only be written in WORD MODE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
-- # endorse or promote products derived from this software without specific prior written #
|
-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_mtime is
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entity neorv32_mtime is
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- time output for CPU --
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-- time output for CPU --
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time_o : out std_ulogic_vector(63 downto 0); -- current system time
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time_o : out std_ulogic_vector(63 downto 0); -- current system time
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-- interrupt --
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-- interrupt --
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irq_o : out std_ulogic -- interrupt request
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irq_o : out std_ulogic -- interrupt request
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);
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);
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end neorv32_mtime;
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end neorv32_mtime;
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|
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architecture neorv32_mtime_rtl of neorv32_mtime is
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architecture neorv32_mtime_rtl of neorv32_mtime is
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|
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-- IO space: module base address --
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(mtime_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(mtime_size_c); -- low address boundary bit
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|
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- module access enable
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signal wren : std_ulogic; -- module access enable
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|
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-- accessible regs --
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-- accessible regs --
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signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtime_lo : std_ulogic_vector(32 downto 0);
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signal mtime_lo : std_ulogic_vector(32 downto 0);
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signal mtime_lo_msb_ff : std_ulogic;
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signal mtime_lo_msb_ff : std_ulogic;
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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|
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-- irq control --
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-- irq control --
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signal cmp_lo : std_ulogic;
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signal cmp_lo : std_ulogic;
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signal cmp_lo_ff : std_ulogic;
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signal cmp_lo_ff : std_ulogic;
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signal cmp_hi : std_ulogic;
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signal cmp_hi : std_ulogic;
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signal cmp_match_ff : std_ulogic;
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signal cmp_match_ff : std_ulogic;
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|
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begin
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begin
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|
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i and and_all_f(ben_i);
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wren <= acc_en and wren_i;
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|
|
|
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-- Write Access ---------------------------------------------------------------------------
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-- Write Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wr_access: process(clk_i)
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wr_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- mtimecmp --
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-- mtimecmp --
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if (wren = '1') then
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if (wren = '1') then
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if (addr = mtime_cmp_lo_addr_c) then -- low
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if (addr = mtime_cmp_lo_addr_c) then -- low
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mtimecmp_lo <= data_i;
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mtimecmp_lo <= data_i;
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end if;
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end if;
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if (addr = mtime_cmp_hi_addr_c) then -- high
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if (addr = mtime_cmp_hi_addr_c) then -- high
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mtimecmp_hi <= data_i;
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mtimecmp_hi <= data_i;
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end if;
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end if;
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end if;
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end if;
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|
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-- mtime low --
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-- mtime low --
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if (wren = '1') and (addr = mtime_time_lo_addr_c) then
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if (wren = '1') and (addr = mtime_time_lo_addr_c) then
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mtime_lo_msb_ff <= '0';
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mtime_lo_msb_ff <= '0';
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mtime_lo <= '0' & data_i;
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mtime_lo <= '0' & data_i;
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else -- auto increment
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else -- auto increment
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mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
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mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
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mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
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mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
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end if;
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end if;
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|
|
-- mtime high --
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-- mtime high --
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if (wren = '1') and (addr = mtime_time_hi_addr_c) then
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if (wren = '1') and (addr = mtime_time_hi_addr_c) then
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mtime_hi <= data_i;
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mtime_hi <= data_i;
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elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
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elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
|
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
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end if;
|
end if;
|
end if;
|
end if;
|
end process wr_access;
|
end process wr_access;
|
|
|
|
|
-- Read Access ----------------------------------------------------------------------------
|
-- Read Access ----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
rd_access: process(clk_i)
|
rd_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
ack_o <= acc_en and (rden_i or wren_i);
|
ack_o <= acc_en and (rden_i or wren_i);
|
data_o <= (others => '0'); -- default
|
data_o <= (others => '0'); -- default
|
if (rden_i = '1') and (acc_en = '1') then
|
if (rden_i = '1') and (acc_en = '1') then
|
if (addr = mtime_time_lo_addr_c) then -- mtime LOW
|
if (addr = mtime_time_lo_addr_c) then -- mtime LOW
|
data_o <= mtime_lo(31 downto 00);
|
data_o <= mtime_lo(31 downto 00);
|
elsif (addr = mtime_time_hi_addr_c) then -- mtime HIGH
|
elsif (addr = mtime_time_hi_addr_c) then -- mtime HIGH
|
data_o <= mtime_hi;
|
data_o <= mtime_hi;
|
elsif (addr = mtime_cmp_lo_addr_c) then -- mtimecmp LOW
|
elsif (addr = mtime_cmp_lo_addr_c) then -- mtimecmp LOW
|
data_o <= mtimecmp_lo;
|
data_o <= mtimecmp_lo;
|
else -- (addr = mtime_cmp_hi_addr_c) then -- mtimecmp HIGH
|
else -- (addr = mtime_cmp_hi_addr_c) then -- mtimecmp HIGH
|
data_o <= mtimecmp_hi;
|
data_o <= mtimecmp_hi;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process rd_access;
|
end process rd_access;
|
|
|
-- time output for cpu --
|
-- time output for cpu --
|
time_o <= mtime_hi & mtime_lo(31 downto 00);
|
time_o <= mtime_hi & mtime_lo(31 downto 00);
|
|
|
|
|
-- Comparator -----------------------------------------------------------------------------
|
-- Comparator -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
cmp_sync: process(clk_i)
|
cmp_sync: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
cmp_lo_ff <= cmp_lo;
|
cmp_lo_ff <= cmp_lo;
|
cmp_match_ff <= cmp_lo_ff and cmp_hi;
|
cmp_match_ff <= cmp_lo_ff and cmp_hi;
|
irq_o <= cmp_lo_ff and cmp_hi and (not cmp_match_ff);
|
irq_o <= cmp_lo_ff and cmp_hi and (not cmp_match_ff);
|
end if;
|
end if;
|
end process cmp_sync;
|
end process cmp_sync;
|
|
|
-- test words --
|
-- test words --
|
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp_lo)) else '0';
|
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp_lo)) else '0';
|
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp_hi)) else '0';
|
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp_hi)) else '0';
|
|
|
|
|
end neorv32_mtime_rtl;
|
end neorv32_mtime_rtl;
|
|
|