-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Main VHDL package file >> #
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-- # << NEORV32 - Main VHDL package file >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000600"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01020005"; -- no touchy!
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-- Internal Functions ---------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function index_size_f(input : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
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function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
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function bool_to_ulogic_f(cond : boolean) return std_ulogic;
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function bool_to_ulogic_f(cond : boolean) return std_ulogic;
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function or_all_f( a : std_ulogic_vector) return std_ulogic;
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function or_all_f( a : std_ulogic_vector) return std_ulogic;
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function and_all_f( a : std_ulogic_vector) return std_ulogic;
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function and_all_f( a : std_ulogic_vector) return std_ulogic;
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function xor_all_f( a : std_ulogic_vector) return std_ulogic;
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function xor_all_f( a : std_ulogic_vector) return std_ulogic;
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
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function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
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function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
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-- Processor-internal Address Space Layout ------------------------------------------------
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-- Processor-internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Instruction Memory & Data Memory --
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-- Instruction Memory & Data Memory --
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-- => configured via top's generics
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-- => configured via top's generics
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-- Bootloader ROM --
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-- Bootloader ROM --
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constant boot_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_size_c : natural := 4*1024; -- bytes
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constant boot_size_c : natural := 4*1024; -- bytes
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constant boot_max_size_c : natural := 32*1024; -- bytes, fixed!
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constant boot_max_size_c : natural := 32*1024; -- bytes, fixed!
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-- IO: Peripheral Devices ("IO") Area --
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-- IO: Peripheral Devices ("IO") Area --
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-- Control register(s) (including the device-enable) should be located at the base address of each device
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-- Control register(s) (including the device-enable) should be located at the base address of each device
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constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
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constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
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constant io_size_c : natural := 32*4; -- bytes, fixed!
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constant io_size_c : natural := 32*4; -- bytes, fixed!
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-- General Purpose Input/Output Unit (GPIO) --
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-- General Purpose Input/Output Unit (GPIO) --
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constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
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constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
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constant gpio_size_c : natural := 2*4; -- bytes, fixed!
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constant gpio_size_c : natural := 2*4; -- bytes, fixed!
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constant gpio_in_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000000");
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constant gpio_in_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000000");
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constant gpio_out_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000004");
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constant gpio_out_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"00000004");
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-- Core-Local Interrupt Controller (CLIC) --
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-- Core-Local Interrupt Controller (CLIC) --
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constant clic_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
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constant clic_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
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constant clic_size_c : natural := 1*4; -- bytes, fixed!
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constant clic_size_c : natural := 1*4; -- bytes, fixed!
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constant clic_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(clic_base_c) + x"00000000");
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constant clic_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(clic_base_c) + x"00000000");
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-- Watch Dog Timer (WDT) --
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-- Watch Dog Timer (WDT) --
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constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
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constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
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constant wdt_size_c : natural := 1*4; -- bytes, fixed!
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constant wdt_size_c : natural := 1*4; -- bytes, fixed!
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constant wdt_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(wdt_base_c) + x"00000000");
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constant wdt_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(wdt_base_c) + x"00000000");
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-- Machine System Timer (MTIME) --
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-- Machine System Timer (MTIME) --
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constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address, fixed!
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constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address, fixed!
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constant mtime_size_c : natural := 4*4; -- bytes, fixed!
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constant mtime_size_c : natural := 4*4; -- bytes, fixed!
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constant mtime_time_lo_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000000");
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constant mtime_time_lo_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000000");
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constant mtime_time_hi_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000004");
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constant mtime_time_hi_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000004");
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constant mtime_cmp_lo_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000008");
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constant mtime_cmp_lo_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"00000008");
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constant mtime_cmp_hi_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"0000000C");
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constant mtime_cmp_hi_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(mtime_base_c) + x"0000000C");
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-- Universal Asynchronous Receiver/Transmitter (UART) --
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-- Universal Asynchronous Receiver/Transmitter (UART) --
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constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address, fixed!
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constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address, fixed!
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constant uart_size_c : natural := 2*4; -- bytes, fixed!
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constant uart_size_c : natural := 2*4; -- bytes, fixed!
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constant uart_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"00000000");
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constant uart_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"00000000");
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constant uart_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"00000004");
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constant uart_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"00000004");
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-- Serial Peripheral Interface (SPI) --
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-- Serial Peripheral Interface (SPI) --
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constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address, fixed!
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constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address, fixed!
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constant spi_size_c : natural := 2*4; -- bytes, fixed!
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constant spi_size_c : natural := 2*4; -- bytes, fixed!
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constant spi_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"00000000");
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constant spi_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"00000000");
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constant spi_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"00000004");
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constant spi_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"00000004");
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-- Two Wire Interface (TWI) --
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-- Two Wire Interface (TWI) --
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constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address, fixed!
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constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address, fixed!
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constant twi_size_c : natural := 2*4; -- bytes, fixed!
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constant twi_size_c : natural := 2*4; -- bytes, fixed!
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constant twi_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"00000000");
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constant twi_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"00000000");
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constant twi_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"00000004");
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constant twi_rtx_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"00000004");
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-- Pulse-Width Modulation Controller (PWM) --
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-- Pulse-Width Modulation Controller (PWM) --
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constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
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constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
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constant pwm_size_c : natural := 2*4; -- bytes, fixed!
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constant pwm_size_c : natural := 2*4; -- bytes, fixed!
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constant pwm_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000000");
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constant pwm_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000000");
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constant pwm_duty_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000004");
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constant pwm_duty_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"00000004");
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-- True Random Number generator (TRNG) --
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-- True Random Number generator (TRNG) --
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constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
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constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
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constant trng_size_c : natural := 2*4; -- bytes, fixed!
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constant trng_size_c : natural := 2*4; -- bytes, fixed!
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constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");
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constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");
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constant trng_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000004");
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constant trng_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000004");
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-- RESERVED --
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-- Dummy Device (with SIMULATION output) (DEVNULL) --
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--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed!
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constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed!
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--constant ???_size_c : natural := 13*4; -- bytes, fixed!
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-- Dummy Device (with SIM output) (DEVNULL) --
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constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFFC"; -- base address, fixed!
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constant devnull_size_c : natural := 1*4; -- bytes, fixed!
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constant devnull_size_c : natural := 1*4; -- bytes, fixed!
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constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000");
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constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000");
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-- RESERVED --
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--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC"; -- base address, fixed!
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--constant ???_size_c : natural := 5*4; -- bytes, fixed!
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-- System Information Memory (with SIMULATION output) (SYSINFO) --
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constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
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constant sysinfo_size_c : natural := 8*4; -- bytes, fixed!
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-- Main Control Bus -----------------------------------------------------------------------
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-- Main Control Bus -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- register file --
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-- register file --
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constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM)
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constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM)
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constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR)
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constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR)
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constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0
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constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0
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constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1
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constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1
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constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2
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constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2
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constant ctrl_rf_rs1_adr3_c : natural := 5; -- source register 1 address bit 3
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constant ctrl_rf_rs1_adr3_c : natural := 5; -- source register 1 address bit 3
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constant ctrl_rf_rs1_adr4_c : natural := 6; -- source register 1 address bit 4
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constant ctrl_rf_rs1_adr4_c : natural := 6; -- source register 1 address bit 4
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constant ctrl_rf_rs2_adr0_c : natural := 7; -- source register 2 address bit 0
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constant ctrl_rf_rs2_adr0_c : natural := 7; -- source register 2 address bit 0
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constant ctrl_rf_rs2_adr1_c : natural := 8; -- source register 2 address bit 1
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constant ctrl_rf_rs2_adr1_c : natural := 8; -- source register 2 address bit 1
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constant ctrl_rf_rs2_adr2_c : natural := 9; -- source register 2 address bit 2
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constant ctrl_rf_rs2_adr2_c : natural := 9; -- source register 2 address bit 2
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constant ctrl_rf_rs2_adr3_c : natural := 10; -- source register 2 address bit 3
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constant ctrl_rf_rs2_adr3_c : natural := 10; -- source register 2 address bit 3
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constant ctrl_rf_rs2_adr4_c : natural := 11; -- source register 2 address bit 4
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constant ctrl_rf_rs2_adr4_c : natural := 11; -- source register 2 address bit 4
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constant ctrl_rf_rd_adr0_c : natural := 12; -- destiantion register address bit 0
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constant ctrl_rf_rd_adr0_c : natural := 12; -- destiantion register address bit 0
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constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1
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constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1
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constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2
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constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2
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constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
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constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3
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constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
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constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4
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constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
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constant ctrl_rf_wb_en_c : natural := 17; -- write back enable
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constant ctrl_rf_clear_rs1_c : natural := 18; -- force rs1=r0
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constant ctrl_rf_clear_rs1_c : natural := 18; -- force rs1=r0
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constant ctrl_rf_clear_rs2_c : natural := 19; -- force rs2=r0
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constant ctrl_rf_clear_rs2_c : natural := 19; -- force rs2=r0
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-- alu --
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-- alu --
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constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
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constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
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constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
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constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
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constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
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constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
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constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
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constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
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constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (10=CSR, 11=?)
|
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (1-=CSR)
|
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
|
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
|
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (10=rs1, 11=?)
|
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (1-=rs1)
|
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
|
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
|
constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
|
constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
|
constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
|
constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
|
-- bus interface --
|
-- bus interface --
|
constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_rd_c : natural := 33; -- read data request
|
constant ctrl_bus_rd_c : natural := 33; -- read data request
|
constant ctrl_bus_wr_c : natural := 34; -- write data request
|
constant ctrl_bus_wr_c : natural := 34; -- write data request
|
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
|
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request
|
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
|
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
|
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
|
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
|
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
|
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
|
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
|
constant ctrl_bus_exc_ack_c : natural := 40; -- acknowledge bus exception
|
constant ctrl_bus_ierr_ack_c : natural := 40; -- acknowledge instruction fetch bus exception
|
constant ctrl_bus_reset_c : natural := 41; -- reset bus unit, terminate all actions
|
constant ctrl_bus_derr_ack_c : natural := 41; -- acknowledge data access bus exception
|
|
constant ctrl_bus_fence_c : natural := 42; -- executed fence operation
|
|
constant ctrl_bus_fencei_c : natural := 43; -- executed fencei operation
|
-- co-processor --
|
-- co-processor --
|
constant ctrl_cp_use_c : natural := 42; -- is cp operation
|
constant ctrl_cp_use_c : natural := 44; -- is cp operation
|
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select lsb
|
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select lsb
|
constant ctrl_cp_id_msb_c : natural := 44; -- cp select msb
|
constant ctrl_cp_id_msb_c : natural := 46; -- cp select msb
|
constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0
|
constant ctrl_cp_cmd0_c : natural := 47; -- cp command bit 0
|
constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1
|
constant ctrl_cp_cmd1_c : natural := 48; -- cp command bit 1
|
constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2
|
constant ctrl_cp_cmd2_c : natural := 49; -- cp command bit 2
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 48; -- control bus size
|
constant ctrl_width_c : natural := 50; -- control bus size
|
|
|
-- ALU Comparator Bus ---------------------------------------------------------------------
|
-- ALU Comparator Bus ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant alu_cmp_equal_c : natural := 0;
|
constant alu_cmp_equal_c : natural := 0;
|
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
|
|
-- RISC-V Opcode Layout -------------------------------------------------------------------
|
-- RISC-V Opcode Layout -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
|
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
|
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
|
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
|
constant instr_rd_lsb_c : natural := 7; -- destination register address bit 0
|
constant instr_rd_lsb_c : natural := 7; -- destination register address bit 0
|
constant instr_rd_msb_c : natural := 11; -- destination register address bit 4
|
constant instr_rd_msb_c : natural := 11; -- destination register address bit 4
|
constant instr_funct3_lsb_c : natural := 12; -- funct3 bit 0
|
constant instr_funct3_lsb_c : natural := 12; -- funct3 bit 0
|
constant instr_funct3_msb_c : natural := 14; -- funct3 bit 2
|
constant instr_funct3_msb_c : natural := 14; -- funct3 bit 2
|
constant instr_rs1_lsb_c : natural := 15; -- source register 1 address bit 0
|
constant instr_rs1_lsb_c : natural := 15; -- source register 1 address bit 0
|
constant instr_rs1_msb_c : natural := 19; -- source register 1 address bit 4
|
constant instr_rs1_msb_c : natural := 19; -- source register 1 address bit 4
|
constant instr_rs2_lsb_c : natural := 20; -- source register 2 address bit 0
|
constant instr_rs2_lsb_c : natural := 20; -- source register 2 address bit 0
|
constant instr_rs2_msb_c : natural := 24; -- source register 2 address bit 4
|
constant instr_rs2_msb_c : natural := 24; -- source register 2 address bit 4
|
constant instr_funct7_lsb_c : natural := 25; -- funct7 bit 0
|
constant instr_funct7_lsb_c : natural := 25; -- funct7 bit 0
|
constant instr_funct7_msb_c : natural := 31; -- funct7 bit 6
|
constant instr_funct7_msb_c : natural := 31; -- funct7 bit 6
|
constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
|
constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
|
constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
|
constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
|
constant instr_imm12_lsb_c : natural := 20; -- immediate12 bit 0
|
constant instr_imm12_lsb_c : natural := 20; -- immediate12 bit 0
|
constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11
|
constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11
|
constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0
|
constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0
|
constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21
|
constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21
|
constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0
|
constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0
|
constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11
|
constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11
|
|
|
-- RISC-V Opcodes -------------------------------------------------------------------------
|
-- RISC-V Opcodes -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- alu --
|
-- alu --
|
constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
|
constant opcode_lui_c : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
|
constant opcode_auipc_c : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
|
constant opcode_auipc_c : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
|
constant opcode_alui_c : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
|
constant opcode_alui_c : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
|
constant opcode_alu_c : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
|
constant opcode_alu_c : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
|
-- control flow --
|
-- control flow --
|
constant opcode_jal_c : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
|
constant opcode_jal_c : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
|
constant opcode_jalr_c : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and register
|
constant opcode_jalr_c : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and register
|
constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
|
constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
|
-- memory access --
|
-- memory access --
|
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
|
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
|
constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
|
constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
|
-- system/csr --
|
-- system/csr --
|
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
|
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- RISC-V Funct3 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- control flow --
|
-- control flow --
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
constant funct3_beq_c : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
|
constant funct3_bne_c : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
|
constant funct3_bne_c : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
|
constant funct3_blt_c : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
|
constant funct3_blt_c : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
|
constant funct3_bge_c : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
|
constant funct3_bge_c : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
|
constant funct3_bltu_c : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
|
constant funct3_bltu_c : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
|
constant funct3_bgeu_c : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
|
constant funct3_bgeu_c : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
|
-- memory access --
|
-- memory access --
|
constant funct3_lb_c : std_ulogic_vector(2 downto 0) := "000"; -- load byte
|
constant funct3_lb_c : std_ulogic_vector(2 downto 0) := "000"; -- load byte
|
constant funct3_lh_c : std_ulogic_vector(2 downto 0) := "001"; -- load half word
|
constant funct3_lh_c : std_ulogic_vector(2 downto 0) := "001"; -- load half word
|
constant funct3_lw_c : std_ulogic_vector(2 downto 0) := "010"; -- load word
|
constant funct3_lw_c : std_ulogic_vector(2 downto 0) := "010"; -- load word
|
constant funct3_lbu_c : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
|
constant funct3_lbu_c : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
|
constant funct3_lhu_c : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
|
constant funct3_lhu_c : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
|
constant funct3_sb_c : std_ulogic_vector(2 downto 0) := "000"; -- store byte
|
constant funct3_sb_c : std_ulogic_vector(2 downto 0) := "000"; -- store byte
|
constant funct3_sh_c : std_ulogic_vector(2 downto 0) := "001"; -- store half word
|
constant funct3_sh_c : std_ulogic_vector(2 downto 0) := "001"; -- store half word
|
constant funct3_sw_c : std_ulogic_vector(2 downto 0) := "010"; -- store word
|
constant funct3_sw_c : std_ulogic_vector(2 downto 0) := "010"; -- store word
|
-- alu --
|
-- alu --
|
constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
|
constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
|
constant funct3_sll_c : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
|
constant funct3_sll_c : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
|
constant funct3_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- set on less
|
constant funct3_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- set on less
|
constant funct3_sltu_c : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
|
constant funct3_sltu_c : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
|
constant funct3_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- xor
|
constant funct3_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- xor
|
constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
|
constant funct3_sr_c : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
|
constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or
|
constant funct3_or_c : std_ulogic_vector(2 downto 0) := "110"; -- or
|
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
|
constant funct3_and_c : std_ulogic_vector(2 downto 0) := "111"; -- and
|
-- system/csr --
|
-- system/csr --
|
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
|
constant funct3_env_c : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
|
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
|
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
|
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
|
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
|
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
|
--
|
--
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
|
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
|
-- fence --
|
-- fence --
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
|
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
|
|
|
-- RISC-V Funct12 --------------------------------------------------------------------------
|
-- RISC-V Funct12 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- system --
|
-- system --
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
|
|
|
-- Co-Processor Operations ----------------------------------------------------------------
|
-- Co-Processor Operations ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- cp ids --
|
-- cp ids --
|
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV CP
|
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV CP
|
-- muldiv cp --
|
-- muldiv cp --
|
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
|
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
|
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
|
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
|
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
|
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
|
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
|
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
|
constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div
|
constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div
|
constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu
|
constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu
|
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
|
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
|
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
|
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
|
|
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- ALU Function Codes ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant alu_cmd_add_c : std_ulogic_vector(2 downto 0) := "000"; -- r <= A + B
|
constant alu_cmd_add_c : std_ulogic_vector(2 downto 0) := "000"; -- r <= A + B
|
constant alu_cmd_sub_c : std_ulogic_vector(2 downto 0) := "001"; -- r <= A - B
|
constant alu_cmd_sub_c : std_ulogic_vector(2 downto 0) := "001"; -- r <= A - B
|
constant alu_cmd_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- r <= A < B
|
constant alu_cmd_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- r <= A < B
|
constant alu_cmd_shift_c : std_ulogic_vector(2 downto 0) := "011"; -- r <= A <</>> B
|
constant alu_cmd_shift_c : std_ulogic_vector(2 downto 0) := "011"; -- r <= A <</>> B
|
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
|
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
|
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
|
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
|
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
|
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
|
constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
|
constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
|
|
|
|
-- Trap ID Codes --------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
constant trap_ima_c : std_ulogic_vector(4 downto 0) := "00000"; -- 0.0: instruction misaligned
|
|
constant trap_iba_c : std_ulogic_vector(4 downto 0) := "00001"; -- 0.1: instruction access fault
|
|
constant trap_iil_c : std_ulogic_vector(4 downto 0) := "00010"; -- 0.2: illegal instruction
|
|
constant trap_brk_c : std_ulogic_vector(4 downto 0) := "00011"; -- 0.3: breakpoint
|
|
constant trap_lma_c : std_ulogic_vector(4 downto 0) := "00100"; -- 0.4: load address misaligned
|
|
constant trap_lbe_c : std_ulogic_vector(4 downto 0) := "00101"; -- 0.5: load access fault
|
|
constant trap_sma_c : std_ulogic_vector(4 downto 0) := "00110"; -- 0.6: store address misaligned
|
|
constant trap_sbe_c : std_ulogic_vector(4 downto 0) := "00111"; -- 0.7: store access fault
|
|
constant trap_env_c : std_ulogic_vector(4 downto 0) := "01011"; -- 0.11: environment call from m-mode
|
|
constant trap_msi_c : std_ulogic_vector(4 downto 0) := "10011"; -- 1.3: machine software interrupt
|
|
constant trap_mti_c : std_ulogic_vector(4 downto 0) := "10111"; -- 1.7: machine timer interrupt
|
|
constant trap_mei_c : std_ulogic_vector(4 downto 0) := "11011"; -- 1.11: machine external interrupt
|
|
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- exception source bits --
|
-- exception source bits --
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
constant exception_iillegal_c : natural := 1; -- illegal instrution
|
constant exception_iillegal_c : natural := 1; -- illegal instrution
|
constant exception_ialign_c : natural := 2; -- instrution address misaligned
|
constant exception_ialign_c : natural := 2; -- instrution address misaligned
|
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode
|
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode
|
constant exception_break_c : natural := 4; -- breakpoint
|
constant exception_break_c : natural := 4; -- breakpoint
|
constant exception_salign_c : natural := 5; -- store address misaligned
|
constant exception_salign_c : natural := 5; -- store address misaligned
|
constant exception_lalign_c : natural := 6; -- load address misaligned
|
constant exception_lalign_c : natural := 6; -- load address misaligned
|
constant exception_saccess_c : natural := 7; -- store access fault
|
constant exception_saccess_c : natural := 7; -- store access fault
|
constant exception_laccess_c : natural := 8; -- load access fault
|
constant exception_laccess_c : natural := 8; -- load access fault
|
constant exception_width_c : natural := 9; -- length of this list in bits
|
constant exception_width_c : natural := 9; -- length of this list in bits
|
-- interrupt source bits --
|
-- interrupt source bits --
|
constant interrupt_mtime_irq_c : natural := 0; -- machine timer interrupt
|
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
|
constant interrupt_msw_irq_c : natural := 1; -- machine sw interrupt
|
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_width_c : natural := 3; -- length of this list in bits
|
constant interrupt_width_c : natural := 3; -- length of this list in bits
|
|
|
-- Clock Generator -------------------------------------------------------------------------
|
-- Clock Generator -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant clk_div2_c : natural := 0;
|
constant clk_div2_c : natural := 0;
|
constant clk_div4_c : natural := 1;
|
constant clk_div4_c : natural := 1;
|
constant clk_div8_c : natural := 2;
|
constant clk_div8_c : natural := 2;
|
constant clk_div64_c : natural := 3;
|
constant clk_div64_c : natural := 3;
|
constant clk_div128_c : natural := 4;
|
constant clk_div128_c : natural := 4;
|
constant clk_div1024_c : natural := 5;
|
constant clk_div1024_c : natural := 5;
|
constant clk_div2048_c : natural := 6;
|
constant clk_div2048_c : natural := 6;
|
constant clk_div4096_c : natural := 7;
|
constant clk_div4096_c : natural := 7;
|
|
|
-- Component: NEORV32 Processor Top Entity ------------------------------------------------
|
-- Component: NEORV32 Processor Top Entity ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_top
|
component neorv32_top
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
-- Memory configuration: Instruction memory --
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
-- Memory configuration: Data memory --
|
-- Memory configuration: Data memory --
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
-- Memory configuration: External memory interface --
|
-- Memory configuration: External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout (>=1)
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout (>=1)
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
-- Wishbone bus interface --
|
-- Wishbone bus interface --
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- GPIO --
|
-- GPIO --
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
-- UART --
|
-- UART --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
-- SPI --
|
-- SPI --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- TWI --
|
-- TWI --
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
-- PWM --
|
-- PWM --
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
-- Interrupts --
|
-- Interrupts --
|
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
|
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
|
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
|
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Top Entity --------------------------------------------------------------
|
-- Component: CPU Top Entity --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu
|
component neorv32_cpu
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
-- Memory configuration: External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
-- bus interface --
|
-- instruction bus interface --
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
|
-- data bus interface --
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- external interrupts --
|
-- external interrupts --
|
|
msw_irq_i : in std_ulogic; -- software interrupt
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
mtime_irq_i : in std_ulogic -- machine timer interrupt
|
mtime_irq_i : in std_ulogic -- machine timer interrupt
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_control
|
component neorv32_cpu_control
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- status input --
|
-- status input --
|
alu_wait_i : in std_ulogic; -- wait for ALU
|
alu_wait_i : in std_ulogic; -- wait for ALU
|
bus_wait_i : in std_ulogic; -- wait for bus
|
bus_i_wait_i : in std_ulogic; -- wait for bus
|
|
bus_d_wait_i : in std_ulogic; -- wait for bus
|
-- data input --
|
-- data input --
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
|
-- data output --
|
-- data output --
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
-- csr interface --
|
-- csr interface --
|
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
|
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
-- external interrupt --
|
-- external interrupt --
|
|
msw_irq_i : in std_ulogic; -- software interrupt
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- bus access exceptions --
|
-- bus access exceptions --
|
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
|
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
|
ma_instr_i : in std_ulogic; -- misaligned instruction address
|
ma_instr_i : in std_ulogic; -- misaligned instruction address
|
ma_load_i : in std_ulogic; -- misaligned load data address
|
ma_load_i : in std_ulogic; -- misaligned load data address
|
ma_store_i : in std_ulogic; -- misaligned store data address
|
ma_store_i : in std_ulogic; -- misaligned store data address
|
be_instr_i : in std_ulogic; -- bus error on instruction access
|
be_instr_i : in std_ulogic; -- bus error on instruction access
|
be_load_i : in std_ulogic; -- bus error on load data access
|
be_load_i : in std_ulogic; -- bus error on load data access
|
be_store_i : in std_ulogic; -- bus error on store data access
|
be_store_i : in std_ulogic -- bus error on store data access
|
bus_busy_i : in std_ulogic -- bus unit is busy
|
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Register File -----------------------------------------------------------
|
-- Component: CPU Register File -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_regfile
|
component neorv32_cpu_regfile
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- data input --
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current pc
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current pc
|
-- data output --
|
-- data output --
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_alu
|
component neorv32_cpu_alu
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- data input --
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
-- data output --
|
-- data output --
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
-- co-processor interface --
|
-- co-processor interface --
|
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
|
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
|
cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
|
cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
|
cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
|
cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
|
cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
|
cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
|
-- status --
|
-- status --
|
wait_o : out std_ulogic -- busy due to iterative processing units
|
wait_o : out std_ulogic -- busy due to iterative processing units
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Co-Processor MULDIV -----------------------------------------------------
|
-- Component: CPU Co-Processor MULDIV -----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_cp_muldiv
|
component neorv32_cpu_cp_muldiv
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- data input --
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
-- result and status --
|
-- result and status --
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
|
valid_o : out std_ulogic -- data output valid
|
valid_o : out std_ulogic -- data output valid
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- Component: CPU Bus Interface -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_bus
|
component neorv32_cpu_bus
|
generic (
|
generic (
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- cpu instruction fetch interface --
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
|
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
|
-- data output --
|
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
|
i_wait_o : out std_ulogic; -- wait for fetch to complete
|
|
--
|
|
ma_instr_o : out std_ulogic; -- misaligned instruction address
|
|
be_instr_o : out std_ulogic; -- bus error on instruction access
|
|
-- cpu data access interface --
|
|
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
|
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
-- status --
|
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
ma_instr_o : out std_ulogic; -- misaligned instruction address
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
|
--
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
be_instr_o : out std_ulogic; -- bus error on instruction access
|
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_store_o : out std_ulogic; -- bus error on store data
|
be_store_o : out std_ulogic; -- bus error on store data access
|
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
|
-- instruction bus --
|
bus_busy_o : out std_ulogic; -- bus unit is busy
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
-- bus system --
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_we_o : out std_ulogic; -- write enable
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
bus_we_o : out std_ulogic; -- write enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_re_o : out std_ulogic; -- read enable
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
bus_err_i : in std_ulogic -- bus transfer error
|
-- data bus --
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
|
d_bus_fence_o : out std_ulogic -- fence operation
|
|
);
|
|
end component;
|
|
|
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_busswitch
|
|
generic (
|
|
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
|
|
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only
|
|
);
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
|
-- controller interface a --
|
|
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
|
ca_bus_we_i : in std_ulogic; -- write enable
|
|
ca_bus_re_i : in std_ulogic; -- read enable
|
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
|
-- controller interface b --
|
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
|
cb_bus_we_i : in std_ulogic; -- write enable
|
|
cb_bus_re_i : in std_ulogic; -- read enable
|
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
|
-- peripheral bus --
|
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
p_bus_we_o : out std_ulogic; -- write enable
|
|
p_bus_re_o : out std_ulogic; -- read enable
|
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Compressed Instructions Decompressor ------------------------------------
|
-- Component: CPU Compressed Instructions Decompressor ------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_decompressor
|
component neorv32_cpu_decompressor
|
port (
|
port (
|
-- instruction input --
|
-- instruction input --
|
ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
|
ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
|
-- instruction output --
|
-- instruction output --
|
ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
|
ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
|
ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
|
ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Processor-internal instruction memory (IMEM) --------------------------------
|
-- Component: Processor-internal instruction memory (IMEM) --------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_imem
|
component neorv32_imem
|
generic (
|
generic (
|
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
|
IMEM_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
|
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes
|
IMEM_SIZE : natural := 4*1024; -- processor-internal instruction memory size in bytes
|
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
|
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
|
BOOTLOADER_USE : boolean := true -- implement and use bootloader?
|
BOOTLOADER_USE : boolean := true -- implement and use bootloader?
|
);
|
);
|
port (
|
port (
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
upen_i : in std_ulogic; -- update enable
|
upen_i : in std_ulogic; -- update enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Processor-internal data memory (DMEM) ---------------------------------------
|
-- Component: Processor-internal data memory (DMEM) ---------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_dmem
|
component neorv32_dmem
|
generic (
|
generic (
|
DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
|
DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
|
DMEM_SIZE : natural := 4*1024 -- processor-internal instruction memory size in bytes
|
DMEM_SIZE : natural := 4*1024 -- processor-internal instruction memory size in bytes
|
);
|
);
|
port (
|
port (
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
|
-- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_boot_rom
|
component neorv32_boot_rom
|
port (
|
port (
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Machine System Timer (mtime) ------------------------------------------------
|
-- Component: Machine System Timer (mtime) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_mtime
|
component neorv32_mtime
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- time output for CPU --
|
-- time output for CPU --
|
time_o : out std_ulogic_vector(63 downto 0); -- current system time
|
time_o : out std_ulogic_vector(63 downto 0); -- current system time
|
-- interrupt --
|
-- interrupt --
|
irq_o : out std_ulogic -- interrupt request
|
irq_o : out std_ulogic -- interrupt request
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
|
-- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_gpio
|
component neorv32_gpio
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- parallel io --
|
-- parallel io --
|
gpio_o : out std_ulogic_vector(15 downto 0);
|
gpio_o : out std_ulogic_vector(15 downto 0);
|
gpio_i : in std_ulogic_vector(15 downto 0);
|
gpio_i : in std_ulogic_vector(15 downto 0);
|
-- interrupt --
|
-- interrupt --
|
irq_o : out std_ulogic
|
irq_o : out std_ulogic
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Core Local Interrupt Controller (CLIC) --------------------------------------
|
-- Component: Core Local Interrupt Controller (CLIC) --------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_clic
|
component neorv32_clic
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- cpu interrupt --
|
-- cpu interrupt --
|
cpu_irq_o : out std_ulogic; -- trigger CPU's external IRQ
|
cpu_irq_o : out std_ulogic; -- trigger CPU's external IRQ
|
-- external interrupt lines --
|
-- external interrupt lines --
|
ext_irq_i : in std_ulogic_vector(07 downto 0); -- IRQ, triggering on HIGH level
|
ext_irq_i : in std_ulogic_vector(07 downto 0); -- IRQ, triggering on HIGH level
|
ext_ack_o : out std_ulogic_vector(07 downto 0) -- acknowledge
|
ext_ack_o : out std_ulogic_vector(07 downto 0) -- acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
|
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_wdt
|
component neorv32_wdt
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
-- timeout event --
|
-- timeout event --
|
irq_o : out std_ulogic; -- timeout IRQ
|
irq_o : out std_ulogic; -- timeout IRQ
|
rstn_o : out std_ulogic -- timeout reset, low_active, use it as async!
|
rstn_o : out std_ulogic -- timeout reset, low_active, use it as async!
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_uart
|
component neorv32_uart
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
-- com lines --
|
-- com lines --
|
uart_txd_o : out std_ulogic;
|
uart_txd_o : out std_ulogic;
|
uart_rxd_i : in std_ulogic;
|
uart_rxd_i : in std_ulogic;
|
-- interrupts --
|
-- interrupts --
|
uart_irq_o : out std_ulogic -- uart rx/tx interrupt
|
uart_irq_o : out std_ulogic -- uart rx/tx interrupt
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Serial Peripheral Interface (SPI) -------------------------------------------
|
-- Component: Serial Peripheral Interface (SPI) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_spi
|
component neorv32_spi
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
-- com lines --
|
-- com lines --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- interrupt --
|
-- interrupt --
|
spi_irq_o : out std_ulogic -- transmission done interrupt
|
spi_irq_o : out std_ulogic -- transmission done interrupt
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Two-Wire Interface (TWI) ----------------------------------------------------
|
-- Component: Two-Wire Interface (TWI) ----------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_twi
|
component neorv32_twi
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
-- com lines --
|
-- com lines --
|
twi_sda_io : inout std_logic; -- serial data line
|
twi_sda_io : inout std_logic; -- serial data line
|
twi_scl_io : inout std_logic; -- serial clock line
|
twi_scl_io : inout std_logic; -- serial clock line
|
-- interrupt --
|
-- interrupt --
|
twi_irq_o : out std_ulogic -- transfer done IRQ
|
twi_irq_o : out std_ulogic -- transfer done IRQ
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
|
-- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_pwm
|
component neorv32_pwm
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
-- pwm output channels --
|
-- pwm output channels --
|
pwm_o : out std_ulogic_vector(03 downto 0)
|
pwm_o : out std_ulogic_vector(03 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: True Random Number Generator (TRNG) -----------------------------------------
|
-- Component: True Random Number Generator (TRNG) -----------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_trng
|
component neorv32_trng
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
|
-- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_wishbone
|
component neorv32_wishbone
|
generic (
|
generic (
|
INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
-- Memory configuration: Instruction memory --
|
-- Memory configuration: Instruction memory --
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
-- Memory configuration: Data memory --
|
-- Memory configuration: Data memory --
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
-- host access --
|
-- host access --
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
cancel_i : in std_ulogic; -- cancel current bus transaction
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
err_o : out std_ulogic; -- transfer error
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
---- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
|
---- Component: Dummy Device with SIM Output (DEVNULL) -------------------------------------
|
---- -------------------------------------------------------------------------------------------
|
---- -------------------------------------------------------------------------------------------
|
component neorv32_devnull
|
component neorv32_devnull
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
|
);
|
|
end component;
|
|
|
|
---- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
|
---- -------------------------------------------------------------------------------------------
|
|
component neorv32_sysinfo
|
|
generic (
|
|
-- General --
|
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
|
);
|
|
port (
|
|
-- host access --
|
|
clk_i : in std_ulogic; -- global clock line
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
rden_i : in std_ulogic; -- read enable
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
package body neorv32_package is
|
package body neorv32_package is
|
|
|
-- Function: Minimal required bit width ---------------------------------------------------
|
-- Function: Minimal required bit width ---------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural is
|
function index_size_f(input : natural) return natural is
|
begin
|
begin
|
for i in 0 to natural'high loop
|
for i in 0 to natural'high loop
|
if (2**i >= input) then
|
if (2**i >= input) then
|
return i;
|
return i;
|
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
return 0;
|
return 0;
|
end function index_size_f;
|
end function index_size_f;
|
|
|
-- Function: Conditional select natural ---------------------------------------------------
|
-- Function: Conditional select natural ---------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
|
begin
|
begin
|
if (cond = true) then
|
if (cond = true) then
|
return val_t;
|
return val_t;
|
else
|
else
|
return val_f;
|
return val_f;
|
end if;
|
end if;
|
end function cond_sel_natural_f;
|
end function cond_sel_natural_f;
|
|
|
-- Function: Conditional select std_ulogic_vector -----------------------------------------
|
-- Function: Conditional select std_ulogic_vector -----------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
|
begin
|
begin
|
if (cond = true) then
|
if (cond = true) then
|
return val_t;
|
return val_t;
|
else
|
else
|
return val_f;
|
return val_f;
|
end if;
|
end if;
|
end function cond_sel_stdulogicvector_f;
|
end function cond_sel_stdulogicvector_f;
|
|
|
-- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
|
-- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic is
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic is
|
begin
|
begin
|
if (cond = true) then
|
if (cond = true) then
|
return '1';
|
return '1';
|
else
|
else
|
return '0';
|
return '0';
|
end if;
|
end if;
|
end function bool_to_ulogic_f;
|
end function bool_to_ulogic_f;
|
|
|
-- Function: OR all bits ------------------------------------------------------------------
|
-- Function: OR all bits ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function or_all_f(a : std_ulogic_vector) return std_ulogic is
|
function or_all_f(a : std_ulogic_vector) return std_ulogic is
|
variable tmp_v : std_ulogic;
|
variable tmp_v : std_ulogic;
|
begin
|
begin
|
tmp_v := a(a'low);
|
tmp_v := a(a'low);
|
for i in a'low+1 to a'high loop
|
for i in a'low+1 to a'high loop
|
tmp_v := tmp_v or a(i);
|
tmp_v := tmp_v or a(i);
|
end loop; -- i
|
end loop; -- i
|
return tmp_v;
|
return tmp_v;
|
end function or_all_f;
|
end function or_all_f;
|
|
|
-- Function: AND all bits -----------------------------------------------------------------
|
-- Function: AND all bits -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function and_all_f(a : std_ulogic_vector) return std_ulogic is
|
function and_all_f(a : std_ulogic_vector) return std_ulogic is
|
variable tmp_v : std_ulogic;
|
variable tmp_v : std_ulogic;
|
begin
|
begin
|
tmp_v := a(a'low);
|
tmp_v := a(a'low);
|
for i in a'low+1 to a'high loop
|
for i in a'low+1 to a'high loop
|
tmp_v := tmp_v and a(i);
|
tmp_v := tmp_v and a(i);
|
end loop; -- i
|
end loop; -- i
|
return tmp_v;
|
return tmp_v;
|
end function and_all_f;
|
end function and_all_f;
|
|
|
-- Function: XOR all bits -----------------------------------------------------------------
|
-- Function: XOR all bits -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function xor_all_f(a : std_ulogic_vector) return std_ulogic is
|
function xor_all_f(a : std_ulogic_vector) return std_ulogic is
|
variable tmp_v : std_ulogic;
|
variable tmp_v : std_ulogic;
|
begin
|
begin
|
tmp_v := a(a'low);
|
tmp_v := a(a'low);
|
for i in a'low+1 to a'high loop
|
for i in a'low+1 to a'high loop
|
tmp_v := tmp_v xor a(i);
|
tmp_v := tmp_v xor a(i);
|
end loop; -- i
|
end loop; -- i
|
return tmp_v;
|
return tmp_v;
|
end function xor_all_f;
|
end function xor_all_f;
|
|
|
-- Function: XNOR all bits ----------------------------------------------------------------
|
-- Function: XNOR all bits ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
|
function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
|
variable tmp_v : std_ulogic;
|
variable tmp_v : std_ulogic;
|
begin
|
begin
|
tmp_v := a(a'low);
|
tmp_v := a(a'low);
|
for i in a'low+1 to a'high loop
|
for i in a'low+1 to a'high loop
|
tmp_v := tmp_v xnor a(i);
|
tmp_v := tmp_v xnor a(i);
|
end loop; -- i
|
end loop; -- i
|
return tmp_v;
|
return tmp_v;
|
end function xnor_all_f;
|
end function xnor_all_f;
|
|
|
-- Function: Convert to hex char ----------------------------------------------------------
|
-- Function: Convert to hex char ----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
|
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
|
variable output_v : character;
|
variable output_v : character;
|
begin
|
begin
|
case input is
|
case input is
|
when x"0" => output_v := '0';
|
when x"0" => output_v := '0';
|
when x"1" => output_v := '1';
|
when x"1" => output_v := '1';
|
when x"2" => output_v := '2';
|
when x"2" => output_v := '2';
|
when x"3" => output_v := '3';
|
when x"3" => output_v := '3';
|
when x"4" => output_v := '4';
|
when x"4" => output_v := '4';
|
when x"5" => output_v := '5';
|
when x"5" => output_v := '5';
|
when x"6" => output_v := '6';
|
when x"6" => output_v := '6';
|
when x"7" => output_v := '7';
|
when x"7" => output_v := '7';
|
when x"8" => output_v := '8';
|
when x"8" => output_v := '8';
|
when x"9" => output_v := '9';
|
when x"9" => output_v := '9';
|
when x"a" => output_v := 'a';
|
when x"a" => output_v := 'a';
|
when x"b" => output_v := 'b';
|
when x"b" => output_v := 'b';
|
when x"c" => output_v := 'c';
|
when x"c" => output_v := 'c';
|
when x"d" => output_v := 'd';
|
when x"d" => output_v := 'd';
|
when x"e" => output_v := 'e';
|
when x"e" => output_v := 'e';
|
when x"f" => output_v := 'f';
|
when x"f" => output_v := 'f';
|
when others => output_v := '?';
|
when others => output_v := '?';
|
end case;
|
end case;
|
return output_v;
|
return output_v;
|
end function to_hexchar_f;
|
end function to_hexchar_f;
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|