URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sim/] [README.md] - Diff between revs 42 and 61

Rev 42	Rev 61
`## Simulation Source Folder`	`## Simulation Source Folder`

### [`ghdl`](https://github.com/stnolting/neorv32/tree/master/sim/ghdl)	### [`ghdl`](https://github.com/stnolting/neorv32/tree/master/sim/ghdl)

`This folder contains a script for simulating the processor using GHDL.`	`This folder contains a script for simulating the processor using GHDL.`

### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)	### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)

`This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.`	`This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.`

### [`vivado`](https://github.com/stnolting/neorv32/tree/master/sim/vivado)	### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)

`This folder provides an example waveform configuration (for Xilinx ISIM simulator) for the default testbench.`	`VUnit testbench for the NEORV32 Processor.`

### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)	### [`neorv32_tb.simple.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.simple.vhd)

`Default testbench for the NEORV32 Processor.`	`Simple testbench for the NEORV32 Processor.`