-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Default Testbench >> #
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-- # << NEORV32 - Default Testbench >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Use the "User Configuration" section to configure the testbench according to your need. #
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-- # Use the "User Configuration" section to configure the testbench according to your need. #
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-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information. #
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-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # provided with the distribution. #
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-- # #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
-- # endorse or promote products derived from this software without specific prior written #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # permission. #
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-- # #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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-- #################################################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.math_real.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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use std.textio.all;
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use std.textio.all;
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entity neorv32_tb is
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entity neorv32_tb is
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end neorv32_tb;
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end neorv32_tb;
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architecture neorv32_tb_rtl of neorv32_tb is
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architecture neorv32_tb_rtl of neorv32_tb is
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-- User Configuration ---------------------------------------------------------------------
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-- User Configuration ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- general --
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-- general --
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constant ext_imem_c : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
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constant ext_imem_c : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A)
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constant ext_dmem_c : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
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constant ext_dmem_c : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B)
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constant icache_use_c : boolean := false; -- set true to use processor-internal instruction cache
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constant icache_use_c : boolean := false; -- set true to use processor-internal instruction cache
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constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
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constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A
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constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
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constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B
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constant f_clock_c : natural := 100000000; -- main clock in Hz
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constant f_clock_c : natural := 100000000; -- main clock in Hz
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constant baud_rate_c : natural := 19200; -- simulation UART output baudrate
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constant baud_rate_c : natural := 19200; -- simulation UART output baudrate
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-- simulated external Wishbone memory A (can be used as external IMEM) --
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-- simulated external Wishbone memory A (can be used as external IMEM) --
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constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
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constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
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constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
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constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
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constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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-- simulated external Wishbone memory B (can be used as external DMEM) --
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-- simulated external Wishbone memory B (can be used as external DMEM) --
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constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
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constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
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constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes
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constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes
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constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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-- simulated external Wishbone memory C (can be used as external IO) --
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-- simulated external Wishbone memory C (can be used as external IO) --
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constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
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constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
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constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes
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constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes
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constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
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-- machine interrupt triggers --
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-- machine interrupt triggers --
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constant msi_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; -- machine software interrupt
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constant msi_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; -- machine software interrupt
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constant mei_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000004"; -- machine external interrupt
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constant mei_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000004"; -- machine external interrupt
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- internals - hands off! --
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-- internals - hands off! --
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constant int_imem_c : boolean := not ext_imem_c;
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constant int_imem_c : boolean := not ext_imem_c;
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constant int_dmem_c : boolean := not ext_dmem_c;
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constant int_dmem_c : boolean := not ext_dmem_c;
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constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c);
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constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c);
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constant t_clock_c : time := (1 sec) / f_clock_c;
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constant t_clock_c : time := (1 sec) / f_clock_c;
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-- text.io --
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-- text.io --
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out";
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-- generators --
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-- generators --
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signal clk_gen, rst_gen : std_ulogic := '0';
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signal clk_gen, rst_gen : std_ulogic := '0';
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-- simulation uart receiver --
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-- simulation uart receiver --
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signal uart_txd : std_ulogic;
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signal uart_txd : std_ulogic;
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart_rx_sync : std_ulogic_vector(04 downto 0) := (others => '1');
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signal uart_rx_busy : std_ulogic := '0';
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signal uart_rx_busy : std_ulogic := '0';
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart_rx_sreg : std_ulogic_vector(08 downto 0) := (others => '0');
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signal uart_rx_baud_cnt : real;
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signal uart_rx_baud_cnt : real;
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signal uart_rx_bitcnt : natural;
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signal uart_rx_bitcnt : natural;
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-- gpio --
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-- gpio --
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signal gpio : std_ulogic_vector(31 downto 0);
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signal gpio : std_ulogic_vector(31 downto 0);
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-- twi --
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-- twi --
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signal twi_scl, twi_sda : std_logic;
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signal twi_scl, twi_sda : std_logic;
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-- spi --
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-- spi --
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signal spi_data : std_ulogic;
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signal spi_data : std_ulogic;
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-- irq --
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-- irq --
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signal msi_ring, mei_ring : std_ulogic;
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signal msi_ring, mei_ring : std_ulogic;
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-- Wishbone bus --
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-- Wishbone bus --
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type wishbone_t is record
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type wishbone_t is record
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addr : std_ulogic_vector(31 downto 0); -- address
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addr : std_ulogic_vector(31 downto 0); -- address
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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wdata : std_ulogic_vector(31 downto 0); -- master write data
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rdata : std_ulogic_vector(31 downto 0); -- master read data
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rdata : std_ulogic_vector(31 downto 0); -- master read data
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we : std_ulogic; -- write enable
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we : std_ulogic; -- write enable
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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stb : std_ulogic; -- strobe
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stb : std_ulogic; -- strobe
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cyc : std_ulogic; -- valid cycle
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cyc : std_ulogic; -- valid cycle
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ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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tag : std_ulogic_vector(2 downto 0); -- tag
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tag : std_ulogic_vector(2 downto 0); -- tag
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lock : std_ulogic; -- locked/exclusive bus access
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lock : std_ulogic; -- locked/exclusive bus access
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end record;
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end record;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_msi, wb_mei : wishbone_t;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_msi, wb_mei : wishbone_t;
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-- Wishbone memories --
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-- Wishbone memories --
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
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type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
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-- init function --
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-- init function --
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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variable mem_v : ext_mem_a_ram_t;
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variable mem_v : ext_mem_a_ram_t;
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begin
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begin
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mem_v := (others => (others => '0'));
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mem_v := (others => (others => '0'));
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for i in 0 to init'length-1 loop -- init only in range of source data array
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for i in 0 to init'length-1 loop -- init only in range of source data array
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if (xbus_big_endian_c = true) then
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if (xbus_big_endian_c = true) then
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mem_v(i) := init(i);
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mem_v(i) := init(i);
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else
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else
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mem_v(i) := bswap32_f(init(i));
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mem_v(i) := bswap32_f(init(i));
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end if;
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end if;
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end loop; -- i
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end loop; -- i
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return mem_v;
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return mem_v;
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end function init_wbmem;
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end function init_wbmem;
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-- external memory components --
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-- external memory components --
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signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external IMEM
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signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external IMEM
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signal ext_ram_b : ext_mem_b_ram_t := (others => (others => '0')); -- zero, used to simulate external DMEM
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signal ext_ram_b : ext_mem_b_ram_t := (others => (others => '0')); -- zero, used to simulate external DMEM
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signal ext_ram_c : ext_mem_c_ram_t; -- uninitialized, used to simulate external IO
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signal ext_ram_c : ext_mem_c_ram_t; -- uninitialized, used to simulate external IO
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type ext_mem_t is record
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type ext_mem_t is record
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rdata : ext_mem_read_latency_t;
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rdata : ext_mem_read_latency_t;
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acc_en : std_ulogic;
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acc_en : std_ulogic;
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ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
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ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0);
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end record;
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end record;
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signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
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signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
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begin
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begin
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- Clock/Reset Generator ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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clk_gen <= not clk_gen after (t_clock_c/2);
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clk_gen <= not clk_gen after (t_clock_c/2);
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rst_gen <= '0', '1' after 60*(t_clock_c/2);
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rst_gen <= '0', '1' after 60*(t_clock_c/2);
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-- CPU Core -------------------------------------------------------------------------------
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-- CPU Core -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_top_inst: neorv32_top
|
neorv32_top_inst: neorv32_top
|
generic map (
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generic map (
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-- General --
|
-- General --
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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USER_CODE => x"12345678", -- custom user code
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USER_CODE => x"12345678", -- custom user code
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE => true, -- implement PMP?
|
PMP_NUM_REGIONS => 5, -- number of regions (0..64)
|
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PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
|
-- Hardware Performance Monitors (HPM) --
|
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HPM_NUM_CNTS => 12, -- number of inmplemnted HPM counters (0..29)
|
-- Internal Instruction memory --
|
-- Internal Instruction memory --
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MEM_INT_IMEM_USE => int_imem_c , -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE => int_imem_c , -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
-- Internal Data memory --
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-- Internal Data memory --
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MEM_INT_DMEM_USE => int_dmem_c, -- implement processor-internal data memory
|
MEM_INT_DMEM_USE => int_dmem_c, -- implement processor-internal data memory
|
MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes
|
MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes
|
-- Internal Cache memory --
|
-- Internal Cache memory --
|
ICACHE_USE => icache_use_c, -- implement instruction cache
|
ICACHE_USE => icache_use_c, -- implement instruction cache
|
ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2
|
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_USE => true, -- implement external memory bus interface?
|
MEM_EXT_USE => true, -- implement external memory bus interface?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
|
IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
|
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE => true, -- implement two-wire interface (TWI)?
|
IO_TWI_USE => true, -- implement two-wire interface (TWI)?
|
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
|
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
|
IO_TRNG_USE => false, -- trng cannot be simulated
|
IO_TRNG_USE => false, -- trng cannot be simulated
|
IO_CFU0_USE => true, -- implement custom functions unit 0 (CFU0)?
|
IO_CFU0_USE => true, -- implement custom functions unit 0 (CFU0)?
|
IO_CFU1_USE => true -- implement custom functions unit 1 (CFU1)?
|
IO_CFU1_USE => true -- implement custom functions unit 1 (CFU1)?
|
)
|
)
|
port map (
|
port map (
|
-- Global control --
|
-- Global control --
|
clk_i => clk_gen, -- global clock, rising edge
|
clk_i => clk_gen, -- global clock, rising edge
|
rstn_i => rst_gen, -- global reset, low-active, async
|
rstn_i => rst_gen, -- global reset, low-active, async
|
-- Wishbone bus interface --
|
-- Wishbone bus interface --
|
wb_tag_o => wb_cpu.tag, -- tag
|
wb_tag_o => wb_cpu.tag, -- tag
|
wb_adr_o => wb_cpu.addr, -- address
|
wb_adr_o => wb_cpu.addr, -- address
|
wb_dat_i => wb_cpu.rdata, -- read data
|
wb_dat_i => wb_cpu.rdata, -- read data
|
wb_dat_o => wb_cpu.wdata, -- write data
|
wb_dat_o => wb_cpu.wdata, -- write data
|
wb_we_o => wb_cpu.we, -- read/write
|
wb_we_o => wb_cpu.we, -- read/write
|
wb_sel_o => wb_cpu.sel, -- byte enable
|
wb_sel_o => wb_cpu.sel, -- byte enable
|
wb_stb_o => wb_cpu.stb, -- strobe
|
wb_stb_o => wb_cpu.stb, -- strobe
|
wb_cyc_o => wb_cpu.cyc, -- valid cycle
|
wb_cyc_o => wb_cpu.cyc, -- valid cycle
|
wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access
|
wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access
|
wb_ack_i => wb_cpu.ack, -- transfer acknowledge
|
wb_ack_i => wb_cpu.ack, -- transfer acknowledge
|
wb_err_i => wb_cpu.err, -- transfer error
|
wb_err_i => wb_cpu.err, -- transfer error
|
-- Advanced memory control signals --
|
-- Advanced memory control signals --
|
fence_o => open, -- indicates an executed FENCE operation
|
fence_o => open, -- indicates an executed FENCE operation
|
fencei_o => open, -- indicates an executed FENCEI operation
|
fencei_o => open, -- indicates an executed FENCEI operation
|
-- GPIO --
|
-- GPIO --
|
gpio_o => gpio, -- parallel output
|
gpio_o => gpio, -- parallel output
|
gpio_i => gpio, -- parallel input
|
gpio_i => gpio, -- parallel input
|
-- UART --
|
-- UART --
|
uart_txd_o => uart_txd, -- UART send data
|
uart_txd_o => uart_txd, -- UART send data
|
uart_rxd_i => uart_txd, -- UART receive data
|
uart_rxd_i => uart_txd, -- UART receive data
|
-- SPI --
|
-- SPI --
|
spi_sck_o => open, -- SPI serial clock
|
spi_sck_o => open, -- SPI serial clock
|
spi_sdo_o => spi_data, -- controller data out, peripheral data in
|
spi_sdo_o => spi_data, -- controller data out, peripheral data in
|
spi_sdi_i => spi_data, -- controller data in, peripheral data out
|
spi_sdi_i => spi_data, -- controller data in, peripheral data out
|
spi_csn_o => open, -- SPI CS
|
spi_csn_o => open, -- SPI CS
|
-- TWI --
|
-- TWI --
|
twi_sda_io => twi_sda, -- twi serial data line
|
twi_sda_io => twi_sda, -- twi serial data line
|
twi_scl_io => twi_scl, -- twi serial clock line
|
twi_scl_io => twi_scl, -- twi serial clock line
|
-- PWM --
|
-- PWM --
|
pwm_o => open, -- pwm channels
|
pwm_o => open, -- pwm channels
|
-- system time input from external MTIME (available if IO_MTIME_USE = false) --
|
-- system time input from external MTIME (available if IO_MTIME_USE = false) --
|
mtime_i => (others => '0'), -- current system time
|
mtime_i => (others => '0'), -- current system time
|
-- Interrupts --
|
-- Interrupts --
|
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_USE = false
|
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_USE = false
|
msw_irq_i => msi_ring, -- machine software interrupt
|
msw_irq_i => msi_ring, -- machine software interrupt
|
mext_irq_i => mei_ring -- machine external interrupt
|
mext_irq_i => mei_ring -- machine external interrupt
|
);
|
);
|
|
|
-- TWI termination (pull-ups) --
|
-- TWI termination (pull-ups) --
|
twi_scl <= 'H';
|
twi_scl <= 'H';
|
twi_sda <= 'H';
|
twi_sda <= 'H';
|
|
|
|
|
-- Console UART Receiver ------------------------------------------------------------------
|
-- Console UART Receiver ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
uart_rx_console: process(clk_gen)
|
uart_rx_console: process(clk_gen)
|
variable i : integer;
|
variable i : integer;
|
variable l : line;
|
variable l : line;
|
begin
|
begin
|
-- "UART" --
|
-- "UART" --
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- synchronizer --
|
-- synchronizer --
|
uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
|
uart_rx_sync <= uart_rx_sync(3 downto 0) & uart_txd;
|
-- arbiter --
|
-- arbiter --
|
if (uart_rx_busy = '0') then -- idle
|
if (uart_rx_busy = '0') then -- idle
|
uart_rx_busy <= '0';
|
uart_rx_busy <= '0';
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
uart_rx_bitcnt <= 9;
|
uart_rx_bitcnt <= 9;
|
if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
|
if (uart_rx_sync(4 downto 1) = "1100") then -- start bit? (falling edge)
|
uart_rx_busy <= '1';
|
uart_rx_busy <= '1';
|
end if;
|
end if;
|
else
|
else
|
if (uart_rx_baud_cnt <= 0.0) then
|
if (uart_rx_baud_cnt <= 0.0) then
|
if (uart_rx_bitcnt = 1) then
|
if (uart_rx_bitcnt = 1) then
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
uart_rx_baud_cnt <= round(0.5 * baud_val_c);
|
else
|
else
|
uart_rx_baud_cnt <= round(baud_val_c);
|
uart_rx_baud_cnt <= round(baud_val_c);
|
end if;
|
end if;
|
if (uart_rx_bitcnt = 0) then
|
if (uart_rx_bitcnt = 0) then
|
uart_rx_busy <= '0'; -- done
|
uart_rx_busy <= '0'; -- done
|
i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
|
i := to_integer(unsigned(uart_rx_sreg(8 downto 1)));
|
|
|
if (i < 32) or (i > 32+95) then -- printable char?
|
if (i < 32) or (i > 32+95) then -- printable char?
|
report "NEORV32_TB_UART.TX: (" & integer'image(i) & ")"; -- print code
|
report "NEORV32_TB_UART.TX: (" & integer'image(i) & ")"; -- print code
|
else
|
else
|
report "NEORV32_TB_UART.TX: " & character'val(i); -- print ASCII
|
report "NEORV32_TB_UART.TX: " & character'val(i); -- print ASCII
|
end if;
|
end if;
|
|
|
if (i = 10) then -- Linux line break
|
if (i = 10) then -- Linux line break
|
writeline(file_uart_tx_out, l);
|
writeline(file_uart_tx_out, l);
|
elsif (i /= 13) then -- Remove additional carriage return
|
elsif (i /= 13) then -- Remove additional carriage return
|
write(l, character'val(i));
|
write(l, character'val(i));
|
end if;
|
end if;
|
else
|
else
|
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
|
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1);
|
uart_rx_bitcnt <= uart_rx_bitcnt - 1;
|
uart_rx_bitcnt <= uart_rx_bitcnt - 1;
|
end if;
|
end if;
|
else
|
else
|
uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
|
uart_rx_baud_cnt <= uart_rx_baud_cnt - 1.0;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process uart_rx_console;
|
end process uart_rx_console;
|
|
|
|
|
-- Wishbone Fabric ------------------------------------------------------------------------
|
-- Wishbone Fabric ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- CPU broadcast signals --
|
-- CPU broadcast signals --
|
wb_mem_a.addr <= wb_cpu.addr;
|
wb_mem_a.addr <= wb_cpu.addr;
|
wb_mem_a.wdata <= wb_cpu.wdata;
|
wb_mem_a.wdata <= wb_cpu.wdata;
|
wb_mem_a.we <= wb_cpu.we;
|
wb_mem_a.we <= wb_cpu.we;
|
wb_mem_a.sel <= wb_cpu.sel;
|
wb_mem_a.sel <= wb_cpu.sel;
|
wb_mem_a.tag <= wb_cpu.tag;
|
wb_mem_a.tag <= wb_cpu.tag;
|
wb_mem_a.cyc <= wb_cpu.cyc;
|
wb_mem_a.cyc <= wb_cpu.cyc;
|
wb_mem_a.lock <= wb_cpu.lock;
|
wb_mem_a.lock <= wb_cpu.lock;
|
|
|
wb_mem_b.addr <= wb_cpu.addr;
|
wb_mem_b.addr <= wb_cpu.addr;
|
wb_mem_b.wdata <= wb_cpu.wdata;
|
wb_mem_b.wdata <= wb_cpu.wdata;
|
wb_mem_b.we <= wb_cpu.we;
|
wb_mem_b.we <= wb_cpu.we;
|
wb_mem_b.sel <= wb_cpu.sel;
|
wb_mem_b.sel <= wb_cpu.sel;
|
wb_mem_b.tag <= wb_cpu.tag;
|
wb_mem_b.tag <= wb_cpu.tag;
|
wb_mem_b.cyc <= wb_cpu.cyc;
|
wb_mem_b.cyc <= wb_cpu.cyc;
|
wb_mem_b.lock <= wb_cpu.lock;
|
wb_mem_b.lock <= wb_cpu.lock;
|
|
|
wb_mem_c.addr <= wb_cpu.addr;
|
wb_mem_c.addr <= wb_cpu.addr;
|
wb_mem_c.wdata <= wb_cpu.wdata;
|
wb_mem_c.wdata <= wb_cpu.wdata;
|
wb_mem_c.we <= wb_cpu.we;
|
wb_mem_c.we <= wb_cpu.we;
|
wb_mem_c.sel <= wb_cpu.sel;
|
wb_mem_c.sel <= wb_cpu.sel;
|
wb_mem_c.tag <= wb_cpu.tag;
|
wb_mem_c.tag <= wb_cpu.tag;
|
wb_mem_c.cyc <= wb_cpu.cyc;
|
wb_mem_c.cyc <= wb_cpu.cyc;
|
wb_mem_c.lock <= wb_cpu.lock;
|
wb_mem_c.lock <= wb_cpu.lock;
|
|
|
wb_msi.addr <= wb_cpu.addr;
|
wb_msi.addr <= wb_cpu.addr;
|
wb_msi.wdata <= wb_cpu.wdata;
|
wb_msi.wdata <= wb_cpu.wdata;
|
wb_msi.we <= wb_cpu.we;
|
wb_msi.we <= wb_cpu.we;
|
wb_msi.sel <= wb_cpu.sel;
|
wb_msi.sel <= wb_cpu.sel;
|
wb_msi.tag <= wb_cpu.tag;
|
wb_msi.tag <= wb_cpu.tag;
|
wb_msi.cyc <= wb_cpu.cyc;
|
wb_msi.cyc <= wb_cpu.cyc;
|
wb_msi.lock <= wb_cpu.lock;
|
wb_msi.lock <= wb_cpu.lock;
|
|
|
wb_mei.addr <= wb_cpu.addr;
|
wb_mei.addr <= wb_cpu.addr;
|
wb_mei.wdata <= wb_cpu.wdata;
|
wb_mei.wdata <= wb_cpu.wdata;
|
wb_mei.we <= wb_cpu.we;
|
wb_mei.we <= wb_cpu.we;
|
wb_mei.sel <= wb_cpu.sel;
|
wb_mei.sel <= wb_cpu.sel;
|
wb_mei.tag <= wb_cpu.tag;
|
wb_mei.tag <= wb_cpu.tag;
|
wb_mei.cyc <= wb_cpu.cyc;
|
wb_mei.cyc <= wb_cpu.cyc;
|
wb_mei.lock <= wb_cpu.lock;
|
wb_mei.lock <= wb_cpu.lock;
|
|
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_mei.rdata or wb_msi.rdata;
|
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_mei.rdata or wb_msi.rdata;
|
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_mei.ack or wb_msi.ack;
|
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_mei.ack or wb_msi.ack;
|
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_mei.err or wb_msi.err;
|
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_mei.err or wb_msi.err;
|
|
|
-- peripheral select via STROBE signal --
|
-- peripheral select via STROBE signal --
|
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
|
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
|
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
|
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
|
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
|
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
|
wb_msi.stb <= wb_cpu.stb when (wb_cpu.addr = msi_trigger_c) else '0';
|
wb_msi.stb <= wb_cpu.stb when (wb_cpu.addr = msi_trigger_c) else '0';
|
wb_mei.stb <= wb_cpu.stb when (wb_cpu.addr = mei_trigger_c) else '0';
|
wb_mei.stb <= wb_cpu.stb when (wb_cpu.addr = mei_trigger_c) else '0';
|
|
|
|
|
-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
|
-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ext_mem_a_access: process(clk_gen)
|
ext_mem_a_access: process(clk_gen)
|
begin
|
begin
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- control --
|
-- control --
|
ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
|
ext_mem_a.ack(0) <= wb_mem_a.cyc and wb_mem_a.stb; -- wishbone acknowledge
|
|
|
-- write access --
|
-- write access --
|
if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
|
if ((wb_mem_a.cyc and wb_mem_a.stb and wb_mem_a.we) = '1') then -- valid write access
|
for i in 0 to 3 loop
|
for i in 0 to 3 loop
|
if (wb_mem_a.sel(i) = '1') then
|
if (wb_mem_a.sel(i) = '1') then
|
ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_a.wdata(7+i*8 downto 0+i*8);
|
ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_a.wdata(7+i*8 downto 0+i*8);
|
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
|
|
-- read access --
|
-- read access --
|
ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
|
ext_mem_a.rdata(0) <= ext_ram_a(to_integer(unsigned(wb_mem_a.addr(index_size_f(ext_mem_a_size_c/4)+1 downto 2)))); -- word aligned
|
-- virtual read and ack latency --
|
-- virtual read and ack latency --
|
if (ext_mem_a_latency_c > 1) then
|
if (ext_mem_a_latency_c > 1) then
|
for i in 1 to ext_mem_a_latency_c-1 loop
|
for i in 1 to ext_mem_a_latency_c-1 loop
|
ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
|
ext_mem_a.rdata(i) <= ext_mem_a.rdata(i-1);
|
ext_mem_a.ack(i) <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
|
ext_mem_a.ack(i) <= ext_mem_a.ack(i-1) and wb_mem_a.cyc;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
|
|
-- bus output register --
|
-- bus output register --
|
wb_mem_a.err <= '0';
|
wb_mem_a.err <= '0';
|
if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
|
wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
|
wb_mem_a.ack <= '1';
|
wb_mem_a.ack <= '1';
|
else
|
else
|
wb_mem_a.rdata <= (others => '0');
|
wb_mem_a.rdata <= (others => '0');
|
wb_mem_a.ack <= '0';
|
wb_mem_a.ack <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process ext_mem_a_access;
|
end process ext_mem_a_access;
|
|
|
|
|
-- Wishbone Memory B (simulated external DMEM) --------------------------------------------
|
-- Wishbone Memory B (simulated external DMEM) --------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ext_mem_b_access: process(clk_gen)
|
ext_mem_b_access: process(clk_gen)
|
begin
|
begin
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- control --
|
-- control --
|
ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
|
ext_mem_b.ack(0) <= wb_mem_b.cyc and wb_mem_b.stb; -- wishbone acknowledge
|
|
|
-- write access --
|
-- write access --
|
if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
|
if ((wb_mem_b.cyc and wb_mem_b.stb and wb_mem_b.we) = '1') then -- valid write access
|
for i in 0 to 3 loop
|
for i in 0 to 3 loop
|
if (wb_mem_b.sel(i) = '1') then
|
if (wb_mem_b.sel(i) = '1') then
|
ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_b.wdata(7+i*8 downto 0+i*8);
|
ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_b.wdata(7+i*8 downto 0+i*8);
|
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
|
|
-- read access --
|
-- read access --
|
ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
|
ext_mem_b.rdata(0) <= ext_ram_b(to_integer(unsigned(wb_mem_b.addr(index_size_f(ext_mem_b_size_c/4)+1 downto 2)))); -- word aligned
|
-- virtual read and ack latency --
|
-- virtual read and ack latency --
|
if (ext_mem_b_latency_c > 1) then
|
if (ext_mem_b_latency_c > 1) then
|
for i in 1 to ext_mem_b_latency_c-1 loop
|
for i in 1 to ext_mem_b_latency_c-1 loop
|
ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
|
ext_mem_b.rdata(i) <= ext_mem_b.rdata(i-1);
|
ext_mem_b.ack(i) <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
|
ext_mem_b.ack(i) <= ext_mem_b.ack(i-1) and wb_mem_b.cyc;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
|
|
-- bus output register --
|
-- bus output register --
|
wb_mem_b.err <= '0';
|
wb_mem_b.err <= '0';
|
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
|
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
|
wb_mem_b.ack <= '1';
|
wb_mem_b.ack <= '1';
|
else
|
else
|
wb_mem_b.rdata <= (others => '0');
|
wb_mem_b.rdata <= (others => '0');
|
wb_mem_b.ack <= '0';
|
wb_mem_b.ack <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process ext_mem_b_access;
|
end process ext_mem_b_access;
|
|
|
|
|
-- Wishbone Memory C (simulated external IO) ----------------------------------------------
|
-- Wishbone Memory C (simulated external IO) ----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ext_mem_c_access: process(clk_gen)
|
ext_mem_c_access: process(clk_gen)
|
begin
|
begin
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- control --
|
-- control --
|
ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
|
ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge
|
|
|
-- write access --
|
-- write access --
|
if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
|
if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access
|
for i in 0 to 3 loop
|
for i in 0 to 3 loop
|
if (wb_mem_c.sel(i) = '1') then
|
if (wb_mem_c.sel(i) = '1') then
|
ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
|
ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8);
|
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
|
|
-- read access --
|
-- read access --
|
ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
|
ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned
|
-- virtual read and ack latency --
|
-- virtual read and ack latency --
|
if (ext_mem_c_latency_c > 1) then
|
if (ext_mem_c_latency_c > 1) then
|
for i in 1 to ext_mem_c_latency_c-1 loop
|
for i in 1 to ext_mem_c_latency_c-1 loop
|
ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
|
ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
|
ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
|
ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
|
|
-- error to simulate interrupted LOCKED/EXCLUSIVE bus access --
|
-- error to simulate interrupted LOCKED/EXCLUSIVE bus access --
|
wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail
|
wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail
|
|
|
-- bus output register --
|
-- bus output register --
|
if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then
|
if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then
|
wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
|
wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
|
wb_mem_c.ack <= '1';
|
wb_mem_c.ack <= '1';
|
else
|
else
|
wb_mem_c.rdata <= (others => '0');
|
wb_mem_c.rdata <= (others => '0');
|
wb_mem_c.ack <= '0';
|
wb_mem_c.ack <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process ext_mem_c_access;
|
end process ext_mem_c_access;
|
|
|
|
|
-- Wishbone IRQ Triggers ------------------------------------------------------------------
|
-- Wishbone IRQ Triggers ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ext_irq_trigger: process(clk_gen)
|
ext_irq_trigger: process(clk_gen)
|
begin
|
begin
|
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- default --
|
-- default --
|
msi_ring <= '0';
|
msi_ring <= '0';
|
wb_msi.rdata <= (others => '0');
|
wb_msi.rdata <= (others => '0');
|
wb_msi.ack <= '0';
|
wb_msi.ack <= '0';
|
wb_msi.err <= '0';
|
wb_msi.err <= '0';
|
mei_ring <= '0';
|
mei_ring <= '0';
|
wb_mei.rdata <= (others => '0');
|
wb_mei.rdata <= (others => '0');
|
wb_mei.ack <= '0';
|
wb_mei.ack <= '0';
|
wb_mei.err <= '0';
|
wb_mei.err <= '0';
|
|
|
-- machine software interrupt --
|
-- machine software interrupt --
|
if ((wb_msi.cyc and wb_msi.stb and wb_msi.we) = '1') then
|
if ((wb_msi.cyc and wb_msi.stb and wb_msi.we) = '1') then
|
msi_ring <= '1';
|
msi_ring <= '1';
|
wb_msi.ack <= '1';
|
wb_msi.ack <= '1';
|
end if;
|
end if;
|
|
|
-- machine external interrupt --
|
-- machine external interrupt --
|
if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then
|
if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then
|
mei_ring <= '1';
|
mei_ring <= '1';
|
wb_mei.ack <= '1';
|
wb_mei.ack <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process ext_irq_trigger;
|
end process ext_irq_trigger;
|
|
|
|
|
end neorv32_tb_rtl;
|
end neorv32_tb_rtl;
|
|
|
