// #################################################################################################
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// #################################################################################################
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// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
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// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # BSD 3-Clause License #
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// # #
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// # #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # permitted provided that the following conditions are met: #
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// # #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # conditions and the following disclaimer. #
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// # #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # provided with the distribution. #
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// # #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # permission. #
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// # #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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// #################################################################################################
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/**********************************************************************//**
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/**********************************************************************//**
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* @file neorv32_cpu.c
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* @file neorv32_cpu.c
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* @author Stephan Nolting
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* @author Stephan Nolting
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* @brief CPU Core Functions HW driver source file.
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* @brief CPU Core Functions HW driver source file.
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**************************************************************************/
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32.h"
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#include "neorv32_cpu.h"
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#include "neorv32_cpu.h"
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/**********************************************************************//**
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/**********************************************************************//**
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* Enable specific CPU interrupt.
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* Enable specific CPU interrupt.
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*
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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return 0;
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return 0;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Disable specific CPU interrupt.
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* Disable specific CPU interrupt.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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return 0;
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return 0;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Get cycle count from cycle[h].
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* Get cycle count from cycle[h].
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*
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*
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* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
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* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
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*
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*
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* @return Current cycle counter (64 bit).
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* @return Current cycle counter (64 bit).
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**************************************************************************/
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**************************************************************************/
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uint64_t neorv32_cpu_get_cycle(void) {
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uint64_t neorv32_cpu_get_cycle(void) {
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union {
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union {
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uint64_t uint64;
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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} cycles;
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uint32_t tmp1, tmp2, tmp3;
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uint32_t tmp1, tmp2, tmp3;
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while(1) {
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while(1) {
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tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
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tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
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tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
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tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
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tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
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tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
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if (tmp1 == tmp3) {
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if (tmp1 == tmp3) {
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break;
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break;
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}
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}
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}
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}
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cycles.uint32[0] = tmp2;
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cycles.uint32[0] = tmp2;
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cycles.uint32[1] = tmp3;
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cycles.uint32[1] = tmp3;
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return cycles.uint64;
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return cycles.uint64;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Set mcycle[h] counter.
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* Set mcycle[h] counter.
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*
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*
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* @param[in] value New value for mcycle[h] CSR (64-bit).
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* @param[in] value New value for mcycle[h] CSR (64-bit).
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**************************************************************************/
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**************************************************************************/
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void neorv32_cpu_set_mcycle(uint64_t value) {
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void neorv32_cpu_set_mcycle(uint64_t value) {
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union {
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union {
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uint64_t uint64;
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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} cycles;
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cycles.uint64 = value;
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cycles.uint64 = value;
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neorv32_cpu_csr_write(CSR_MCYCLE, 0);
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neorv32_cpu_csr_write(CSR_MCYCLE, 0);
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neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
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neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
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neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]);
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neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]);
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Get retired instructions counter from instret[h].
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* Get retired instructions counter from instret[h].
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*
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*
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* @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
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* @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
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*
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*
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* @return Current instructions counter (64 bit).
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* @return Current instructions counter (64 bit).
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**************************************************************************/
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**************************************************************************/
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uint64_t neorv32_cpu_get_instret(void) {
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uint64_t neorv32_cpu_get_instret(void) {
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union {
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union {
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uint64_t uint64;
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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} cycles;
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uint32_t tmp1, tmp2, tmp3;
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uint32_t tmp1, tmp2, tmp3;
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while(1) {
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while(1) {
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tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
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tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
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tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
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tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
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tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
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tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
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if (tmp1 == tmp3) {
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if (tmp1 == tmp3) {
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break;
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break;
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}
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}
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}
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}
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cycles.uint32[0] = tmp2;
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cycles.uint32[0] = tmp2;
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cycles.uint32[1] = tmp3;
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cycles.uint32[1] = tmp3;
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return cycles.uint64;
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return cycles.uint64;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Set retired instructions counter minstret[h].
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* Set retired instructions counter minstret[h].
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*
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*
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* @param[in] value New value for mcycle[h] CSR (64-bit).
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* @param[in] value New value for mcycle[h] CSR (64-bit).
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**************************************************************************/
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**************************************************************************/
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void neorv32_cpu_set_minstret(uint64_t value) {
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void neorv32_cpu_set_minstret(uint64_t value) {
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union {
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union {
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uint64_t uint64;
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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} cycles;
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cycles.uint64 = value;
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cycles.uint64 = value;
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neorv32_cpu_csr_write(CSR_MINSTRET, 0);
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neorv32_cpu_csr_write(CSR_MINSTRET, 0);
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neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
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neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
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neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]);
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neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]);
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Get current system time from time[h] CSR.
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* Get current system time from time[h] CSR.
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*
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*
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* @note This function requires the MTIME system timer to be implemented.
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* @note This function requires the MTIME system timer to be implemented.
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*
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*
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* @return Current system time (64 bit).
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* @return Current system time (64 bit).
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**************************************************************************/
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**************************************************************************/
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uint64_t neorv32_cpu_get_systime(void) {
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uint64_t neorv32_cpu_get_systime(void) {
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union {
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union {
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uint64_t uint64;
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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} cycles;
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uint32_t tmp1, tmp2, tmp3;
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uint32_t tmp1, tmp2, tmp3;
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while(1) {
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while(1) {
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tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
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tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
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tmp2 = neorv32_cpu_csr_read(CSR_TIME);
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tmp2 = neorv32_cpu_csr_read(CSR_TIME);
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tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
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tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
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if (tmp1 == tmp3) {
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if (tmp1 == tmp3) {
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break;
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break;
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}
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}
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}
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}
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cycles.uint32[0] = tmp2;
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cycles.uint32[0] = tmp2;
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cycles.uint32[1] = tmp3;
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cycles.uint32[1] = tmp3;
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return cycles.uint64;
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return cycles.uint64;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Simple delay function (not very precise) using busy wait.
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* Simple delay function using busy wait.
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*
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* @warning This function requires the cycle CSR(s). Hence, the Zicsr extension is mandatory.
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*
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*
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* @param[in] time_ms Time in ms to wait.
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* @param[in] time_ms Time in ms to wait.
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**************************************************************************/
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**************************************************************************/
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void neorv32_cpu_delay_ms(uint32_t time_ms) {
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void neorv32_cpu_delay_ms(uint32_t time_ms) {
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uint32_t clock_speed = SYSINFO_CLK >> 10; // fake divide by 1000
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uint64_t time_resume = neorv32_cpu_get_cycle();
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clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
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uint32_t cnt = clock_speed * time_ms;
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uint32_t clock = SYSINFO_CLK; // clock ticks per second
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clock = clock / 1000; // clock ticks per ms
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// one iteration = ~30 cycles
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while (cnt) {
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uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
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asm volatile("nop");
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time_resume += wait_cycles;
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asm volatile("nop");
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asm volatile("nop");
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while(1) {
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asm volatile("nop");
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if (neorv32_cpu_get_cycle() >= time_resume) {
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cnt--;
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break;
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}
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}
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}
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Switch from privilege mode MACHINE to privilege mode USER.
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* Switch from privilege mode MACHINE to privilege mode USER.
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*
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*
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* @note This function requires the U extension to be implemented.
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* @warning This function requires the U extension to be implemented.
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* @note Maybe you should do a fence.i after this.
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**************************************************************************/
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**************************************************************************/
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void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) {
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void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) {
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// make sure to use NO registers in here! -> naked
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// make sure to use NO registers in here! -> naked
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asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can use ra as general purpose register in here
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asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here
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"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits
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"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits
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"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode
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"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode
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"mret \n\t" // return and switch to user mode
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"mret \n\t" // return and switch to user mode
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: : [input_imm] "i" ((1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L)));
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: : [input_imm] "i" ((1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L)));
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}
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}
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/**********************************************************************//**
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* Atomic compare-and-swap operation (for implemeneting semaphores and mutexes).
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*
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* @warning This function requires the A (atomic) CPU extension.
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*
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* @param[in] addr Address of memory location.
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* @param[in] expected Expected value (for comparison).
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* @param[in] desired Desired value (new value).
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* @return Returns 0 on success, 1 on failure.
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**************************************************************************/
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int __attribute__ ((noinline)) neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired) {
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#ifdef __riscv_atomic
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register uint32_t addr_reg = addr;
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register uint32_t des_reg = desired;
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register uint32_t tmp_reg;
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// load original value + reservation (lock)
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asm volatile ("lr.w %[result], (%[input])" : [result] "=r" (tmp_reg) : [input] "r" (addr_reg));
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if (tmp_reg != expected) {
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asm volatile ("lw x0, 0(%[input])" : : [input] "r" (addr_reg)); // clear reservation lock
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return 1;
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}
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// store-conditional
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asm volatile ("sc.w %[result], %[input_i], (%[input_j])" : [result] "=r" (tmp_reg) : [input_i] "r" (des_reg), [input_j] "r" (addr_reg));
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if (tmp_reg) {
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return 1;
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}
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return 0;
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#else
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return 1; // A extension not implemented -Y always fail
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#endif
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}
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No newline at end of file
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No newline at end of file
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