URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [svd/] [neorv32.svd] - Diff between revs 69 and 70

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Rev 69	Rev 70



`stnolting`	`stnolting`
`neorv32`	`neorv32`
`RISC-V`	`RISC-V`
`1.6.4`	`1.6.4`
`The NEORV32 RISC-V Processor`	`The NEORV32 RISC-V Processor`



`NEORV32`	`NEORV32`
`r2p0`	`r2p0`
`little`	`little`
`true`	`true`
`true`	`true`
`false`	`false`
`false`	`false`
`true`	`true`
`true`	`true`
`0`	`0`
`false`	`false`



`8`	`8`
`32`	`32`
`32`	`32`
`read-write`	`read-write`
`0x00000000`	`0x00000000`
`0x00000000`	`0x00000000`






`CFS`	`CFS`
`Custom functions subsystem`	`Custom functions subsystem`
`CFS`	`CFS`
`0xFFFFFE00`	`0xFFFFFE00`

`CFS_FIRQ1`	`CFS_FIRQ1`


`0`	`0`
`0x80`	`0x80`
`registers`	`registers`



`REG0Application-defined0x00`	`REG0Application-defined0x00`
`REG1Application-defined0x04`	`REG1Application-defined0x04`
`REG2Application-defined0x08`	`REG2Application-defined0x08`
`REG3Application-defined0x0C`	`REG3Application-defined0x0C`
`REG4Application-defined0x10`	`REG4Application-defined0x10`
`REG5Application-defined0x14`	`REG5Application-defined0x14`
`REG6Application-defined0x18`	`REG6Application-defined0x18`
`REG7Application-defined0x1C`	`REG7Application-defined0x1C`
`REG8Application-defined0x20`	`REG8Application-defined0x20`
`REG9Application-defined0x24`	`REG9Application-defined0x24`
`REG10Application-defined0x28`	`REG10Application-defined0x28`
`REG11Application-defined0x2C`	`REG11Application-defined0x2C`
`REG12Application-defined0x30`	`REG12Application-defined0x30`
`REG13Application-defined0x34`	`REG13Application-defined0x34`
`REG14Application-defined0x38`	`REG14Application-defined0x38`
`REG15Application-defined0x3C`	`REG15Application-defined0x3C`
`REG16Application-defined0x40`	`REG16Application-defined0x40`
`REG17Application-defined0x44`	`REG17Application-defined0x44`
`REG18Application-defined0x48`	`REG18Application-defined0x48`
`REG19Application-defined0x4C`	`REG19Application-defined0x4C`
`REG20Application-defined0x50`	`REG20Application-defined0x50`
`REG21Application-defined0x54`	`REG21Application-defined0x54`
`REG22Application-defined0x58`	`REG22Application-defined0x58`
`REG23Application-defined0x5C`	`REG23Application-defined0x5C`
`REG24Application-defined0x60`	`REG24Application-defined0x60`
`REG25Application-defined0x64`	`REG25Application-defined0x64`
`REG26Application-defined0x68`	`REG26Application-defined0x68`
`REG27Application-defined0x6C`	`REG27Application-defined0x6C`
`REG28Application-defined0x70`	`REG28Application-defined0x70`
`REG29Application-defined0x74`	`REG29Application-defined0x74`
`REG30Application-defined0x78`	`REG30Application-defined0x78`
`REG31Application-defined0x7C`	`REG31Application-defined0x7C`





`PWM`	`PWM`
`Pulse-width modulation controller`	`Pulse-width modulation controller`
`PWM`	`PWM`
`0xFFFFFE80`	`0xFFFFFE80`


`0`	`0`
`0x40`	`0x40`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`PWM_CTRL_EN`	`PWM_CTRL_EN`
`[0:0]`	`[0:0]`
`PWM controller enable flag`	`PWM controller enable flag`


`PWM_CTRL_PRSCx`	`PWM_CTRL_PRSCx`
`[3:1]`	`[3:1]`
`Clock prescaler select`	`Clock prescaler select`




`DUTY0`	`DUTY0`
`Duty cycle register 0`	`Duty cycle register 0`
`0x04`	`0x04`


`DUTY1`	`DUTY1`
`Duty cycle register 1`	`Duty cycle register 1`
`0x08`	`0x08`


`DUTY2`	`DUTY2`
`Duty cycle register 2`	`Duty cycle register 2`
`0x0C`	`0x0C`


`DUTY3`	`DUTY3`
`Duty cycle register 3`	`Duty cycle register 3`
`0x10`	`0x10`


`DUTY4`	`DUTY4`
`Duty cycle register 4`	`Duty cycle register 4`
`0x14`	`0x14`


`DUTY5`	`DUTY5`
`Duty cycle register 5`	`Duty cycle register 5`
`0x18`	`0x18`


`DUTY6`	`DUTY6`
`Duty cycle register 6`	`Duty cycle register 6`
`0x1C`	`0x1C`


`DUTY7`	`DUTY7`
`Duty cycle register 7`	`Duty cycle register 7`
`0x20`	`0x20`


`DUTY8`	`DUTY8`
`Duty cycle register 8`	`Duty cycle register 8`
`0x24`	`0x24`


`DUTY9`	`DUTY9`
`Duty cycle register 9`	`Duty cycle register 9`
`0x28`	`0x28`


`DUTY10`	`DUTY10`
`Duty cycle register 10`	`Duty cycle register 10`
`0x2C`	`0x2C`


`DUTY11`	`DUTY11`
`Duty cycle register 11`	`Duty cycle register 11`
`0x30`	`0x30`


`DUTY12`	`DUTY12`
`Duty cycle register 12`	`Duty cycle register 12`
`0x34`	`0x34`


`DUTY13`	`DUTY13`
`Duty cycle register 13`	`Duty cycle register 13`
`0x38`	`0x38`


`DUTY14`	`DUTY14`
`Duty cycle register 14`	`Duty cycle register 14`
`0x3C`	`0x3C`






`SLINK`	`SLINK`
`Stream link interface`	`Stream link interface`
`SLINK`	`SLINK`
`0xFFFFFEC0`	`0xFFFFFEC0`

`SLINK_RX_FIRQ10`	`SLINK_RX_FIRQ10`
`SLINK_TX_FIRQ11`	`SLINK_TX_FIRQ11`


`0`	`0`
`0x40`	`0x40`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`SLINK_CTRL_RX_NUMx`	`SLINK_CTRL_RX_NUMx`
`read-only`	`read-only`
`[3:0]`	`[3:0]`
`Number of implemented RX links`	`Number of implemented RX links`


`SLINK_CTRL_TX_NUMx`	`SLINK_CTRL_TX_NUMx`
`read-only`	`read-only`
`[7:4]`	`[7:4]`
`Number of implemented TX links`	`Number of implemented TX links`


`SLINK_CTRL_RX_FIFO_Sx`	`SLINK_CTRL_RX_FIFO_Sx`
`read-only`	`read-only`
`[11:8]`	`[11:8]`
`log2(RX FIFO size)`	`log2(RX FIFO size)`


`SLINK_CTRL_TX_FIFO_Sx`	`SLINK_CTRL_TX_FIFO_Sx`
`read-only`	`read-only`
`[15:12]`	`[15:12]`
`log2(TX FIFO size)`	`log2(TX FIFO size)`


`SLINK_CTRL_EN`	`SLINK_CTRL_EN`
`read-write`	`read-write`
`[31:31]`	`[31:31]`
`SLINK enable flag`	`SLINK enable flag`




`IRQ`	`IRQ`
`Link interrupt configuration register`	`Link interrupt configuration register`
`0x08`	`0x08`


`SLINK_IRQ_RX_EN`	`SLINK_IRQ_RX_EN`
`[7:0]`	`[7:0]`
`RX link interrupt enable`	`RX link interrupt enable`


`SLINK_IRQ_RX_MODE`	`SLINK_IRQ_RX_MODE`
`[15:8]`	`[15:8]`
`RX link interrupt mode`	`RX link interrupt mode`


`SLINK_IRQ_TX_EN`	`SLINK_IRQ_TX_EN`
`[23:16]`	`[23:16]`
`TX link interrupt enable`	`TX link interrupt enable`


`SLINK_IRQ_TX_MODE`	`SLINK_IRQ_TX_MODE`
`[31:24]`	`[31:24]`
`TX link interrupt mode`	`TX link interrupt mode`




`STATUS`	`STATUS`
`Link status register`	`Link status register`
`0x10`	`0x10`


`SLINK_STATUS_RX_AVAIL`	`SLINK_STATUS_RX_AVAIL`
`[7:0]`	`[7:0]`
`RX link n FIFO is NOT empty (data available)`	`RX link n FIFO is NOT empty (data available)`


`SLINK_STATUS_TX_FREE`	`SLINK_STATUS_TX_FREE`
`[15:8]`	`[15:8]`
`TX link n FIFO is NOT full (ready to send)`	`TX link n FIFO is NOT full (ready to send)`


`SLINK_STATUS_RX_HALF`	`SLINK_STATUS_RX_HALF`
`[23:16]`	`[23:16]`
`RX link n FIFO fill level is >= half-full`	`RX link n FIFO fill level is >= half-full`


`SLINK_STATUS_TX_HALF`	`SLINK_STATUS_TX_HALF`
`[31:24]`	`[31:24]`
`TX link 0 FIFO fill level is > half-full`	`TX link 0 FIFO fill level is > half-full`




`DATA0`	`DATA0`
`Link 0 RTX data register`	`Link 0 RTX data register`
`0x20`	`0x20`


`DATA1`	`DATA1`
`Link 1 RTX data register`	`Link 1 RTX data register`
`0x24`	`0x24`


`DATA2`	`DATA2`
`Link 2 RTX data register`	`Link 2 RTX data register`
`0x28`	`0x28`


`DATA3`	`DATA3`
`Link 3 RTX data register`	`Link 3 RTX data register`
`0x2C`	`0x2C`


`DATA4`	`DATA4`
`Link 4 RTX data register`	`Link 4 RTX data register`
`0x30`	`0x30`


`DATA5`	`DATA5`
`Link 5 RTX data register`	`Link 5 RTX data register`
`0x34`	`0x34`


`DATA6`	`DATA6`
`Link 6 RTX data register`	`Link 6 RTX data register`
`0x38`	`0x38`


`DATA7`	`DATA7`
`Link 7 RTX data register`	`Link 7 RTX data register`
`0x3C`	`0x3C`






	`XIP`
	`Execute In Place Module`
	`CIP`
	`0xFFFFFF40`


	`0`
	`0x10`
	`registers`




	`CTRL`
	`Control register`
	`0x00`


	`XIP_CTRL_EN`
	`[0:0]`
	`XIP module enable flag`


	`XIP_CTRL_PRSC`
	`[3:1]`
	`SPI clock prescaler select`


	`XIP_CTRL_CPOL`
	`[4:4]`
	`SPI clock (idle) polarity`


	`XIP_CTRL_CPHA`
	`[5:5]`
	`SPI clock phase`


	`XIP_CTRL_SPI_NBYTES`
	`[9:6]`
	`Number of bytes in SPI transmission`


	`XIP_CTRL_XIP_EN`
	`[10:10]`
	`XIP mode enable`


	`XIP_CTRL_XIP_ABYTES`
	`[12:11]`
	`Number of XIP address bytes (minus 1)`


	`XIP_CTRL_RD_CMD`
	`[20:13]`
	`SPI flash read command`


	`XIP_CTRL_XIP_PAGE`
	`[24:21]`
	`XIP memory page`


	`XIP_CTRL_SPI_CSEN`
	`[25:25]`
	`SPI chip-select enable`


	`XIP_CTRL_HIGHSPEED`
	`[26:26]`
	`SPI high-speed mode enable (ignoring XIP_CTRL_PRSC)`


	`XIP_CTRL_PHY_BUSY`
	`[30:30]`
	`read-only`
	`SPI PHY busy`


	`XIP_CTRL_XIP_BUSY`
	`[31:31]`
	`read-only`
	`XIP access in progress`




	`DATA_LO`
	`Direct SPI access - data register low`
	`0x08`


	`DATA_HI`
	`Direct SPI access - data register high`
	`0x0C`






`GPTMR`	`GPTMR`
`General purpose timer`	`General purpose timer`
`GPTMR`	`GPTMR`
`0xFFFFFF60`	`0xFFFFFF60`

`GPTMR_FIRQ12`	`GPTMR_FIRQ12`


`0`	`0`
`0x10`	`0x10`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`GPTMR_CTRL_EN`	`GPTMR_CTRL_EN`
`[0:0]`	`[0:0]`
`Timer enable flag`	`Timer enable flag`


`GPTMR_CTRL_PRSC`	`GPTMR_CTRL_PRSC`
`[3:1]`	`[3:1]`
`Clock prescaler select`	`Clock prescaler select`


`GPTMR_CTRL_MODE`	`GPTMR_CTRL_MODE`
`[4:4]`	`[4:4]`
`Timer mode: 0=single-shot mode, 1=continuous mode`	`Timer mode: 0=single-shot mode, 1=continuous mode`




`THRES`	`THRES`
`Threshold register`	`Threshold register`
`0x04`	`0x04`


`COUNT`	`COUNT`
`Counter register`	`Counter register`
`0x08`	`0x08`






`BUSKEEPER`	`BUSKEEPER`
`Bus keeper`	`Bus keeper`
`BUSKEEPER`	`BUSKEEPER`
`0xFFFFFF7C`	`0xFFFFFF7C`


`0`	`0`
`0x04`	`0x04`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`BUSKEEPER_ERR_TYPE`	`BUSKEEPER_ERR_TYPE`
`[0:0]`	`[0:0]`
`read-only`	`read-only`
`Bus error type: 0=device error, 1=access timeout`	`Bus error type: 0=device error, 1=access timeout`


	`BUSKEEPER_NULL_CHECK_EN`
	`[16:16]`
	`Enable NULL address check when set`


`BUSKEEPER_ERR_FLAG`	`BUSKEEPER_ERR_FLAG`
`[31:31]`	`[31:31]`
`Sticky error flag, clears after read or write access`	`Sticky error flag, clears after read or write access`








`XIRQ`	`XIRQ`
`External interrupts controller`	`External interrupts controller`
`XIRQ`	`XIRQ`
`0xFFFFFF80`	`0xFFFFFF80`

`XIRQ_FIRQ8`	`XIRQ_FIRQ8`


`0`	`0`
`0x10`	`0x10`
`registers`	`registers`




`IER`	`IER`
`IRQ input enable register`	`IRQ input enable register`
`0x00`	`0x00`


`IPR`	`IPR`
`IRQ pending/ack/clear register`	`IRQ pending/ack/clear register`
`0x04`	`0x04`


`SCR`	`SCR`
`IRQ source register`	`IRQ source register`
`0x08`	`0x08`






`MTIME`	`MTIME`
`Machine timer`	`Machine timer`
`MTIME`	`MTIME`
`0xFFFFFF90`	`0xFFFFFF90`


`0`	`0`
`0x10`	`0x10`
`registers`	`registers`




`TIME_LO`	`TIME_LO`
`System time register - low`	`System time register - low`
`0x00`	`0x00`


`TIME_HI`	`TIME_HI`
`System time register - high`	`System time register - high`
`0x04`	`0x04`


`TIMECMP_LO`	`TIMECMP_LO`
`Time compare register - low`	`Time compare register - low`
`0x08`	`0x08`


`TIMECMP_HI`	`TIMECMP_HI`
`Time compare register - high`	`Time compare register - high`
`0x0C`	`0x0C`






`UART0`	`UART0`
`Primary universal asynchronous receiver and transmitter`	`Primary universal asynchronous receiver and transmitter`
`UART0`	`UART0`
`0xFFFFFFA0`	`0xFFFFFFA0`

`UART0_RX_FIRQ2`	`UART0_RX_FIRQ2`
`UART0_TX_FIRQ3`	`UART0_TX_FIRQ3`


`0`	`0`
`0x08`	`0x08`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`UART_CTRL_BAUD`	`UART_CTRL_BAUD`
`[11:0]`	`[11:0]`
`Baud rate divisor`	`Baud rate divisor`


`UART_CTRL_SIM_MODE`	`UART_CTRL_SIM_MODE`
`[12:12]`	`[12:12]`
`Simulation output override enable, for use in simulation only`	`Simulation output override enable, for use in simulation only`


`UART_CTRL_RX_EMPTY`	`UART_CTRL_RX_EMPTY`
`[13:13]`	`[13:13]`
`read-only`	`read-only`
`RX FIFO is empty`	`RX FIFO is empty`


`UART_CTRL_RX_HALF`	`UART_CTRL_RX_HALF`
`[14:14]`	`[14:14]`
`read-only`	`read-only`
`RX FIFO is at least half-full`	`RX FIFO is at least half-full`


`UART_CTRL_RX_FULL`	`UART_CTRL_RX_FULL`
`[15:15]`	`[15:15]`
`read-only`	`read-only`
`RX FIFO is full`	`RX FIFO is full`


`UART_CTRL_TX_EMPTY`	`UART_CTRL_TX_EMPTY`
`[16:16]`	`[16:16]`
`read-only`	`read-only`
`TX FIFO is empty`	`TX FIFO is empty`


`UART_CTRL_TX_HALF`	`UART_CTRL_TX_HALF`
`[17:17]`	`[17:17]`
`read-only`	`read-only`
`TX FIFO is at least half-full`	`TX FIFO is at least half-full`


`UART_CTRL_TX_FULL`	`UART_CTRL_TX_FULL`
`[18:18]`	`[18:18]`
`read-only`	`read-only`
`TX FIFO is full`	`TX FIFO is full`


`UART_CTRL_RTS_EN`	`UART_CTRL_RTS_EN`
`[20:20]`	`[20:20]`
`Enable hardware flow control: Assert RTS output if UART.RX is ready to receive`	`Enable hardware flow control: Assert RTS output if UART.RX is ready to receive`


`UART_CTRL_CTS_EN`	`UART_CTRL_CTS_EN`
`[21:21]`	`[21:21]`
`Enable hardware flow control: UART.TX starts sending only if CTS input is asserted`	`Enable hardware flow control: UART.TX starts sending only if CTS input is asserted`


`UART_CTRL_PMODE0`	`UART_CTRL_PMODE0`
`[22:22]`	`[22:22]`
`Parity configuration (0=even; 1=odd)`	`Parity configuration (0=even; 1=odd)`


`UART_CTRL_PMODE1`	`UART_CTRL_PMODE1`
`[23:23]`	`[23:23]`
`Parity bit enabled when set`	`Parity bit enabled when set`


`UART_CTRL_PRSC`	`UART_CTRL_PRSC`
`[26:24]`	`[26:24]`
`Clock prescaler select`	`Clock prescaler select`


`UART_CTRL_CTS`	`UART_CTRL_CTS`
`[27:27]`	`[27:27]`
`read-only`	`read-only`
`current state of CTS input`	`current state of CTS input`


`UART_CTRL_EN`	`UART_CTRL_EN`
`[28:28]`	`[28:28]`
`UART enable flag`	`UART enable flag`


`UART_CTRL_RX_IRQ`	`UART_CTRL_RX_IRQ`
`[29:29]`	`[29:29]`
`RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty`	`RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty`


`UART_CTRL_TX_IRQ`	`UART_CTRL_TX_IRQ`
`[30:30]`	`[30:30]`
`TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full`	`TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full`


`UART_CTRL_TX_BUSY`	`UART_CTRL_TX_BUSY`
`[31:31]`	`[31:31]`
`read-only`	`read-only`
`Transmitter is busy when set`	`Transmitter is busy when set`




`DATA`	`DATA`
`RX/TX data register`	`RX/TX data register`
`0x04`	`0x04`


`UART_DATA`	`UART_DATA`
`[7:0]`	`[7:0]`
`Receive/transmit data`	`Receive/transmit data`


`UART_DATA_PERR`	`UART_DATA_PERR`
`[28:28]`	`[28:28]`
`read-only`	`read-only`
`RX parity error detected when set`	`RX parity error detected when set`


`UART_DATA_FERR`	`UART_DATA_FERR`
`[29:29]`	`[29:29]`
`read-only`	`read-only`
`RX frame error (no valid stop bit) detected when set`	`RX frame error (no valid stop bit) detected when set`


`UART_DATA_OVERR`	`UART_DATA_OVERR`
`[30:30]`	`[30:30]`
`read-only`	`read-only`
`RX parity error detected when set`	`RX parity error detected when set`


`UART_DATA_AVAIL`	`UART_DATA_AVAIL`
`[31:31]`	`[31:31]`
`read-only`	`read-only`
`RX data available when set`	`RX data available when set`








`UART1`	`UART1`
`Secondary universal asynchronous receiver and transmitter`	`Secondary universal asynchronous receiver and transmitter`
`UART1`	`UART1`
`0xFFFFFFD0`	`0xFFFFFFD0`

`UART1_RX_FIRQ4`	`UART1_RX_FIRQ4`
`UART1_TX_FIRQ5`	`UART1_TX_FIRQ5`


`0`	`0`
`0x08`	`0x08`
`registers`	`registers`






`SPI`	`SPI`
`Serial peripheral interface controller`	`Serial peripheral interface controller`
`SPI`	`SPI`
`0xFFFFFFA8`	`0xFFFFFFA8`

`SPI_FIRQ6`	`SPI_FIRQ6`


`0`	`0`
`0x08`	`0x08`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`SPI_CTRL_CS`	`SPI_CTRL_CS`
`[7:0]`	`[7:0]`
`Direct chip select line`	`Direct chip select line`


`SPI_CTRL_EN`	`SPI_CTRL_EN`
`[8:8]`	`[8:8]`
`SPI enable flag`	`SPI enable flag`


`SPI_CTRL_CPHA`	`SPI_CTRL_CPHA`
`[9:9]`	`[9:9]`
`Clock phase`	`Clock phase`


`SPI_CTRL_PRSC`	`SPI_CTRL_PRSC`
`[12:10]`	`[12:10]`
`Clock prescaler select`	`Clock prescaler select`


`SPI_CTRL_SIZE`	`SPI_CTRL_SIZE`
`[14:13]`	`[14:13]`
`Data transfer size`	`Data transfer size`


`SPI_CTRL_CPOL`	`SPI_CTRL_CPOL`
`[15:15]`	`[15:15]`
`Clock polarity`	`Clock polarity`


	`SPI_CTRL_HIGHSPEED`
	`[16:16]`
	`SPI high-speed mode enable (ignoring SPI_CTRL_PRSC)`


`SPI_CTRL_BUSY`	`SPI_CTRL_BUSY`
`[31:31]`	`[31:31]`
`read-only`	`read-only`
`SPI busy flag`	`SPI busy flag`




`DATA`	`DATA`
`RX/TX data register`	`RX/TX data register`
`0x04`	`0x04`






`TWI`	`TWI`
`Two-wire interface controller`	`Two-wire interface controller`
`SPI`	`SPI`
`0xFFFFFFB0`	`0xFFFFFFB0`

`TWI_FIRQ7`	`TWI_FIRQ7`


`0`	`0`
`0x08`	`0x08`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`TWI_CTRL_EN`	`TWI_CTRL_EN`
`[0:0]`	`[0:0]`
`TWI enable flag`	`TWI enable flag`


`TWI_CTRL_START`	`TWI_CTRL_START`
`[1:1]`	`[1:1]`
`Generate START condition, auto-clears`	`Generate START condition, auto-clears`


`TWI_CTRL_STOP`	`TWI_CTRL_STOP`
`[2:2]`	`[2:2]`
`Generate STOP condition, auto-clears`	`Generate STOP condition, auto-clears`


`TWI_CTRL_PRSC`	`TWI_CTRL_PRSC`
`[5:3]`	`[5:3]`
`Clock prescaler select`	`Clock prescaler select`


`TWI_CTRL_MACK`	`TWI_CTRL_MACK`
`[6:6]`	`[6:6]`
`Generate ACK by controller for each transmission`	`Generate ACK by controller for each transmission`


`TWI_CTRL_ACK`	`TWI_CTRL_ACK`
`[30:30]`	`[30:30]`
`read-only`	`read-only`
`ACK received when set`	`ACK received when set`


`TWI_CTRL_BUSY`	`TWI_CTRL_BUSY`
`[31:31]`	`[31:31]`
`read-only`	`read-only`
`Transfer in progress, busy flag`	`Transfer in progress, busy flag`




`DATA`	`DATA`
`RX/TX data register`	`RX/TX data register`
`0x04`	`0x04`


`TWI_DATA`	`TWI_DATA`
`[7:0]`	`[7:0]`
`RX/TX data`	`RX/TX data`








`TRNG`	`TRNG`
`True random number generator`	`True random number generator`
`TRNG`	`TRNG`
`0xFFFFFFB8`	`0xFFFFFFB8`


`0`	`0`
`0x04`	`0x04`
`registers`	`registers`




`CTRL`	`CTRL`
`Control and data register`	`Control and data register`
`0x00`	`0x00`


`TRNG_CTRL_DATA`	`TRNG_CTRL_DATA`
`[7:0]`	`[7:0]`
`read-only`	`read-only`
`Random data`	`Random data`


`TRNG_CTRL_EN`	`TRNG_CTRL_EN`
`[30:30]`	`[30:30]`
`TRNG enable flag`	`TRNG enable flag`


`TRNG_CTRL_VALID`	`TRNG_CTRL_VALID`
`[31:31]`	`[31:31]`
`read-only`	`read-only`
`Random data output valid`	`Random data output valid`








`WDT`	`WDT`
`Watchdog timer`	`Watchdog timer`
`WDT`	`WDT`
`0xFFFFFFBC`	`0xFFFFFFBC`

`WDT_FIRQ0`	`WDT_FIRQ0`


`0`	`0`
`0x04`	`0x04`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`WDT_CTRL_EN`	`WDT_CTRL_EN`
`[0:0]`	`[0:0]`
`WDT enable flag`	`WDT enable flag`


`WDT_CTRL_CLK_SEL`	`WDT_CTRL_CLK_SEL`
`[3:1]`	`[3:1]`
`Clock prescaler select`	`Clock prescaler select`


`WDT_CTRL_MODE`	`WDT_CTRL_MODE`
`[4:4]`	`[4:4]`
`Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset`	`Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset`


`WDT_CTRL_RCAUSE`	`WDT_CTRL_RCAUSE`
`[5:5]`	`[5:5]`
`read-only`	`read-only`
`Cause of last system reset: 0=external reset, 1=watchdog`	`Cause of last system reset: 0=external reset, 1=watchdog`


`WDT_CTRL_RESET`	`WDT_CTRL_RESET`
`[6:6]`	`[6:6]`
`Reset WDT counter when set, auto-clears`	`Reset WDT counter when set, auto-clears`


`WDT_CTRL_FORCE`	`WDT_CTRL_FORCE`
`[7:7]`	`[7:7]`
`Force WDT action, auto-clears`	`Force WDT action, auto-clears`


`WDT_CTRL_LOCK`	`WDT_CTRL_LOCK`
`[8:8]`	`[8:8]`
`Lock write access to control register, clears on reset (HW or WDT) only`	`Lock write access to control register, clears on reset (HW or WDT) only`


`WDT_CTRL_DBEN`	`WDT_CTRL_DBEN`
`[9:9]`	`[9:9]`
`Allow WDT to continue operation even when in debug mode`	`Allow WDT to continue operation even when in debug mode`


`WDT_CTRL_HALF`	`WDT_CTRL_HALF`
`[10:10]`	`[10:10]`
`read-only`	`read-only`
`Set if at least half of the max. timeout counter value has been reached`	`Set if at least half of the max. timeout counter value has been reached`








`GPIO`	`GPIO`
`General purpose input/output port`	`General purpose input/output port`
`GPIO`	`GPIO`
`0xFFFFFFc0`	`0xFFFFFFc0`


`0`	`0`
`0x10`	`0x10`
`registers`	`registers`




`INPUT_LO`	`INPUT_LO`
`Parallel input register - low`	`Parallel input register - low`
`0x00`	`0x00`
`read-only`	`read-only`


`INPUT_HI`	`INPUT_HI`
`Parallel input register - high`	`Parallel input register - high`
`0x04`	`0x04`
`read-only`	`read-only`


`OUTPUT_LO`	`OUTPUT_LO`
`Parallel output register - low`	`Parallel output register - low`
`0x08`	`0x08`


`OUTPUT_HI`	`OUTPUT_HI`
`Parallel output register - high`	`Parallel output register - high`
`0x0C`	`0x0C`






`NEOLED`	`NEOLED`
`Smart LED hardware interface`	`Smart LED hardware interface`
`NEOLED`	`NEOLED`
`0xFFFFFFD8`	`0xFFFFFFD8`

`NEOLED_FIRQ9`	`NEOLED_FIRQ9`


`0`	`0`
`0x08`	`0x08`
`registers`	`registers`




`CTRL`	`CTRL`
`Control register`	`Control register`
`0x00`	`0x00`


`NEOLED_CTRL_EN`	`NEOLED_CTRL_EN`
`[0:0]`	`[0:0]`
`NEOLED enable flag`	`NEOLED enable flag`


`NEOLED_CTRL_MODE`	`NEOLED_CTRL_MODE`
`[1:1]`	`[1:1]`
`TX mode (0=24-bit, 1=32-bit)`	`TX mode (0=24-bit, 1=32-bit)`


`NEOLED_CTRL_STROBE`	`NEOLED_CTRL_STROBE`
`[2:2]`	`[2:2]`
`Strobe (0=send normal data, 1=send RESET command on data write)`	`Strobe (0=send normal data, 1=send RESET command on data write)`


`NEOLED_CTRL_PRSC`	`NEOLED_CTRL_PRSC`
`[5:3]`	`[5:3]`
`Clock prescaler select`	`Clock prescaler select`


`NEOLED_CTRL_BUFS`	`NEOLED_CTRL_BUFS`
`[9:6]`	`[9:6]`
`read-only`	`read-only`
`log2(tx buffer size)`	`log2(tx buffer size)`


`NEOLED_CTRL_T_TOT`	`NEOLED_CTRL_T_TOT`
`[14:10]`	`[14:10]`
`pulse-clock ticks per total period bit`	`pulse-clock ticks per total period bit`


`NEOLED_CTRL_T_ZERO_H`	`NEOLED_CTRL_T_ZERO_H`
`[19:15]`	`[19:15]`
`pulse-clock ticks per ZERO high-time`	`pulse-clock ticks per ZERO high-time`


`NEOLED_CTRL_T_ONE_H`	`NEOLED_CTRL_T_ONE_H`
`[24:20]`	`[24:20]`
`pulse-clock ticks per ONE high-time`	`pulse-clock ticks per ONE high-time`


`NEOLED_CTRL_IRQ_CONF`	`NEOLED_CTRL_IRQ_CONF`
`[27:27]`	`[27:27]`
`TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty`	`TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty`


`NEOLED_CTRL_TX_EMPTY`	`NEOLED_CTRL_TX_EMPTY`
`[28:28]`	`[28:28]`
`read-only`	`read-only`
`TX FIFO is empty`	`TX FIFO is empty`


`NEOLED_CTRL_TX_HALF`	`NEOLED_CTRL_TX_HALF`
`[29:29]`	`[29:29]`
`read-only`	`read-only`
`TX FIFO is at least half-full`	`TX FIFO is at least half-full`


`NEOLED_CTRL_TX_FULL`	`NEOLED_CTRL_TX_FULL`
`[30:30]`	`[30:30]`
`read-only`	`read-only`
`TX FIFO is full`	`TX FIFO is full`


`NEOLED_CTRL_TX_BUSY`	`NEOLED_CTRL_TX_BUSY`
`[31:31]`	`[31:31]`
`read-only`	`read-only`
`busy flag`	`busy flag`




`DATA`	`DATA`
`Data register`	`Data register`
`0x04`	`0x04`






`SYSINFO`	`SYSINFO`
`System configuration information memory`	`System configuration information memory`
`SYSINFO`	`SYSINFO`
`0xFFFFFFE0`	`0xFFFFFFE0`


`0`	`0`
`0x20`	`0x20`
`registers`	`registers`




`CLK`	`CLK`
`Clock speed in Hz`	`Clock speed in Hz`
`0x00`	`0x00`
`read-only`	`read-only`


`CPU`	`CPU`
`CPU core features`	`CPU core features`
`0x04`	`0x04`
`read-only`	`read-only`

`SYSINFO_CPU_ZICSR[0:0]Zicsr extension (I sub-extension) available when set`	`SYSINFO_CPU_ZICSR[0:0]Zicsr extension (I sub-extension) available when set`
`SYSINFO_CPU_ZIFENCEI[1:1]Zifencei extension (I sub-extension) available when set`	`SYSINFO_CPU_ZIFENCEI[1:1]Zifencei extension (I sub-extension) available when set`
`SYSINFO_CPU_ZMMUL[2:2]Zmmul extension (M sub-extension) available when set`	`SYSINFO_CPU_ZMMUL[2:2]Zmmul extension (M sub-extension) available when set`
`SYSINFO_CPU_ZFINX[5:5]Zfinx extension (F sub-/alternative-extension) available when set`	`SYSINFO_CPU_ZFINX[5:5]Zfinx extension (F sub-/alternative-extension) available when set`
`SYSINFO_CPU_ZXSCNT[6:6]Custom extension - Small CPU counters`	`SYSINFO_CPU_ZXSCNT[6:6]Custom extension - Small CPU counters`
`SYSINFO_CPU_ZICNTR[7:7]Basic CPU counters available when set`	`SYSINFO_CPU_ZICNTR[7:7]Basic CPU counters available when set`
`SYSINFO_CPU_PMP[8:8]PMP (physical memory protection) extension available when set`	`SYSINFO_CPU_PMP[8:8]PMP (physical memory protection) extension available when set`
`SYSINFO_CPU_ZIHPM[9:9]HPM (hardware performance monitors) extension available when set`	`SYSINFO_CPU_ZIHPM[9:9]HPM (hardware performance monitors) extension available when set`
`SYSINFO_CPU_DEBUGMODE[10:10]RISC-V CPU debug mode available when set`	`SYSINFO_CPU_DEBUGMODE[10:10]RISC-V CPU debug mode available when set`
`SYSINFO_CPU_FASTMUL[30:30]fast multiplications (via FAST_MUL_EN generic) available when set`	`SYSINFO_CPU_FASTMUL[30:30]fast multiplications (via FAST_MUL_EN generic) available when set`
`SYSINFO_CPU_FASTSHIFT[31:31]fast shifts (via FAST_SHIFT_EN generic) available when set`	`SYSINFO_CPU_FASTSHIFT[31:31]fast shifts (via FAST_SHIFT_EN generic) available when set`



`SOC`	`SOC`
`SoC features`	`SoC features`
`0x08`	`0x08`
`read-only`	`read-only`

`SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented`	`SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented`
`SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented`	`SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented`
`SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented`	`SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented`
`SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented`	`SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented`
`SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order`	`SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order`
`SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented`	`SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented`
`SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated`	`SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated`
`SYSINFO_SOC_OCD[14:14]On-chip debugger implemented`	`SYSINFO_SOC_OCD[14:14]On-chip debugger implemented`
`SYSINFO_SOC_HW_RESET[15:15]Dedicated hardware reset of core registers implemented`	`SYSINFO_SOC_HW_RESET[15:15]Dedicated hardware reset of core registers implemented`
`SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented`	`SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented`
`SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented`	`SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented`
`SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented`	`SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented`
`SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented`	`SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented`
`SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented`	`SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented`
`SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented`	`SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented`
`SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented`	`SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented`
`SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented`	`SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented`
`SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented`	`SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented`
`SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented`	`SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented`
`SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented`	`SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented`
`SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented`	`SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented`
`SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented`	`SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented`
`SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented`	`SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented`
	`SYSINFO_SOC_IO_XIP[30:30]Execute in place module implemented`



`CACHE`	`CACHE`
`Cache configuration`	`Cache configuration`
`0x0C`	`0x0C`
`read-only`	`read-only`

`SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes)`	`SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes)`
`SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines)`	`SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines)`
`SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity)`	`SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity)`
`SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0)`	`SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0)`



`ISPACE_BASE`	`ISPACE_BASE`
`Instruction memory address space base address`	`Instruction memory address space base address`
`0x10`	`0x10`
`read-only`	`read-only`


`DSPACE_BASE`	`DSPACE_BASE`
`Data memory address space base address`	`Data memory address space base address`
`0x14`	`0x14`
`read-only`	`read-only`


`IMEM_SIZE`	`IMEM_SIZE`
`Internal instruction memory (IMEM) size in bytes`	`Internal instruction memory (IMEM) size in bytes`
`0x18`	`0x18`
`read-only`	`read-only`


`DMEM_SIZE`	`DMEM_SIZE`
`Internal data memory (DMEM) size in bytes`	`Internal data memory (DMEM) size in bytes`
`0x1C`	`0x1C`
`read-only`	`read-only`

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[/] [neorv32/] [trunk/] [sw/] [svd/] [neorv32.svd] - Diff between revs 69 and 70