//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : H264Decoder
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// Design : H264Decoder
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// Author : KE XU
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// Author : KE XU
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// Email : kexu@ee.cuhk.edu.hk
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// Email : kexu@ee.cuhk.edu.hk
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// File : rec_DF_RAM1.v
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// File : rec_DF_RAM1.v
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// Generated : Dec 7 2005
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// Generated : Dec 7 2005
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// Description : SRAM between reconstruction and deblocking filter (96x32bit)
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// Description : SRAM between reconstruction and deblocking filter (96x32bit)
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module rec_DF_RAM1_wrapper (clk,gclk_rec_DF_RAM1,reset_n,
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module rec_DF_RAM1_wrapper (clk,gclk_rec_DF_RAM1,reset_n,
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rec_DF_RAM1_cs_n,rec_DF_RAM1_wr,rec_DF_RAM1_addr,rec_DF_RAM1_din,rec_DF_RAM1_dout);
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rec_DF_RAM1_cs_n,rec_DF_RAM1_wr,rec_DF_RAM1_addr,rec_DF_RAM1_din,rec_DF_RAM1_dout);
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input clk;
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input clk;
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input gclk_rec_DF_RAM1;
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input gclk_rec_DF_RAM1;
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input reset_n;
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input reset_n;
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input rec_DF_RAM1_cs_n;
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input rec_DF_RAM1_cs_n;
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input rec_DF_RAM1_wr;
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input rec_DF_RAM1_wr;
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input [6:0] rec_DF_RAM1_addr;
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input [6:0] rec_DF_RAM1_addr;
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input [31:0] rec_DF_RAM1_din;
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input [31:0] rec_DF_RAM1_din;
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output [31:0] rec_DF_RAM1_dout;
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output [31:0] rec_DF_RAM1_dout;
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reg rec_DF_RAM1_OEN;
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reg rec_DF_RAM1_OEN;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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rec_DF_RAM1_OEN <= 1'b1;
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rec_DF_RAM1_OEN <= 1'b1;
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else if (!rec_DF_RAM1_cs_n && !rec_DF_RAM1_wr)
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else if (!rec_DF_RAM1_cs_n && !rec_DF_RAM1_wr)
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rec_DF_RAM1_OEN <= 1'b0;
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rec_DF_RAM1_OEN <= 1'b0;
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else
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else
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rec_DF_RAM1_OEN <= 1'b1;
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rec_DF_RAM1_OEN <= 1'b1;
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wire rec_DF_RAM1_CEN;
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wire rec_DF_RAM1_CEN;
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assign rec_DF_RAM1_CEN = rec_DF_RAM1_cs_n & rec_DF_RAM1_OEN;
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assign rec_DF_RAM1_CEN = rec_DF_RAM1_cs_n & rec_DF_RAM1_OEN;
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rec_DF_RAM1_96x32 rec_DF_RAM1_96x32 (
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rec_DF_RAM1_96x32 rec_DF_RAM1_96x32 (
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.CK(gclk_rec_DF_RAM1),
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.CK(gclk_rec_DF_RAM1),
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.ADR(rec_DF_RAM1_addr),
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.ADR(rec_DF_RAM1_addr),
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.DI(rec_DF_RAM1_din),
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.DI(rec_DF_RAM1_din),
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.WEN(~rec_DF_RAM1_wr),
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.WEN(~rec_DF_RAM1_wr),
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.CEN(rec_DF_RAM1_CEN),
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.CEN(rec_DF_RAM1_CEN),
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.OEN(rec_DF_RAM1_OEN),
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.OEN(rec_DF_RAM1_OEN),
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.DOUT(rec_DF_RAM1_dout)
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.DOUT(rec_DF_RAM1_dout)
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);
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);
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endmodule
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endmodule
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/*
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/*
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module rec_DF_RAM1_96x32 (CK,ADR,DI,WEN,CEN,OEN,DOUT);
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module rec_DF_RAM1_96x32 (CK,ADR,DI,WEN,CEN,OEN,DOUT);
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input CK;
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input CK;
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input [6:0] ADR;
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input [6:0] ADR;
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input [31:0] DI;
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input [31:0] DI;
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input WEN;
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input WEN;
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input CEN;
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input CEN;
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input OEN;
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input OEN;
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output [31:0] DOUT;
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output [31:0] DOUT;
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reg [31:0] DOUT;
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reg [31:0] DOUT;
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reg [31:0] RAM [0:95];
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reg [31:0] RAM [0:95];
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always @ (posedge CK)
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always @ (posedge CK)
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if (!CEN && !WEN)
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if (!CEN && !WEN)
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RAM[ADR] <= DI;
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RAM[ADR] <= DI;
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always @ (posedge CK)
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always @ (posedge CK)
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if (!CEN && !OEN)
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if (!CEN && !OEN)
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DOUT <= RAM[ADR];
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DOUT <= RAM[ADR];
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endmodule*/
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endmodule*/
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