//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : DF_top.v
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// File : DF_top.v
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// Generated : Dec 30, 2005
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// Generated : Dec 30, 2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Top module of deblocking filter
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// Top module of deblocking filter
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module DF_top (clk,reset_n,gclk_DF,gclk_end_of_MB_DEC,gclk_DF_mbAddrA_RF,gclk_DF_mbAddrB_RAM,
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module DF_top (clk,reset_n,gclk_DF,gclk_end_of_MB_DEC,gclk_DF_mbAddrA_RF,gclk_DF_mbAddrB_RAM,
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end_of_BS_DEC,disable_DF,mb_num_h,mb_num_v,
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end_of_BS_DEC,disable_DF,mb_num_h,mb_num_v,
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bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
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bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
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QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
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QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
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blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM_dout,
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blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM_dout,
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blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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DF_duration,end_of_MB_DF,DF_edge_counter_MR,one_edge_counter_MR,
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DF_duration,end_of_MB_DF,DF_edge_counter_MR,one_edge_counter_MR,
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DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,
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DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,
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dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din);
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dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din);
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input clk;
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input clk;
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input gclk_DF;
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input gclk_DF;
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input gclk_end_of_MB_DEC;
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input gclk_end_of_MB_DEC;
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input gclk_DF_mbAddrA_RF;
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input gclk_DF_mbAddrA_RF;
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input gclk_DF_mbAddrB_RAM;
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input gclk_DF_mbAddrB_RAM;
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input reset_n;
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input reset_n;
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input end_of_BS_DEC;
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input end_of_BS_DEC;
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input disable_DF;
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input disable_DF;
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input [3:0] mb_num_h;
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input [3:0] mb_num_h;
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input [3:0] mb_num_v;
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input [3:0] mb_num_v;
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input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
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input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
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input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
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input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
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input [5:0] QPy,QPc;
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input [5:0] QPy,QPc;
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input [3:0] slice_alpha_c0_offset_div2;
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input [3:0] slice_alpha_c0_offset_div2;
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input [3:0] slice_beta_offset_div2;
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input [3:0] slice_beta_offset_div2;
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input [31:0] rec_DF_RAM_dout;
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input [31:0] rec_DF_RAM_dout;
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input [2:0] blk4x4_sum_counter;
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input [2:0] blk4x4_sum_counter;
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input [4:0] blk4x4_rec_counter_2_raster_order;
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input [4:0] blk4x4_rec_counter_2_raster_order;
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input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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output DF_duration;
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output DF_duration;
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output end_of_MB_DF;
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output end_of_MB_DF;
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output [5:0] DF_edge_counter_MR;
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output [5:0] DF_edge_counter_MR;
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output [1:0] one_edge_counter_MR;
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output [1:0] one_edge_counter_MR;
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output DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr;
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output DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr;
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output DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
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output DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
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output dis_frame_RAM_wr;
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output dis_frame_RAM_wr;
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output [13:0] dis_frame_RAM_wr_addr;
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output [13:0] dis_frame_RAM_wr_addr;
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output [31:0] dis_frame_RAM_din;
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output [31:0] dis_frame_RAM_din;
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wire end_of_MB_DF;
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wire end_of_MB_DF;
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wire end_of_lastMB_DF;
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wire end_of_lastMB_DF;
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wire [3:0] mb_num_h_DF;
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wire [3:0] mb_num_h_DF;
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wire [3:0] mb_num_v_DF;
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wire [3:0] mb_num_v_DF;
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wire [5:0] DF_edge_counter_MR,DF_edge_counter_MW;
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wire [5:0] DF_edge_counter_MR,DF_edge_counter_MW;
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wire [1:0] one_edge_counter_MR,one_edge_counter_MW;
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wire [1:0] one_edge_counter_MR,one_edge_counter_MW;
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wire [2:0] bs_curr_MR,bs_curr_MW;
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wire [2:0] bs_curr_MR,bs_curr_MW;
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wire [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
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wire [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
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wire [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
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wire [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
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wire [31:0] buf0_0,buf0_1,buf0_2,buf0_3;
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wire [31:0] buf0_0,buf0_1,buf0_2,buf0_3;
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wire [31:0] buf1_0,buf1_1,buf1_2,buf1_3;
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wire [31:0] buf1_0,buf1_1,buf1_2,buf1_3;
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wire [31:0] buf2_0,buf2_1,buf2_2,buf2_3;
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wire [31:0] buf2_0,buf2_1,buf2_2,buf2_3;
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wire [31:0] buf3_0,buf3_1,buf3_2,buf3_3;
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wire [31:0] buf3_0,buf3_1,buf3_2,buf3_3;
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wire [31:0] t0_0,t0_1,t0_2,t0_3;
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wire [31:0] t0_0,t0_1,t0_2,t0_3;
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wire [31:0] t1_0,t1_1,t1_2,t1_3;
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wire [31:0] t1_0,t1_1,t1_2,t1_3;
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wire [31:0] t2_0,t2_1,t2_2,t2_3;
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wire [31:0] t2_0,t2_1,t2_2,t2_3;
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wire DF_mbAddrA_RF_rd;
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wire DF_mbAddrA_RF_rd;
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wire DF_mbAddrA_RF_wr;
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wire DF_mbAddrA_RF_wr;
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wire [4:0] DF_mbAddrA_RF_rd_addr;
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wire [4:0] DF_mbAddrA_RF_rd_addr;
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wire [4:0] DF_mbAddrA_RF_wr_addr;
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wire [4:0] DF_mbAddrA_RF_wr_addr;
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wire [31:0] DF_mbAddrA_RF_din;
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wire [31:0] DF_mbAddrA_RF_din;
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wire [31:0] DF_mbAddrA_RF_dout;
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wire [31:0] DF_mbAddrA_RF_dout;
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wire DF_mbAddrB_RAM_rd;
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wire DF_mbAddrB_RAM_rd;
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wire DF_mbAddrB_RAM_wr;
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wire DF_mbAddrB_RAM_wr;
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wire [8:0] DF_mbAddrB_RAM_addr;
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wire [8:0] DF_mbAddrB_RAM_addr;
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wire [31:0] DF_mbAddrB_RAM_din;
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wire [31:0] DF_mbAddrB_RAM_din;
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wire [31:0] DF_mbAddrB_RAM_dout;
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wire [31:0] DF_mbAddrB_RAM_dout;
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DF_pipeline DF_pipeline (
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DF_pipeline DF_pipeline (
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.clk(clk),
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.clk(clk),
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.gclk_DF(gclk_DF),
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.gclk_DF(gclk_DF),
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.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
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.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.disable_DF(disable_DF),
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.disable_DF(disable_DF),
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.end_of_BS_DEC(end_of_BS_DEC),
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.end_of_BS_DEC(end_of_BS_DEC),
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.end_of_MB_DF(end_of_MB_DF),
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.end_of_MB_DF(end_of_MB_DF),
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.end_of_lastMB_DF(end_of_lastMB_DF),
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.end_of_lastMB_DF(end_of_lastMB_DF),
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.bs_V0(bs_V0),.bs_V1(bs_V1),.bs_V2(bs_V2),.bs_V3(bs_V3),
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.bs_V0(bs_V0),.bs_V1(bs_V1),.bs_V2(bs_V2),.bs_V3(bs_V3),
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.bs_H0(bs_H0),.bs_H1(bs_H1),.bs_H2(bs_H2),.bs_H3(bs_H3),
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.bs_H0(bs_H0),.bs_H1(bs_H1),.bs_H2(bs_H2),.bs_H3(bs_H3),
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.QPy(QPy),
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.QPy(QPy),
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.QPc(QPc),
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.QPc(QPc),
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.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
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.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
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.slice_beta_offset_div2(slice_beta_offset_div2),
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.slice_beta_offset_div2(slice_beta_offset_div2),
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.DF_mbAddrA_RF_dout(DF_mbAddrA_RF_dout),
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.DF_mbAddrA_RF_dout(DF_mbAddrA_RF_dout),
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.DF_mbAddrB_RAM_dout(DF_mbAddrB_RAM_dout),
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.DF_mbAddrB_RAM_dout(DF_mbAddrB_RAM_dout),
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.rec_DF_RAM_dout(rec_DF_RAM_dout),
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.rec_DF_RAM_dout(rec_DF_RAM_dout),
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.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
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.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
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.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3),
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.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3),
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.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
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.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
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.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
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.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
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.DF_duration(DF_duration),
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.DF_duration(DF_duration),
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.DF_edge_counter_MR(DF_edge_counter_MR),
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.DF_edge_counter_MR(DF_edge_counter_MR),
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.DF_edge_counter_MW(DF_edge_counter_MW),
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.DF_edge_counter_MW(DF_edge_counter_MW),
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.one_edge_counter_MR(one_edge_counter_MR),
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.one_edge_counter_MR(one_edge_counter_MR),
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.one_edge_counter_MW(one_edge_counter_MW),
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.one_edge_counter_MW(one_edge_counter_MW),
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.bs_curr_MR(bs_curr_MR),
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.bs_curr_MR(bs_curr_MR),
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.bs_curr_MW(bs_curr_MW),
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.bs_curr_MW(bs_curr_MW),
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.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
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.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
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.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW)
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.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW)
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);
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);
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DF_reg_ctrl DF_reg_ctrl (
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DF_reg_ctrl DF_reg_ctrl (
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.gclk_DF(gclk_DF),
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.gclk_DF(gclk_DF),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.DF_edge_counter_MW(DF_edge_counter_MW),
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.DF_edge_counter_MW(DF_edge_counter_MW),
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.one_edge_counter_MW(one_edge_counter_MW),
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.one_edge_counter_MW(one_edge_counter_MW),
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.mb_num_h_DF(mb_num_h_DF),
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.mb_num_h_DF(mb_num_h_DF),
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.mb_num_v_DF(mb_num_v_DF),
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.mb_num_v_DF(mb_num_v_DF),
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.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
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.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
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.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW),
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.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW),
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.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
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.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
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.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3),
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.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3),
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.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
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.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
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.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
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.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
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.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3),
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.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3),
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.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3),
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.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3),
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.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3)
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.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3)
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);
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);
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DF_mem_ctrl DF_mem_ctrl (
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DF_mem_ctrl DF_mem_ctrl (
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
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.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
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.disable_DF(disable_DF),
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.disable_DF(disable_DF),
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.mb_num_h(mb_num_h),
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.mb_num_h(mb_num_h),
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.mb_num_v(mb_num_v),
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.mb_num_v(mb_num_v),
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.bs_curr_MR(bs_curr_MR),
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.bs_curr_MR(bs_curr_MR),
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.bs_curr_MW(bs_curr_MW),
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.bs_curr_MW(bs_curr_MW),
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.blk4x4_sum_counter(blk4x4_sum_counter),
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.blk4x4_sum_counter(blk4x4_sum_counter),
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.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
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.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
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.DF_edge_counter_MR(DF_edge_counter_MR),
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.DF_edge_counter_MR(DF_edge_counter_MR),
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.DF_edge_counter_MW(DF_edge_counter_MW),
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.DF_edge_counter_MW(DF_edge_counter_MW),
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.one_edge_counter_MR(one_edge_counter_MR),
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.one_edge_counter_MR(one_edge_counter_MR),
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.one_edge_counter_MW(one_edge_counter_MW),
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.one_edge_counter_MW(one_edge_counter_MW),
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.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
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.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
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.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
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.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
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.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
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.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
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.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
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.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
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.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
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.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
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.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW),
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.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW),
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.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
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.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
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.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
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.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
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.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
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.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
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.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3),
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.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3),
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.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3),
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.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3),
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.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3),
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.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3),
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.mb_num_h_DF(mb_num_h_DF),
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.mb_num_h_DF(mb_num_h_DF),
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.mb_num_v_DF(mb_num_v_DF),
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.mb_num_v_DF(mb_num_v_DF),
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.end_of_MB_DF(end_of_MB_DF),
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.end_of_MB_DF(end_of_MB_DF),
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.end_of_lastMB_DF(end_of_lastMB_DF),
|
.end_of_lastMB_DF(end_of_lastMB_DF),
|
.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd),
|
.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd),
|
.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr),
|
.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr),
|
.DF_mbAddrA_RF_rd_addr(DF_mbAddrA_RF_rd_addr),
|
.DF_mbAddrA_RF_rd_addr(DF_mbAddrA_RF_rd_addr),
|
.DF_mbAddrA_RF_wr_addr(DF_mbAddrA_RF_wr_addr),
|
.DF_mbAddrA_RF_wr_addr(DF_mbAddrA_RF_wr_addr),
|
.DF_mbAddrA_RF_din(DF_mbAddrA_RF_din),
|
.DF_mbAddrA_RF_din(DF_mbAddrA_RF_din),
|
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd),
|
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd),
|
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr),
|
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr),
|
.DF_mbAddrB_RAM_addr(DF_mbAddrB_RAM_addr),
|
.DF_mbAddrB_RAM_addr(DF_mbAddrB_RAM_addr),
|
.DF_mbAddrB_RAM_din(DF_mbAddrB_RAM_din),
|
.DF_mbAddrB_RAM_din(DF_mbAddrB_RAM_din),
|
.dis_frame_RAM_wr(dis_frame_RAM_wr),
|
.dis_frame_RAM_wr(dis_frame_RAM_wr),
|
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr),
|
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr),
|
.dis_frame_RAM_din(dis_frame_RAM_din)
|
.dis_frame_RAM_din(dis_frame_RAM_din)
|
);
|
);
|
ram_sync_1r_sync_1w # (`DF_mbAddrA_RAM_data_width,`DF_mbAddrA_RAM_data_depth)
|
ram_sync_1r_sync_1w # (`DF_mbAddrA_RAM_data_width,`DF_mbAddrA_RAM_data_depth)
|
DF_mbAddrA_RAM (
|
DF_mbAddrA_RAM (
|
.clk(gclk_DF_mbAddrA_RF),
|
.clk(gclk_DF_mbAddrA_RF),
|
.rst_n(reset_n),
|
.rst_n(reset_n),
|
.wr_n(~DF_mbAddrA_RF_wr),
|
.wr_n(~DF_mbAddrA_RF_wr),
|
.rd_n(~DF_mbAddrA_RF_rd),
|
.rd_n(~DF_mbAddrA_RF_rd),
|
.wr_addr(DF_mbAddrA_RF_wr_addr),
|
.wr_addr(DF_mbAddrA_RF_wr_addr),
|
.rd_addr(DF_mbAddrA_RF_rd_addr),
|
.rd_addr(DF_mbAddrA_RF_rd_addr),
|
.data_in(DF_mbAddrA_RF_din),
|
.data_in(DF_mbAddrA_RF_din),
|
.data_out(DF_mbAddrA_RF_dout)
|
.data_out(DF_mbAddrA_RF_dout)
|
);
|
);
|
ram_sync_1r_sync_1w # (`DF_mbAddrB_RAM_data_width,`DF_mbAddrB_RAM_data_depth)
|
ram_sync_1r_sync_1w # (`DF_mbAddrB_RAM_data_width,`DF_mbAddrB_RAM_data_depth)
|
DF_mbAddrB_RAM (
|
DF_mbAddrB_RAM (
|
.clk(gclk_DF_mbAddrB_RAM),
|
.clk(gclk_DF_mbAddrB_RAM),
|
.rst_n(reset_n),
|
.rst_n(reset_n),
|
.wr_n(~DF_mbAddrB_RAM_wr),
|
.wr_n(~DF_mbAddrB_RAM_wr),
|
.rd_n(~DF_mbAddrB_RAM_rd),
|
.rd_n(~DF_mbAddrB_RAM_rd),
|
.wr_addr(DF_mbAddrB_RAM_addr),
|
.wr_addr(DF_mbAddrB_RAM_addr),
|
.rd_addr(DF_mbAddrB_RAM_addr),
|
.rd_addr(DF_mbAddrB_RAM_addr),
|
.data_in(DF_mbAddrB_RAM_din),
|
.data_in(DF_mbAddrB_RAM_din),
|
.data_out(DF_mbAddrB_RAM_dout)
|
.data_out(DF_mbAddrB_RAM_dout)
|
);
|
);
|
|
|
