//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : Inter_mv_decoding.v
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// File : Inter_mv_decoding.v
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// Generated : May 25, 2005
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// Generated : May 25, 2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Decoding the motion vector x and motion vector y for Inter prediction and P_skip
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// Decoding the motion vector x and motion vector y for Inter prediction and P_skip
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// SearchRange = 16pix -> 64 -> -64 ~ + 64 -> mvd[7:0], mv[7:0], mvp[7:0]
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// SearchRange = 16pix -> 64 -> -64 ~ + 64 -> mvd[7:0], mv[7:0], mvp[7:0]
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module Inter_mv_decoding (clk,reset_n,Is_skip_run_entry,Is_skip_run_end,
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module Inter_mv_decoding (clk,reset_n,Is_skip_run_entry,Is_skip_run_end,
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slice_data_state,mb_pred_state,sub_mb_pred_state,mvd,
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slice_data_state,mb_pred_state,sub_mb_pred_state,mvd,
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mb_num,mb_num_h,mb_num_v,mb_type_general,sub_mb_type,end_of_MB_DEC,mbPartIdx,subMbPartIdx,compIdx,
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mb_num,mb_num_h,mb_num_v,mb_type_general,sub_mb_type,end_of_MB_DEC,mbPartIdx,subMbPartIdx,compIdx,
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MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,MBTypeGen_mbAddrD,
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MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,MBTypeGen_mbAddrD,
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mvx_mbAddrB_dout,mvy_mbAddrB_dout,mvx_mbAddrC_dout,mvy_mbAddrC_dout,mv_mbAddrB_rd_for_DF,
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mvx_mbAddrB_dout,mvy_mbAddrB_dout,mvx_mbAddrC_dout,mvy_mbAddrC_dout,mv_mbAddrB_rd_for_DF,
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skip_mv_calc,Is_skipMB_mv_calc,mvx_mbAddrA,mvy_mbAddrA,
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skip_mv_calc,Is_skipMB_mv_calc,mvx_mbAddrA,mvy_mbAddrA,
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mvx_mbAddrB_cs_n,mvx_mbAddrB_wr_n,mvx_mbAddrB_rd_addr,mvx_mbAddrB_wr_addr,mvx_mbAddrB_din,
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mvx_mbAddrB_cs_n,mvx_mbAddrB_wr_n,mvx_mbAddrB_rd_addr,mvx_mbAddrB_wr_addr,mvx_mbAddrB_din,
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mvy_mbAddrB_cs_n,mvy_mbAddrB_wr_n,mvy_mbAddrB_rd_addr,mvy_mbAddrB_wr_addr,mvy_mbAddrB_din,
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mvy_mbAddrB_cs_n,mvy_mbAddrB_wr_n,mvy_mbAddrB_rd_addr,mvy_mbAddrB_wr_addr,mvy_mbAddrB_din,
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mvx_mbAddrC_cs_n,mvx_mbAddrC_wr_n,mvx_mbAddrC_rd_addr,mvx_mbAddrC_wr_addr,mvx_mbAddrC_din,
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mvx_mbAddrC_cs_n,mvx_mbAddrC_wr_n,mvx_mbAddrC_rd_addr,mvx_mbAddrC_wr_addr,mvx_mbAddrC_din,
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mvy_mbAddrC_cs_n,mvy_mbAddrC_wr_n,mvy_mbAddrC_rd_addr,mvy_mbAddrC_wr_addr,mvy_mbAddrC_din,
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mvy_mbAddrC_cs_n,mvy_mbAddrC_wr_n,mvy_mbAddrC_rd_addr,mvy_mbAddrC_wr_addr,mvy_mbAddrC_din,
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mv_is16x16,
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mv_is16x16,
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mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,
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mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,
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mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3);
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mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3);
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input clk,reset_n;
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input clk,reset_n;
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input Is_skip_run_entry;
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input Is_skip_run_entry;
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input Is_skip_run_end;
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input Is_skip_run_end;
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input [3:0] slice_data_state;
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input [3:0] slice_data_state;
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input [2:0] mb_pred_state;
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input [2:0] mb_pred_state;
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input [1:0] sub_mb_pred_state;
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input [1:0] sub_mb_pred_state;
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input [7:0] mvd;
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input [7:0] mvd;
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input [6:0] mb_num;
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input [6:0] mb_num;
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input [3:0] mb_num_h;
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input [3:0] mb_num_h;
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input [3:0] mb_num_v;
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input [3:0] mb_num_v;
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input [3:0] mb_type_general;
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input [3:0] mb_type_general;
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input [1:0] sub_mb_type;
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input [1:0] sub_mb_type;
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input end_of_MB_DEC;
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input end_of_MB_DEC;
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input [1:0] mbPartIdx,subMbPartIdx;
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input [1:0] mbPartIdx,subMbPartIdx;
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input compIdx;
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input compIdx;
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input [1:0] MBTypeGen_mbAddrA;
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input [1:0] MBTypeGen_mbAddrA;
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input MBTypeGen_mbAddrD;
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input MBTypeGen_mbAddrD;
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input [21:0] MBTypeGen_mbAddrB_reg;
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input [21:0] MBTypeGen_mbAddrB_reg;
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input [31:0] mvx_mbAddrB_dout,mvy_mbAddrB_dout;
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input [31:0] mvx_mbAddrB_dout,mvy_mbAddrB_dout;
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input [7:0] mvx_mbAddrC_dout,mvy_mbAddrC_dout;
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input [7:0] mvx_mbAddrC_dout,mvy_mbAddrC_dout;
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input mv_mbAddrB_rd_for_DF;
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input mv_mbAddrB_rd_for_DF;
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output skip_mv_calc;
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output skip_mv_calc;
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output Is_skipMB_mv_calc;
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output Is_skipMB_mv_calc;
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output [31:0] mvx_mbAddrA,mvy_mbAddrA;
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output [31:0] mvx_mbAddrA,mvy_mbAddrA;
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output mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
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output mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
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output mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
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output mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
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output [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
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output [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
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output [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
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output [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
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output [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
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output [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
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output [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
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output [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
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output mv_is16x16;
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output mv_is16x16;
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output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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reg mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
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reg mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
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reg mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
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reg mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
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reg [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
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reg [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
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reg [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
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reg [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
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reg [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
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reg [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
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reg [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
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reg [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
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reg mv_is16x16;
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reg mv_is16x16;
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reg [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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reg [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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reg [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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reg [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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reg [7:0] mvpAx,mvpAy,mvpBx,mvpBy,mvpCx,mvpCy;
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reg [7:0] mvpAx,mvpAy,mvpBx,mvpBy,mvpCx,mvpCy;
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reg [31:0] mvx_mbAddrA,mvy_mbAddrA;
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reg [31:0] mvx_mbAddrA,mvy_mbAddrA;
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wire [7:0] mvx_mbAddrD,mvy_mbAddrD;
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wire [7:0] mvx_mbAddrD,mvy_mbAddrD;
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reg [7:0] mvpx,mvpy,mvx,mvy;
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reg [7:0] mvpx,mvpy,mvx,mvy;
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reg skip_mv_calc; //This signal is of reg type and is active for one cycle after end_of_MB_DEC and before
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reg skip_mv_calc; //This signal is of reg type and is active for one cycle after end_of_MB_DEC and before
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//trigger_blk4x4_inter_pred.It is used to direct motion vector prediction for skipped MB
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//trigger_blk4x4_inter_pred.It is used to direct motion vector prediction for skipped MB
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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skip_mv_calc <= 1'b0;
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skip_mv_calc <= 1'b0;
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else if (slice_data_state == `skip_run_duration && end_of_MB_DEC && !Is_skip_run_end)
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else if (slice_data_state == `skip_run_duration && end_of_MB_DEC && !Is_skip_run_end)
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skip_mv_calc <= 1'b1;
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skip_mv_calc <= 1'b1;
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else
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else
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skip_mv_calc <= 1'b0;
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skip_mv_calc <= 1'b0;
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wire Is_skipMB_mv_calc;
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wire Is_skipMB_mv_calc;
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assign Is_skipMB_mv_calc = Is_skip_run_entry | skip_mv_calc;
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assign Is_skipMB_mv_calc = Is_skip_run_entry | skip_mv_calc;
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reg [1:0] MBTypeGen_mbAddrB;
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reg [1:0] MBTypeGen_mbAddrB;
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reg [1:0] MBTypeGen_mbAddrC;
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reg [1:0] MBTypeGen_mbAddrC;
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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case (mb_num_h)
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case (mb_num_h)
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0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
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0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
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1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
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1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
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2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
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2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
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3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
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3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
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4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
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4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
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5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
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5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
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6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
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6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
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7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
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7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
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8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
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8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
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9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
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9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
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10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
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10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
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default:MBTypeGen_mbAddrB <= 0;
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default:MBTypeGen_mbAddrB <= 0;
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endcase
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endcase
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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case (mb_num_h)
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case (mb_num_h)
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0:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[3:2];
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0:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[3:2];
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1:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[5:4];
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1:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[5:4];
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2:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[7:6];
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2:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[7:6];
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3:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[9:8];
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3:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[9:8];
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4:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[11:10];
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4:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[11:10];
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5:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[13:12];
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5:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[13:12];
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6:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[15:14];
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6:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[15:14];
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7:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[17:16];
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7:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[17:16];
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8:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[19:18];
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8:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[19:18];
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9:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[21:20];
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9:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[21:20];
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default:MBTypeGen_mbAddrC <= 0;
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default:MBTypeGen_mbAddrC <= 0;
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endcase
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endcase
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wire refIdxL0_A; //Here refIdxL0_A == 1'b1 is equal to refIdxL0_A == -1 in Page122 of H.264 2003.5 standard
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wire refIdxL0_A; //Here refIdxL0_A == 1'b1 is equal to refIdxL0_A == -1 in Page122 of H.264 2003.5 standard
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wire refIdxL0_B; //Here refIdxL0_B == 1'b1 is equal to refIdxL0_B == -1 in Page122 of H.264 2003.5 standard
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wire refIdxL0_B; //Here refIdxL0_B == 1'b1 is equal to refIdxL0_B == -1 in Page122 of H.264 2003.5 standard
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reg refIdxL0_C; //Here refIdxL0_C == 1'b1 is equal to refIdxL0_C == -1 in Page122 of H.264 2003.5 standard
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reg refIdxL0_C; //Here refIdxL0_C == 1'b1 is equal to refIdxL0_C == -1 in Page122 of H.264 2003.5 standard
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assign refIdxL0_A = (
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assign refIdxL0_A = (
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//P_skip
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//P_skip
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(Is_skipMB_mv_calc ||
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(Is_skipMB_mv_calc ||
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//Inter16x16,Inter16x8,Inter8x16 left blk
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//Inter16x16,Inter16x8,Inter8x16 left blk
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(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_Inter16x8 || (mb_type_general == `MB_Inter8x16 && mbPartIdx == 0))) ||
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(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_Inter16x8 || (mb_type_general == `MB_Inter8x16 && mbPartIdx == 0))) ||
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//Inter8x8,left most blk
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//Inter8x8,left most blk
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(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 2) && (
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(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 2) && (
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sub_mb_type == 0 ||
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sub_mb_type == 0 ||
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sub_mb_type == 1 ||
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sub_mb_type == 1 ||
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(sub_mb_type == 2 && subMbPartIdx == 0) ||
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(sub_mb_type == 2 && subMbPartIdx == 0) ||
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(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 2))))) &&
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(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 2))))) &&
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(mb_num_h == 0 || MBTypeGen_mbAddrA[1] == 1))? 1'b1:1'b0;
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(mb_num_h == 0 || MBTypeGen_mbAddrA[1] == 1))? 1'b1:1'b0;
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assign refIdxL0_B = (
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assign refIdxL0_B = (
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//P_skip
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//P_skip
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(Is_skipMB_mv_calc ||
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(Is_skipMB_mv_calc ||
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//Inter16x16,Inter16x8 upper blk,Inter8x16
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//Inter16x16,Inter16x8 upper blk,Inter8x16
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(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || (mb_type_general == `MB_Inter16x8 && mbPartIdx == 0) || mb_type_general == `MB_Inter8x16)) ||
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(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || (mb_type_general == `MB_Inter16x8 && mbPartIdx == 0) || mb_type_general == `MB_Inter8x16)) ||
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//Inter8x8,left most blk
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//Inter8x8,left most blk
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(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 1) && (
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(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 1) && (
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sub_mb_type == 0 ||
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sub_mb_type == 0 ||
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sub_mb_type == 2 ||
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sub_mb_type == 2 ||
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(sub_mb_type == 1 && subMbPartIdx == 0) ||
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(sub_mb_type == 1 && subMbPartIdx == 0) ||
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(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 1))))) &&
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(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 1))))) &&
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(mb_num_v == 0 || MBTypeGen_mbAddrB[1] == 1))? 1'b1:1'b0;
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(mb_num_v == 0 || MBTypeGen_mbAddrB[1] == 1))? 1'b1:1'b0;
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always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or mb_num_v or mb_num_h
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always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or mb_num_v or mb_num_h
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or sub_mb_type or mbPartIdx or subMbPartIdx or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
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or sub_mb_type or mbPartIdx or subMbPartIdx or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
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or refIdxL0_A or refIdxL0_B)
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or refIdxL0_A or refIdxL0_B)
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//P_skip,Inter16x16
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//P_skip,Inter16x16
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if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16))
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if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16))
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begin
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begin
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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if (mb_num_v == 0) refIdxL0_C <= 1'b1;
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else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0;
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else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8)
|
begin
|
begin
|
if (mbPartIdx == 0) //upper blk
|
if (mbPartIdx == 0) //upper blk
|
begin
|
begin
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0;
|
else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
end
|
end
|
else //bottom blk
|
else //bottom blk
|
refIdxL0_C <= refIdxL0_A;
|
refIdxL0_C <= refIdxL0_A;
|
end
|
end
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16)
|
begin
|
begin
|
if (mbPartIdx == 0) //left blk
|
if (mbPartIdx == 0) //left blk
|
refIdxL0_C <= refIdxL0_B;
|
refIdxL0_C <= refIdxL0_B;
|
else //right blk
|
else //right blk
|
begin
|
begin
|
if (mb_num_v == 0 || mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
if (mb_num_v == 0 || mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
end
|
end
|
end
|
end
|
//Inter8x8 and below
|
//Inter8x8 and below
|
else if (sub_mb_pred_state == `sub_mvd_l0_s)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
2'b00: //left-top 8x8 blk
|
2'b00: //left-top 8x8 blk
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:refIdxL0_C <= refIdxL0_B;
|
0:refIdxL0_C <= refIdxL0_B;
|
1:refIdxL0_C <= (subMbPartIdx == 0)? refIdxL0_B:refIdxL0_A;
|
1:refIdxL0_C <= (subMbPartIdx == 0)? refIdxL0_B:refIdxL0_A;
|
2:refIdxL0_C <= refIdxL0_B;
|
2:refIdxL0_C <= refIdxL0_B;
|
3:
|
3:
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0,1:refIdxL0_C <= refIdxL0_B;
|
0,1:refIdxL0_C <= refIdxL0_B;
|
2,3:refIdxL0_C <= 1'b0;
|
2,3:refIdxL0_C <= 1'b0;
|
endcase
|
endcase
|
endcase
|
endcase
|
2'b01: //right-top 8x8 blk
|
2'b01: //right-top 8x8 blk
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0: //8x8
|
0: //8x8
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
1: //8x4
|
1: //8x4
|
if (subMbPartIdx == 0)
|
if (subMbPartIdx == 0)
|
begin
|
begin
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
end
|
end
|
else
|
else
|
refIdxL0_C <= 1'b0;
|
refIdxL0_C <= 1'b0;
|
2: //4x8
|
2: //4x8
|
if (subMbPartIdx == 0) refIdxL0_C <= refIdxL0_B;
|
if (subMbPartIdx == 0) refIdxL0_C <= refIdxL0_B;
|
else
|
else
|
begin
|
begin
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
end
|
end
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:refIdxL0_C <= refIdxL0_B;
|
0:refIdxL0_C <= refIdxL0_B;
|
1:
|
1:
|
begin
|
begin
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
if (mb_num_v == 0) refIdxL0_C <= 1'b1;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
|
end
|
end
|
2,3:refIdxL0_C <= 1'b0;
|
2,3:refIdxL0_C <= 1'b0;
|
endcase
|
endcase
|
endcase
|
endcase
|
2'b10: //left-bottom 8x8 blk
|
2'b10: //left-bottom 8x8 blk
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:refIdxL0_C <= 1'b0;
|
0:refIdxL0_C <= 1'b0;
|
1:refIdxL0_C <= (subMbPartIdx == 0)? 1'b0:refIdxL0_A;
|
1:refIdxL0_C <= (subMbPartIdx == 0)? 1'b0:refIdxL0_A;
|
2:refIdxL0_C <= 1'b0;
|
2:refIdxL0_C <= 1'b0;
|
3:refIdxL0_C <= 1'b0;
|
3:refIdxL0_C <= 1'b0;
|
endcase
|
endcase
|
2'b11: //right-bottom 8x8 blk
|
2'b11: //right-bottom 8x8 blk
|
refIdxL0_C <= 1'b0;
|
refIdxL0_C <= 1'b0;
|
endcase
|
endcase
|
else
|
else
|
refIdxL0_C <= 1'b0;
|
refIdxL0_C <= 1'b0;
|
|
|
//-------------
|
//-------------
|
//mvpAx
|
//mvpAx
|
//-------------
|
//-------------
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or mvx_mbAddrA or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
or mvx_mbAddrA or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
//P_skip or Inter16x16
|
//P_skip or Inter16x16
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
begin
|
begin
|
if (mbPartIdx == 0)
|
if (mbPartIdx == 0)
|
mvpAx <= {8{refIdxL0_B}} & mvx_mbAddrA[7:0];
|
mvpAx <= {8{refIdxL0_B}} & mvx_mbAddrA[7:0];
|
else
|
else
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
end
|
end
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
begin
|
begin
|
if (mbPartIdx == 0)
|
if (mbPartIdx == 0)
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
else
|
else
|
mvpAx <= {8{refIdxL0_C}} & mvx_CurrMb0[15:8];
|
mvpAx <= {8{refIdxL0_C}} & mvx_CurrMb0[15:8];
|
end
|
end
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) //sub_mb_pred
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) //sub_mb_pred
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
|
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
1:mvpAx <= mvx_CurrMb0[7:0];
|
1:mvpAx <= mvx_CurrMb0[7:0];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
|
1:mvpAx <= mvx_CurrMb0[7:0];
|
1:mvpAx <= mvx_CurrMb0[7:0];
|
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
|
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
|
3:mvpAx <= mvx_CurrMb0[23:16];
|
3:mvpAx <= mvx_CurrMb0[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAx <= mvx_CurrMb0[15:8];
|
0:mvpAx <= mvx_CurrMb0[15:8];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb0[31:24];
|
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb0[31:24];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb1[7:0];
|
0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb1[7:0];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= mvx_CurrMb0[15:8] ; 1:mvpAx <= mvx_CurrMb1[7:0];
|
0:mvpAx <= mvx_CurrMb0[15:8] ; 1:mvpAx <= mvx_CurrMb1[7:0];
|
2:mvpAx <= mvx_CurrMb0[31:24]; 3:mvpAx <= mvx_CurrMb1[23:16];
|
2:mvpAx <= mvx_CurrMb0[31:24]; 3:mvpAx <= mvx_CurrMb1[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
|
1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
1:mvpAx <= mvx_CurrMb2[7:0];
|
1:mvpAx <= mvx_CurrMb2[7:0];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
|
1:mvpAx <= mvx_CurrMb2[7:0];
|
1:mvpAx <= mvx_CurrMb2[7:0];
|
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
|
2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
|
3:mvpAx <= mvx_CurrMb2[23:16];
|
3:mvpAx <= mvx_CurrMb2[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAx <= mvx_CurrMb2[15:8];
|
0:mvpAx <= mvx_CurrMb2[15:8];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb2[31:24];
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb2[31:24];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0];
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0];
|
default:mvpAx <= 0;
|
default:mvpAx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0];
|
0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0];
|
2:mvpAx <= mvx_CurrMb2[31:24]; 3:mvpAx <= mvx_CurrMb3[23:16];
|
2:mvpAx <= mvx_CurrMb2[31:24]; 3:mvpAx <= mvx_CurrMb3[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
mvpAx <= 0;
|
mvpAx <= 0;
|
|
|
//-------------
|
//-------------
|
//mvpAy
|
//mvpAy
|
//-------------
|
//-------------
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or mvy_mbAddrA or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
or mvy_mbAddrA or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
//P_skip or Inter16x16
|
//P_skip or Inter16x16
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
begin
|
begin
|
if (mbPartIdx == 0)
|
if (mbPartIdx == 0)
|
mvpAy <= {8{refIdxL0_B}} & mvy_mbAddrA[7:0];
|
mvpAy <= {8{refIdxL0_B}} & mvy_mbAddrA[7:0];
|
else
|
else
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
end
|
end
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
begin
|
begin
|
if (mbPartIdx == 0)
|
if (mbPartIdx == 0)
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
else
|
else
|
mvpAy <= {8{refIdxL0_C}} & mvy_CurrMb0[15:8];
|
mvpAy <= {8{refIdxL0_C}} & mvy_CurrMb0[15:8];
|
end
|
end
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) //sub_mb_pred
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) //sub_mb_pred
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8];
|
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
1:mvpAy <= mvy_CurrMb0[7:0];
|
1:mvpAy <= mvy_CurrMb0[7:0];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0];
|
1:mvpAy <= mvy_CurrMb0[7:0];
|
1:mvpAy <= mvy_CurrMb0[7:0];
|
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8];
|
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8];
|
3:mvpAy <= mvy_CurrMb0[23:16];
|
3:mvpAy <= mvy_CurrMb0[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAy <= mvy_CurrMb0[15:8];
|
0:mvpAy <= mvy_CurrMb0[15:8];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb0[31:24];
|
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb0[31:24];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb1[7:0];
|
0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb1[7:0];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= mvy_CurrMb0[15:8] ; 1:mvpAy <= mvy_CurrMb1[7:0];
|
0:mvpAy <= mvy_CurrMb0[15:8] ; 1:mvpAy <= mvy_CurrMb1[7:0];
|
2:mvpAy <= mvy_CurrMb0[31:24]; 3:mvpAy <= mvy_CurrMb1[23:16];
|
2:mvpAy <= mvy_CurrMb0[31:24]; 3:mvpAy <= mvy_CurrMb1[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24];
|
1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
1:mvpAy <= mvy_CurrMb2[7:0];
|
1:mvpAy <= mvy_CurrMb2[7:0];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16];
|
1:mvpAy <= mvy_CurrMb2[7:0];
|
1:mvpAy <= mvy_CurrMb2[7:0];
|
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24];
|
2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24];
|
3:mvpAy <= mvy_CurrMb2[23:16];
|
3:mvpAy <= mvy_CurrMb2[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpAy <= mvy_CurrMb2[15:8];
|
0:mvpAy <= mvy_CurrMb2[15:8];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb2[31:24];
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb2[31:24];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0];
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0];
|
default:mvpAy <= 0;
|
default:mvpAy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0];
|
0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0];
|
2:mvpAy <= mvy_CurrMb2[31:24]; 3:mvpAy <= mvy_CurrMb3[23:16];
|
2:mvpAy <= mvy_CurrMb2[31:24]; 3:mvpAy <= mvy_CurrMb3[23:16];
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
mvpAy <= 0;
|
mvpAy <= 0;
|
//-------------
|
//-------------
|
//mvpBx
|
//mvpBx
|
//-------------
|
//-------------
|
//if B is not available,it can be predicted from A when both B and C are not available
|
//if B is not available,it can be predicted from A when both B and C are not available
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type
|
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1]
|
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1]
|
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
//P_skip or Inter16x16
|
//P_skip or Inter16x16
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
begin
|
begin
|
if (mb_num == 0) mvpBx <= 0;
|
if (mb_num == 0) mvpBx <= 0;
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
begin
|
begin
|
if (mbPartIdx == 0)
|
if (mbPartIdx == 0)
|
begin
|
begin
|
if (mb_num == 0) mvpBx <= 0;
|
if (mb_num == 0) mvpBx <= 0;
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
end
|
end
|
else //for bottom 8x8 block when mbAddrA is not available
|
else //for bottom 8x8 block when mbAddrA is not available
|
mvpBx <= (!refIdxL0_A)? 0:mvx_CurrMb0[23:16];
|
mvpBx <= (!refIdxL0_A)? 0:mvx_CurrMb0[23:16];
|
end
|
end
|
//Inter8x16:for left 8x8 block when mbAddrA is not available
|
//Inter8x16:for left 8x8 block when mbAddrA is not available
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
begin
|
begin
|
if (mbPartIdx == 0) //left blk
|
if (mbPartIdx == 0) //left blk
|
mvpBx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[31:24]:0;
|
mvpBx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[31:24]:0;
|
else //right blk
|
else //right blk
|
case (!refIdxL0_C)
|
case (!refIdxL0_C)
|
1'b1:mvpBx <= 0;
|
1'b1:mvpBx <= 0;
|
1'b0:
|
1'b0:
|
if (mb_num_v == 0)
|
if (mb_num_v == 0)
|
mvpBx <= mvx_CurrMb0[7:0];
|
mvpBx <= mvx_CurrMb0[7:0];
|
else
|
else
|
mvpBx <= (!refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0;
|
mvpBx <= (!refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0;
|
endcase
|
endcase
|
end
|
end
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:if (mb_num == 0) mvpBx <= 0;
|
0:if (mb_num == 0) mvpBx <= 0;
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpBx <= 0;
|
0:if (mb_num == 0) mvpBx <= 0;
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
1:mvpBx <= mvx_CurrMb0[7:0];
|
1:mvpBx <= mvx_CurrMb0[7:0];
|
default:mvpBx <= 0;
|
default:mvpBx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpBx <= 0;
|
0:if (mb_num == 0) mvpBx <= 0;
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
default:mvpBx <= 0;
|
default:mvpBx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpBx <= 0;
|
0:if (mb_num == 0) mvpBx <= 0;
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24];
|
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
2:mvpBx <= mvx_CurrMb0[7:0];
|
2:mvpBx <= mvx_CurrMb0[7:0];
|
3:mvpBx <= mvx_CurrMb0[15:8];
|
3:mvpBx <= mvx_CurrMb0[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
1:mvpBx <= mvx_CurrMb1[7:0];
|
1:mvpBx <= mvx_CurrMb1[7:0];
|
default:mvpBx <= 0;
|
default:mvpBx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]);
|
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]);
|
default:mvpBx <= 0;
|
default:mvpBx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]);
|
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]);
|
1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]);
|
2:mvpBx <= mvx_CurrMb1[7:0];
|
2:mvpBx <= mvx_CurrMb1[7:0];
|
3:mvpBx <= mvx_CurrMb1[15:8];
|
3:mvpBx <= mvx_CurrMb1[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpBx <= mvx_CurrMb0[23:16];
|
0:mvpBx <= mvx_CurrMb0[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb2[7:0]; default:mvpBx <= 0;
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb2[7:0]; default:mvpBx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; default:mvpBx <= 0;
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; default:mvpBx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24];
|
0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24];
|
2:mvpBx <= mvx_CurrMb2[7:0]; 3:mvpBx <= mvx_CurrMb2[15:8];
|
2:mvpBx <= mvx_CurrMb2[7:0]; 3:mvpBx <= mvx_CurrMb2[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpBx <= mvx_CurrMb1[23:16];
|
0:mvpBx <= mvx_CurrMb1[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb3[7:0]; default:mvpBx <= 0;
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb3[7:0]; default:mvpBx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; default:mvpBx <= 0;
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; default:mvpBx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24];
|
0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24];
|
2:mvpBx <= mvx_CurrMb3[7:0]; 3:mvpBx <= mvx_CurrMb3[15:8];
|
2:mvpBx <= mvx_CurrMb3[7:0]; 3:mvpBx <= mvx_CurrMb3[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
mvpBx <= 0;
|
mvpBx <= 0;
|
//-------------
|
//-------------
|
//mvpBy
|
//mvpBy
|
//-------------
|
//-------------
|
//if B is not available,it can be predicted from A when both B and C are not available
|
//if B is not available,it can be predicted from A when both B and C are not available
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type
|
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1]
|
or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1]
|
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
//P_skip or Inter16x16
|
//P_skip or Inter16x16
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
begin
|
begin
|
if (mb_num == 0) mvpBy <= 0;
|
if (mb_num == 0) mvpBy <= 0;
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
begin
|
begin
|
if (mbPartIdx == 0) //upper 8x8 block
|
if (mbPartIdx == 0) //upper 8x8 block
|
begin
|
begin
|
if (mb_num == 0) mvpBy <= 0;
|
if (mb_num == 0) mvpBy <= 0;
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
end
|
end
|
else //for bottom 8x8 block when mbAddrA is not available
|
else //for bottom 8x8 block when mbAddrA is not available
|
mvpBy <= (!refIdxL0_A)? 0:mvy_CurrMb0[23:16];
|
mvpBy <= (!refIdxL0_A)? 0:mvy_CurrMb0[23:16];
|
end
|
end
|
//Inter8x16:for left 8x8 block when mbAddrA is not available
|
//Inter8x16:for left 8x8 block when mbAddrA is not available
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
begin
|
begin
|
if (mbPartIdx == 0) //left blk
|
if (mbPartIdx == 0) //left blk
|
mvpBy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[31:24]:0;
|
mvpBy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[31:24]:0;
|
else //right blk
|
else //right blk
|
case (!refIdxL0_C)
|
case (!refIdxL0_C)
|
1'b1:mvpBy <= 0;
|
1'b1:mvpBy <= 0;
|
1'b0:
|
1'b0:
|
if (mb_num_v == 0)
|
if (mb_num_v == 0)
|
mvpBy <= mvy_CurrMb0[7:0];
|
mvpBy <= mvy_CurrMb0[7:0];
|
else
|
else
|
mvpBy <= (!refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0;
|
mvpBy <= (!refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0;
|
endcase
|
endcase
|
end
|
end
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:if (mb_num == 0) mvpBy <= 0;
|
0:if (mb_num == 0) mvpBy <= 0;
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpBy <= 0;
|
0:if (mb_num == 0) mvpBy <= 0;
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
1:mvpBy <= mvy_CurrMb0[7:0];
|
1:mvpBy <= mvy_CurrMb0[7:0];
|
default:mvpBy <= 0;
|
default:mvpBy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpBy <= 0;
|
0:if (mb_num == 0) mvpBy <= 0;
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
default:mvpBy <= 0;
|
default:mvpBy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpBy <= 0;
|
0:if (mb_num == 0) mvpBy <= 0;
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24];
|
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
2:mvpBy <= mvy_CurrMb0[7:0];
|
2:mvpBy <= mvy_CurrMb0[7:0];
|
3:mvpBy <= mvy_CurrMb0[15:8];
|
3:mvpBy <= mvy_CurrMb0[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
1:mvpBy <= mvy_CurrMb1[7:0];
|
1:mvpBy <= mvy_CurrMb1[7:0];
|
default:mvpBy <= 0;
|
default:mvpBy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]);
|
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]);
|
default:mvpBy <= 0;
|
default:mvpBy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]);
|
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]);
|
1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]);
|
2:mvpBy <= mvy_CurrMb1[7:0];
|
2:mvpBy <= mvy_CurrMb1[7:0];
|
3:mvpBy <= mvy_CurrMb1[15:8];
|
3:mvpBy <= mvy_CurrMb1[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpBy <= mvy_CurrMb0[23:16];
|
0:mvpBy <= mvy_CurrMb0[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb2[7:0]; default:mvpBy <= 0;
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb2[7:0]; default:mvpBy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; default:mvpBy <= 0;
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; default:mvpBy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24];
|
0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24];
|
2:mvpBy <= mvy_CurrMb2[7:0]; 3:mvpBy <= mvy_CurrMb2[15:8];
|
2:mvpBy <= mvy_CurrMb2[7:0]; 3:mvpBy <= mvy_CurrMb2[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpBy <= mvy_CurrMb1[23:16];
|
0:mvpBy <= mvy_CurrMb1[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb3[7:0]; default:mvpBy <= 0;
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb3[7:0]; default:mvpBy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; default:mvpBy <= 0;
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; default:mvpBy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24];
|
0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24];
|
2:mvpBy <= mvy_CurrMb3[7:0]; 3:mvpBy <= mvy_CurrMb3[15:8];
|
2:mvpBy <= mvy_CurrMb3[7:0]; 3:mvpBy <= mvy_CurrMb3[15:8];
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
mvpBy <= 0;
|
mvpBy <= 0;
|
//-------------
|
//-------------
|
//mvpCx
|
//mvpCx
|
//-------------
|
//-------------
|
//if C is not available,it can be predicted from D,then from A
|
//if C is not available,it can be predicted from D,then from A
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
|
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
|
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_mbAddrC_dout or mvx_mbAddrD
|
or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_mbAddrC_dout or mvx_mbAddrD
|
or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
//P_skip,Inter16x16
|
//P_skip,Inter16x16
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
begin
|
begin
|
if (mb_num == 0) mvpCx <= 0;
|
if (mb_num == 0) mvpCx <= 0;
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrD == 1)? 0:mvx_mbAddrD;
|
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrD == 1)? 0:mvx_mbAddrD;
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
begin
|
begin
|
if (mbPartIdx == 0)
|
if (mbPartIdx == 0)
|
mvpCx <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvx_mbAddrD:mvx_mbAddrC_dout):0;
|
mvpCx <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvx_mbAddrD:mvx_mbAddrC_dout):0;
|
else
|
else
|
mvpCx <= 0;
|
mvpCx <= 0;
|
end
|
end
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
begin
|
begin
|
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived
|
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived
|
if (mbPartIdx == 0) //left blk
|
if (mbPartIdx == 0) //left blk
|
mvpCx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0;
|
mvpCx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0;
|
else //right blk
|
else //right blk
|
begin
|
begin
|
if (mb_num == 0) mvpCx <= 0;
|
if (mb_num == 0) mvpCx <= 0;
|
else if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
else if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
end
|
end
|
end
|
end
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:if (mb_num == 0) mvpCx <= 0;
|
0:if (mb_num == 0) mvpCx <= 0;
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpCx <= 0;
|
0:if (mb_num == 0) mvpCx <= 0;
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
1:if (mb_num_h == 0) mvpCx <= 0;
|
1:if (mb_num_h == 0) mvpCx <= 0;
|
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD;
|
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD;
|
default:mvpCx <= 0;
|
default:mvpCx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpCx <= 0;
|
0:if (mb_num == 0) mvpCx <= 0;
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
1:if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_CurrMb0[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
default:mvpCx <= 0;
|
default:mvpCx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpCx <= 0;
|
0:if (mb_num == 0) mvpCx <= 0;
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
2:mvpCx <= mvx_CurrMb0[15:8]; //always available
|
2:mvpCx <= mvx_CurrMb0[15:8]; //always available
|
3:mvpCx <= mvx_CurrMb0[7:0]; //always from D
|
3:mvpCx <= mvx_CurrMb0[7:0]; //always from D
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16];
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
1:mvpCx <= mvx_CurrMb0[15:8]; //C is always unavailable,D is always available
|
1:mvpCx <= mvx_CurrMb0[15:8]; //C is always unavailable,D is always available
|
default:mvpCx <= 0;
|
default:mvpCx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0];
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0];
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0];
|
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
default:mvpCx <= 0;
|
default:mvpCx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0];
|
else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0];
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0];
|
1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0];
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8];
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout;
|
2:mvpCx <= mvx_CurrMb1[15:8];
|
2:mvpCx <= mvx_CurrMb1[15:8];
|
3:mvpCx <= mvx_CurrMb1[7:0];
|
3:mvpCx <= mvx_CurrMb1[7:0];
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpCx <= mvx_CurrMb1[23:16];
|
0:mvpCx <= mvx_CurrMb1[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCx <= mvx_CurrMb1[23:16];
|
0:mvpCx <= mvx_CurrMb1[23:16];
|
1:if (mb_num_h == 0) mvpCx <= 0;
|
1:if (mb_num_h == 0) mvpCx <= 0;
|
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD;
|
else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD;
|
default:mvpCx <= 0;
|
default:mvpCx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0;
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16];
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16];
|
2:mvpCx <= mvx_CurrMb2[15:8]; 3:mvpCx <= mvx_CurrMb2[7:0];
|
2:mvpCx <= mvx_CurrMb2[15:8]; 3:mvpCx <= mvx_CurrMb2[7:0];
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpCx <= mvx_CurrMb0[31:24];
|
0:mvpCx <= mvx_CurrMb0[31:24];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb2[15:8]; default:mvpCx <= 0;
|
0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb2[15:8]; default:mvpCx <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0;
|
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16];
|
0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16];
|
2:mvpCx <= mvx_CurrMb3[15:8]; 3:mvpCx <= mvx_CurrMb3[7:0];
|
2:mvpCx <= mvx_CurrMb3[15:8]; 3:mvpCx <= mvx_CurrMb3[7:0];
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
mvpCx <= 0;
|
mvpCx <= 0;
|
//-------------
|
//-------------
|
//mvpCy
|
//mvpCy
|
//-------------
|
//-------------
|
//if C is not available,it can be predicted from D,then from A
|
//if C is not available,it can be predicted from D,then from A
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v
|
always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx
|
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
|
or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
|
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_mbAddrC_dout or mvy_mbAddrD
|
or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_mbAddrC_dout or mvy_mbAddrD
|
or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
//P_skip,Inter16x16
|
//P_skip,Inter16x16
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
begin
|
begin
|
if (mb_num == 0) mvpCy <= 0;
|
if (mb_num == 0) mvpCy <= 0;
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrD == 1)? 0:mvy_mbAddrD;
|
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrD == 1)? 0:mvy_mbAddrD;
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
begin
|
begin
|
if (mbPartIdx == 0)
|
if (mbPartIdx == 0)
|
mvpCy <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvy_mbAddrD:mvy_mbAddrC_dout):0;
|
mvpCy <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvy_mbAddrD:mvy_mbAddrC_dout):0;
|
else
|
else
|
mvpCy <= 0;
|
mvpCy <= 0;
|
end
|
end
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
begin
|
begin
|
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived
|
//when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived
|
if (mbPartIdx == 0) //left blk
|
if (mbPartIdx == 0) //left blk
|
mvpCy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0;
|
mvpCy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0;
|
else //right blk
|
else //right blk
|
begin
|
begin
|
if (mb_num == 0) mvpCy <= 0;
|
if (mb_num == 0) mvpCy <= 0;
|
else if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
else if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
end
|
end
|
end
|
end
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:if (mb_num == 0) mvpCy <= 0;
|
0:if (mb_num == 0) mvpCy <= 0;
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpCy <= 0;
|
0:if (mb_num == 0) mvpCy <= 0;
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
1:if (mb_num_h == 0) mvpCy <= 0;
|
1:if (mb_num_h == 0) mvpCy <= 0;
|
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD;
|
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD;
|
default:mvpCy <= 0;
|
default:mvpCy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpCy <= 0;
|
0:if (mb_num == 0) mvpCy <= 0;
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
1:if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_CurrMb0[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
default:mvpCy <= 0;
|
default:mvpCy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num == 0) mvpCy <= 0;
|
0:if (mb_num == 0) mvpCy <= 0;
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[7:0];
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
2:mvpCy <= mvy_CurrMb0[15:8]; //always available
|
2:mvpCy <= mvy_CurrMb0[15:8]; //always available
|
3:mvpCy <= mvy_CurrMb0[7:0]; //always from D
|
3:mvpCy <= mvy_CurrMb0[7:0]; //always from D
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16];
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
1:mvpCy <= mvy_CurrMb0[15:8]; //C is always unavailable,D is always available
|
1:mvpCy <= mvy_CurrMb0[15:8]; //C is always unavailable,D is always available
|
default:mvpCy <= 0;
|
default:mvpCy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0];
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0];
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0];
|
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
default:mvpCy <= 0;
|
default:mvpCy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0];
|
else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0];
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0];
|
1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0];
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8];
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout;
|
2:mvpCy <= mvy_CurrMb1[15:8];
|
2:mvpCy <= mvy_CurrMb1[15:8];
|
3:mvpCy <= mvy_CurrMb1[7:0];
|
3:mvpCy <= mvy_CurrMb1[7:0];
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpCy <= mvy_CurrMb1[23:16];
|
0:mvpCy <= mvy_CurrMb1[23:16];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCy <= mvy_CurrMb1[23:16];
|
0:mvpCy <= mvy_CurrMb1[23:16];
|
1:if (mb_num_h == 0) mvpCy <= 0;
|
1:if (mb_num_h == 0) mvpCy <= 0;
|
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD;
|
else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD;
|
default:mvpCy <= 0;
|
default:mvpCy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0;
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16];
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16];
|
2:mvpCy <= mvy_CurrMb2[15:8]; 3:mvpCy <= mvy_CurrMb2[7:0];
|
2:mvpCy <= mvy_CurrMb2[15:8]; 3:mvpCy <= mvy_CurrMb2[7:0];
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvpCy <= mvy_CurrMb0[31:24];
|
0:mvpCy <= mvy_CurrMb0[31:24];
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb2[15:8]; default:mvpCy <= 0;
|
0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb2[15:8]; default:mvpCy <= 0;
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0;
|
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0;
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16];
|
0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16];
|
2:mvpCy <= mvy_CurrMb3[15:8]; 3:mvpCy <= mvy_CurrMb3[7:0];
|
2:mvpCy <= mvy_CurrMb3[15:8]; 3:mvpCy <= mvy_CurrMb3[7:0];
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
mvpCy <= 0;
|
mvpCy <= 0;
|
//------------------------------------------------
|
//------------------------------------------------
|
//obtain motion vector prediction for current Blk
|
//obtain motion vector prediction for current Blk
|
//------------------------------------------------
|
//------------------------------------------------
|
wire [8:0] sub_ABx,sub_ACx,sub_BCx;
|
wire [8:0] sub_ABx,sub_ACx,sub_BCx;
|
wire flag_ABx,flag_ACx,flag_BCx;
|
wire flag_ABx,flag_ACx,flag_BCx;
|
assign sub_ABx = {mvpAx[7],mvpAx[7:0]} - {mvpBx[7],mvpBx[7:0]};
|
assign sub_ABx = {mvpAx[7],mvpAx[7:0]} - {mvpBx[7],mvpBx[7:0]};
|
assign sub_ACx = {mvpAx[7],mvpAx[7:0]} - {mvpCx[7],mvpCx[7:0]};
|
assign sub_ACx = {mvpAx[7],mvpAx[7:0]} - {mvpCx[7],mvpCx[7:0]};
|
assign sub_BCx = {mvpBx[7],mvpBx[7:0]} - {mvpCx[7],mvpCx[7:0]};
|
assign sub_BCx = {mvpBx[7],mvpBx[7:0]} - {mvpCx[7],mvpCx[7:0]};
|
assign flag_ABx = sub_ABx[8];
|
assign flag_ABx = sub_ABx[8];
|
assign flag_ACx = sub_ACx[8];
|
assign flag_ACx = sub_ACx[8];
|
assign flag_BCx = sub_BCx[8];
|
assign flag_BCx = sub_BCx[8];
|
|
|
reg [7:0] mvpx_median;
|
reg [7:0] mvpx_median;
|
always @ (flag_ABx or flag_ACx or flag_BCx or mvpAx or mvpBx or mvpCx)
|
always @ (flag_ABx or flag_ACx or flag_BCx or mvpAx or mvpBx or mvpCx)
|
if (((flag_ABx == 1'b1) && (flag_ACx == 1'b0)) || ((flag_ABx == 1'b0) && (flag_ACx == 1'b1)))
|
if (((flag_ABx == 1'b1) && (flag_ACx == 1'b0)) || ((flag_ABx == 1'b0) && (flag_ACx == 1'b1)))
|
mvpx_median <= mvpAx;
|
mvpx_median <= mvpAx;
|
else if (((flag_ABx == 1'b0) && (flag_BCx == 1'b0)) || ((flag_ABx == 1'b1) && (flag_BCx == 1'b1)))
|
else if (((flag_ABx == 1'b0) && (flag_BCx == 1'b0)) || ((flag_ABx == 1'b1) && (flag_BCx == 1'b1)))
|
mvpx_median <= mvpBx;
|
mvpx_median <= mvpBx;
|
else
|
else
|
mvpx_median <= mvpCx;
|
mvpx_median <= mvpCx;
|
|
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAx or mvpBx or mvpCx or mvpx_median)
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAx or mvpBx or mvpCx or mvpx_median)
|
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C})
|
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C})
|
3'b011:mvpx <= mvpAx;
|
3'b011:mvpx <= mvpAx;
|
3'b101:mvpx <= mvpBx;
|
3'b101:mvpx <= mvpBx;
|
3'b110:mvpx <= mvpCx;
|
3'b110:mvpx <= mvpCx;
|
default:mvpx <= mvpx_median;
|
default:mvpx <= mvpx_median;
|
endcase
|
endcase
|
|
|
wire [8:0] sub_ABy,sub_ACy,sub_BCy;
|
wire [8:0] sub_ABy,sub_ACy,sub_BCy;
|
wire flag_ABy,flag_ACy,flag_BCy;
|
wire flag_ABy,flag_ACy,flag_BCy;
|
assign sub_ABy = {mvpAy[7],mvpAy[7:0]} - {mvpBy[7],mvpBy[7:0]};
|
assign sub_ABy = {mvpAy[7],mvpAy[7:0]} - {mvpBy[7],mvpBy[7:0]};
|
assign sub_ACy = {mvpAy[7],mvpAy[7:0]} - {mvpCy[7],mvpCy[7:0]};
|
assign sub_ACy = {mvpAy[7],mvpAy[7:0]} - {mvpCy[7],mvpCy[7:0]};
|
assign sub_BCy = {mvpBy[7],mvpBy[7:0]} - {mvpCy[7],mvpCy[7:0]};
|
assign sub_BCy = {mvpBy[7],mvpBy[7:0]} - {mvpCy[7],mvpCy[7:0]};
|
assign flag_ABy = sub_ABy[8];
|
assign flag_ABy = sub_ABy[8];
|
assign flag_ACy = sub_ACy[8];
|
assign flag_ACy = sub_ACy[8];
|
assign flag_BCy = sub_BCy[8];
|
assign flag_BCy = sub_BCy[8];
|
|
|
reg [7:0] mvpy_median;
|
reg [7:0] mvpy_median;
|
always @ (flag_ABy or flag_ACy or flag_BCy or mvpAy or mvpBy or mvpCy)
|
always @ (flag_ABy or flag_ACy or flag_BCy or mvpAy or mvpBy or mvpCy)
|
if (((flag_ABy == 1'b1) && (flag_ACy == 1'b0)) || ((flag_ABy == 1'b0) && (flag_ACy == 1'b1)))
|
if (((flag_ABy == 1'b1) && (flag_ACy == 1'b0)) || ((flag_ABy == 1'b0) && (flag_ACy == 1'b1)))
|
mvpy_median <= mvpAy;
|
mvpy_median <= mvpAy;
|
else if (((flag_ABy == 1'b0) && (flag_BCy == 1'b0)) || ((flag_ABy == 1'b1) && (flag_BCy == 1'b1)))
|
else if (((flag_ABy == 1'b0) && (flag_BCy == 1'b0)) || ((flag_ABy == 1'b1) && (flag_BCy == 1'b1)))
|
mvpy_median <= mvpBy;
|
mvpy_median <= mvpBy;
|
else
|
else
|
mvpy_median <= mvpCy;
|
mvpy_median <= mvpCy;
|
|
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAy or mvpBy or mvpCy or mvpy_median)
|
always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAy or mvpBy or mvpCy or mvpy_median)
|
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C})
|
case ({refIdxL0_A,refIdxL0_B,refIdxL0_C})
|
3'b011:mvpy <= mvpAy;
|
3'b011:mvpy <= mvpAy;
|
3'b101:mvpy <= mvpBy;
|
3'b101:mvpy <= mvpBy;
|
3'b110:mvpy <= mvpCy;
|
3'b110:mvpy <= mvpCy;
|
default:mvpy <= mvpy_median;
|
default:mvpy <= mvpy_median;
|
endcase
|
endcase
|
|
|
always @ (Is_skipMB_mv_calc or mb_num_h or mb_num_v or mb_pred_state or sub_mb_pred_state or compIdx or mvpx or mvpy
|
always @ (Is_skipMB_mv_calc or mb_num_h or mb_num_v or mb_pred_state or sub_mb_pred_state or compIdx or mvpx or mvpy
|
or mvd or mvpAx or mvpBx or mvpCx or mvpAy or mvpBy or mvpCy or mb_type_general or mbPartIdx
|
or mvd or mvpAx or mvpBx or mvpCx or mvpAy or mvpBy or mvpCy or mb_type_general or mbPartIdx
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_B or refIdxL0_C)
|
if (Is_skipMB_mv_calc)
|
if (Is_skipMB_mv_calc)
|
begin
|
begin
|
//Refer to Page113,section 8.4.1.1 of H.264/AVC 2003.05 standard
|
//Refer to Page113,section 8.4.1.1 of H.264/AVC 2003.05 standard
|
if (mb_num_h == 0 || mb_num_v == 0 || (refIdxL0_A == 0 && mvpAx == 0 && mvpAy == 0) ||
|
if (mb_num_h == 0 || mb_num_v == 0 || (refIdxL0_A == 0 && mvpAx == 0 && mvpAy == 0) ||
|
(refIdxL0_B == 0 && mvpBx == 0 && mvpBy == 0))
|
(refIdxL0_B == 0 && mvpBx == 0 && mvpBy == 0))
|
begin mvx <= 0; mvy <= 0; end
|
begin mvx <= 0; mvy <= 0; end
|
else
|
else
|
begin mvx <= mvpx; mvy <= mvpy; end
|
begin mvx <= mvpx; mvy <= mvpy; end
|
end
|
end
|
else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s)
|
else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s)
|
begin
|
begin
|
if (mb_type_general == `MB_Inter16x8) //16x8
|
if (mb_type_general == `MB_Inter16x8) //16x8
|
case (mbPartIdx)
|
case (mbPartIdx)
|
2'b00: //upper blk
|
2'b00: //upper blk
|
if (!refIdxL0_B)
|
if (!refIdxL0_B)
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpBx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpBx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpBy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpBy + mvd):0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
end
|
end
|
default: //bottom blk
|
default: //bottom blk
|
if (!refIdxL0_A)
|
if (!refIdxL0_A)
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpAx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpAx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpAy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpAy + mvd):0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
end
|
end
|
endcase
|
endcase
|
else if (mb_type_general == `MB_Inter8x16) //8x16
|
else if (mb_type_general == `MB_Inter8x16) //8x16
|
case (mbPartIdx)
|
case (mbPartIdx)
|
2'b00: //left blk
|
2'b00: //left blk
|
if (!refIdxL0_A)
|
if (!refIdxL0_A)
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpAx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpAx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpAy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpAy + mvd):0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
end
|
end
|
default: //right blk
|
default: //right blk
|
//if mbAddrC is not available but mbAddrB (= mbAddrD) is INTER available (not only available,but also inter
|
//if mbAddrC is not available but mbAddrB (= mbAddrD) is INTER available (not only available,but also inter
|
//available),it still predicted from mbAddrC <- mbAddrD
|
//available),it still predicted from mbAddrC <- mbAddrD
|
if (!refIdxL0_C || (mb_num_h == 10 && !refIdxL0_B))
|
if (!refIdxL0_C || (mb_num_h == 10 && !refIdxL0_B))
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpCx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpCx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpCy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpCy + mvd):0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
end
|
end
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvx <= (compIdx == 0)? (mvpx + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
mvy <= (compIdx == 1)? (mvpy + mvd):0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx <= 0; mvy <= 0;
|
mvx <= 0; mvy <= 0;
|
end
|
end
|
//-----------------------------------------------------
|
//-----------------------------------------------------
|
//Current MB write --> CurrMb0,CurrMb1,CurrMb2,CurrMb3
|
//Current MB write --> CurrMb0,CurrMb1,CurrMb2,CurrMb3
|
//-----------------------------------------------------
|
//-----------------------------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
mv_is16x16 <= 0;
|
mv_is16x16 <= 0;
|
else if (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_P_skip)
|
else if (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_P_skip)
|
mv_is16x16 <= 1;
|
mv_is16x16 <= 1;
|
else
|
else
|
mv_is16x16 <= 0;
|
mv_is16x16 <= 0;
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
begin
|
begin
|
mvx_CurrMb0 <= 0; mvx_CurrMb1 <= 0; mvx_CurrMb2 <= 0; mvx_CurrMb3 <= 0;
|
mvx_CurrMb0 <= 0; mvx_CurrMb1 <= 0; mvx_CurrMb2 <= 0; mvx_CurrMb3 <= 0;
|
end
|
end
|
//Inter16x16 or P_skip
|
//Inter16x16 or P_skip
|
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
|
mvx_CurrMb0[7:0] <= mvx;
|
mvx_CurrMb0[7:0] <= mvx;
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; end
|
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; end
|
1:begin mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end
|
1:begin mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end
|
endcase
|
endcase
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; end
|
0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; end
|
1:begin mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end
|
1:begin mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end
|
endcase
|
endcase
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvx_CurrMb0 <= {mvx,mvx,mvx,mvx};
|
0:mvx_CurrMb0 <= {mvx,mvx,mvx,mvx};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[15:8] <= mvx; end
|
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[15:8] <= mvx; end
|
1:begin mvx_CurrMb0[23:16] <= mvx; mvx_CurrMb0[31:24] <= mvx; end
|
1:begin mvx_CurrMb0[23:16] <= mvx; mvx_CurrMb0[31:24] <= mvx; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[23:16] <= mvx; end
|
0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[23:16] <= mvx; end
|
1:begin mvx_CurrMb0[15:8] <= mvx; mvx_CurrMb0[31:24] <= mvx; end
|
1:begin mvx_CurrMb0[15:8] <= mvx; mvx_CurrMb0[31:24] <= mvx; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvx_CurrMb0[7:0] <= mvx;
|
0:mvx_CurrMb0[7:0] <= mvx;
|
1:mvx_CurrMb0[15:8] <= mvx;
|
1:mvx_CurrMb0[15:8] <= mvx;
|
2:mvx_CurrMb0[23:16] <= mvx;
|
2:mvx_CurrMb0[23:16] <= mvx;
|
3:mvx_CurrMb0[31:24] <= mvx;
|
3:mvx_CurrMb0[31:24] <= mvx;
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvx_CurrMb1 <= {mvx,mvx,mvx,mvx};
|
0:mvx_CurrMb1 <= {mvx,mvx,mvx,mvx};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[15:8] <= mvx; end
|
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[15:8] <= mvx; end
|
1:begin mvx_CurrMb1[23:16] <= mvx; mvx_CurrMb1[31:24] <= mvx; end
|
1:begin mvx_CurrMb1[23:16] <= mvx; mvx_CurrMb1[31:24] <= mvx; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[23:16] <= mvx; end
|
0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[23:16] <= mvx; end
|
1:begin mvx_CurrMb1[15:8] <= mvx; mvx_CurrMb1[31:24] <= mvx; end
|
1:begin mvx_CurrMb1[15:8] <= mvx; mvx_CurrMb1[31:24] <= mvx; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvx_CurrMb1[7:0] <= mvx;
|
0:mvx_CurrMb1[7:0] <= mvx;
|
1:mvx_CurrMb1[15:8] <= mvx;
|
1:mvx_CurrMb1[15:8] <= mvx;
|
2:mvx_CurrMb1[23:16] <= mvx;
|
2:mvx_CurrMb1[23:16] <= mvx;
|
3:mvx_CurrMb1[31:24] <= mvx;
|
3:mvx_CurrMb1[31:24] <= mvx;
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvx_CurrMb2 <= {mvx,mvx,mvx,mvx};
|
0:mvx_CurrMb2 <= {mvx,mvx,mvx,mvx};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[15:8] <= mvx; end
|
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[15:8] <= mvx; end
|
1:begin mvx_CurrMb2[23:16] <= mvx; mvx_CurrMb2[31:24] <= mvx; end
|
1:begin mvx_CurrMb2[23:16] <= mvx; mvx_CurrMb2[31:24] <= mvx; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[23:16] <= mvx; end
|
0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[23:16] <= mvx; end
|
1:begin mvx_CurrMb2[15:8] <= mvx; mvx_CurrMb2[31:24] <= mvx; end
|
1:begin mvx_CurrMb2[15:8] <= mvx; mvx_CurrMb2[31:24] <= mvx; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvx_CurrMb2[7:0] <= mvx;
|
0:mvx_CurrMb2[7:0] <= mvx;
|
1:mvx_CurrMb2[15:8] <= mvx;
|
1:mvx_CurrMb2[15:8] <= mvx;
|
2:mvx_CurrMb2[23:16] <= mvx;
|
2:mvx_CurrMb2[23:16] <= mvx;
|
3:mvx_CurrMb2[31:24] <= mvx;
|
3:mvx_CurrMb2[31:24] <= mvx;
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvx_CurrMb3 <= {mvx,mvx,mvx,mvx};
|
0:mvx_CurrMb3 <= {mvx,mvx,mvx,mvx};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[15:8] <= mvx; end
|
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[15:8] <= mvx; end
|
1:begin mvx_CurrMb3[23:16] <= mvx; mvx_CurrMb3[31:24] <= mvx; end
|
1:begin mvx_CurrMb3[23:16] <= mvx; mvx_CurrMb3[31:24] <= mvx; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[23:16] <= mvx; end
|
0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[23:16] <= mvx; end
|
1:begin mvx_CurrMb3[15:8] <= mvx; mvx_CurrMb3[31:24] <= mvx; end
|
1:begin mvx_CurrMb3[15:8] <= mvx; mvx_CurrMb3[31:24] <= mvx; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvx_CurrMb3[7:0] <= mvx;
|
0:mvx_CurrMb3[7:0] <= mvx;
|
1:mvx_CurrMb3[15:8] <= mvx;
|
1:mvx_CurrMb3[15:8] <= mvx;
|
2:mvx_CurrMb3[23:16] <= mvx;
|
2:mvx_CurrMb3[23:16] <= mvx;
|
3:mvx_CurrMb3[31:24] <= mvx;
|
3:mvx_CurrMb3[31:24] <= mvx;
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
begin
|
begin
|
mvy_CurrMb0 <= 0; mvy_CurrMb1 <= 0; mvy_CurrMb2 <= 0; mvy_CurrMb3 <= 0;
|
mvy_CurrMb0 <= 0; mvy_CurrMb1 <= 0; mvy_CurrMb2 <= 0; mvy_CurrMb3 <= 0;
|
end
|
end
|
//Inter16x16 or P_skip
|
//Inter16x16 or P_skip
|
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1))
|
begin
|
begin
|
mvy_CurrMb0[7:0] <= mvy;
|
mvy_CurrMb0[7:0] <= mvy;
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; end
|
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; end
|
1:begin mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end
|
1:begin mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end
|
endcase
|
endcase
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; end
|
0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; end
|
1:begin mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end
|
1:begin mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end
|
endcase
|
endcase
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:
|
0:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvy_CurrMb0 <= {mvy,mvy,mvy,mvy};
|
0:mvy_CurrMb0 <= {mvy,mvy,mvy,mvy};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[15:8] <= mvy; end
|
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[15:8] <= mvy; end
|
1:begin mvy_CurrMb0[23:16] <= mvy; mvy_CurrMb0[31:24] <= mvy; end
|
1:begin mvy_CurrMb0[23:16] <= mvy; mvy_CurrMb0[31:24] <= mvy; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[23:16] <= mvy; end
|
0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[23:16] <= mvy; end
|
1:begin mvy_CurrMb0[15:8] <= mvy; mvy_CurrMb0[31:24] <= mvy; end
|
1:begin mvy_CurrMb0[15:8] <= mvy; mvy_CurrMb0[31:24] <= mvy; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvy_CurrMb0[7:0] <= mvy;
|
0:mvy_CurrMb0[7:0] <= mvy;
|
1:mvy_CurrMb0[15:8] <= mvy;
|
1:mvy_CurrMb0[15:8] <= mvy;
|
2:mvy_CurrMb0[23:16] <= mvy;
|
2:mvy_CurrMb0[23:16] <= mvy;
|
3:mvy_CurrMb0[31:24] <= mvy;
|
3:mvy_CurrMb0[31:24] <= mvy;
|
endcase
|
endcase
|
endcase
|
endcase
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvy_CurrMb1 <= {mvy,mvy,mvy,mvy};
|
0:mvy_CurrMb1 <= {mvy,mvy,mvy,mvy};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[15:8] <= mvy; end
|
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[15:8] <= mvy; end
|
1:begin mvy_CurrMb1[23:16] <= mvy; mvy_CurrMb1[31:24] <= mvy; end
|
1:begin mvy_CurrMb1[23:16] <= mvy; mvy_CurrMb1[31:24] <= mvy; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[23:16] <= mvy; end
|
0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[23:16] <= mvy; end
|
1:begin mvy_CurrMb1[15:8] <= mvy; mvy_CurrMb1[31:24] <= mvy; end
|
1:begin mvy_CurrMb1[15:8] <= mvy; mvy_CurrMb1[31:24] <= mvy; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvy_CurrMb1[7:0] <= mvy;
|
0:mvy_CurrMb1[7:0] <= mvy;
|
1:mvy_CurrMb1[15:8] <= mvy;
|
1:mvy_CurrMb1[15:8] <= mvy;
|
2:mvy_CurrMb1[23:16] <= mvy;
|
2:mvy_CurrMb1[23:16] <= mvy;
|
3:mvy_CurrMb1[31:24] <= mvy;
|
3:mvy_CurrMb1[31:24] <= mvy;
|
endcase
|
endcase
|
endcase
|
endcase
|
2:
|
2:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvy_CurrMb2 <= {mvy,mvy,mvy,mvy};
|
0:mvy_CurrMb2 <= {mvy,mvy,mvy,mvy};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[15:8] <= mvy; end
|
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[15:8] <= mvy; end
|
1:begin mvy_CurrMb2[23:16] <= mvy; mvy_CurrMb2[31:24] <= mvy; end
|
1:begin mvy_CurrMb2[23:16] <= mvy; mvy_CurrMb2[31:24] <= mvy; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[23:16] <= mvy; end
|
0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[23:16] <= mvy; end
|
1:begin mvy_CurrMb2[15:8] <= mvy; mvy_CurrMb2[31:24] <= mvy; end
|
1:begin mvy_CurrMb2[15:8] <= mvy; mvy_CurrMb2[31:24] <= mvy; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvy_CurrMb2[7:0] <= mvy;
|
0:mvy_CurrMb2[7:0] <= mvy;
|
1:mvy_CurrMb2[15:8] <= mvy;
|
1:mvy_CurrMb2[15:8] <= mvy;
|
2:mvy_CurrMb2[23:16] <= mvy;
|
2:mvy_CurrMb2[23:16] <= mvy;
|
3:mvy_CurrMb2[31:24] <= mvy;
|
3:mvy_CurrMb2[31:24] <= mvy;
|
endcase
|
endcase
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:mvy_CurrMb3 <= {mvy,mvy,mvy,mvy};
|
0:mvy_CurrMb3 <= {mvy,mvy,mvy,mvy};
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[15:8] <= mvy; end
|
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[15:8] <= mvy; end
|
1:begin mvy_CurrMb3[23:16] <= mvy; mvy_CurrMb3[31:24] <= mvy; end
|
1:begin mvy_CurrMb3[23:16] <= mvy; mvy_CurrMb3[31:24] <= mvy; end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[23:16] <= mvy; end
|
0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[23:16] <= mvy; end
|
1:begin mvy_CurrMb3[15:8] <= mvy; mvy_CurrMb3[31:24] <= mvy; end
|
1:begin mvy_CurrMb3[15:8] <= mvy; mvy_CurrMb3[31:24] <= mvy; end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0:mvy_CurrMb3[7:0] <= mvy;
|
0:mvy_CurrMb3[7:0] <= mvy;
|
1:mvy_CurrMb3[15:8] <= mvy;
|
1:mvy_CurrMb3[15:8] <= mvy;
|
2:mvy_CurrMb3[23:16] <= mvy;
|
2:mvy_CurrMb3[23:16] <= mvy;
|
3:mvy_CurrMb3[31:24] <= mvy;
|
3:mvy_CurrMb3[31:24] <= mvy;
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
//----------------------------
|
//----------------------------
|
//mbAddrA write --> mvx_mbAddrA
|
//mbAddrA write --> mvx_mbAddrA
|
//----------------------------
|
//----------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
mvx_mbAddrA <= 0;
|
mvx_mbAddrA <= 0;
|
else if (mb_num_h != 10)//if mb_num_h == 10,mvx_mbAddrA will be no use
|
else if (mb_num_h != 10)//if mb_num_h == 10,mvx_mbAddrA will be no use
|
begin
|
begin
|
//P_skip
|
//P_skip
|
if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
|
if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
|
mvx_mbAddrA <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
|
mvx_mbAddrA <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
|
//Inter16x16
|
//Inter16x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
|
mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end
|
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end
|
1:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end
|
1:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end
|
endcase
|
endcase
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 0)
|
mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
|
mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end
|
0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end
|
1:if (subMbPartIdx == 0) mvx_mbAddrA[7:0] <= mvx;
|
1:if (subMbPartIdx == 0) mvx_mbAddrA[7:0] <= mvx;
|
else mvx_mbAddrA[15:8] <= mvx;
|
else mvx_mbAddrA[15:8] <= mvx;
|
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx;end
|
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx;end
|
3:if (subMbPartIdx == 1) mvx_mbAddrA[7:0] <= mvx;
|
3:if (subMbPartIdx == 1) mvx_mbAddrA[7:0] <= mvx;
|
else if (subMbPartIdx == 3) mvx_mbAddrA[15:8] <= mvx;
|
else if (subMbPartIdx == 3) mvx_mbAddrA[15:8] <= mvx;
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end
|
0:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end
|
1:if (subMbPartIdx == 0) mvx_mbAddrA[23:16] <= mvx;
|
1:if (subMbPartIdx == 0) mvx_mbAddrA[23:16] <= mvx;
|
else mvx_mbAddrA[31:24] <= mvx;
|
else mvx_mbAddrA[31:24] <= mvx;
|
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx;end
|
2:if (subMbPartIdx == 1) begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx;end
|
3:if (subMbPartIdx == 1) mvx_mbAddrA[23:16] <= mvx;
|
3:if (subMbPartIdx == 1) mvx_mbAddrA[23:16] <= mvx;
|
else if (subMbPartIdx == 3) mvx_mbAddrA[31:24] <= mvx;
|
else if (subMbPartIdx == 3) mvx_mbAddrA[31:24] <= mvx;
|
endcase
|
endcase
|
endcase
|
endcase
|
end
|
end
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
mvy_mbAddrA <= 0;
|
mvy_mbAddrA <= 0;
|
else if (mb_num_h != 10)//if mb_num_h == 10,mvy_mbAddrA will be no use
|
else if (mb_num_h != 10)//if mb_num_h == 10,mvy_mbAddrA will be no use
|
begin
|
begin
|
//P_skip
|
//P_skip
|
if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
|
if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
|
mvy_mbAddrA <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]};
|
mvy_mbAddrA <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]};
|
//Inter16x16
|
//Inter16x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
|
mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end
|
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end
|
1:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end
|
1:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end
|
endcase
|
endcase
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 1)
|
mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
|
mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
1:
|
1:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end
|
0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end
|
1:if (subMbPartIdx == 0) mvy_mbAddrA[7:0] <= mvy;
|
1:if (subMbPartIdx == 0) mvy_mbAddrA[7:0] <= mvy;
|
else mvy_mbAddrA[15:8] <= mvy;
|
else mvy_mbAddrA[15:8] <= mvy;
|
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy;end
|
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy;end
|
3:if (subMbPartIdx == 1) mvy_mbAddrA[7:0] <= mvy;
|
3:if (subMbPartIdx == 1) mvy_mbAddrA[7:0] <= mvy;
|
else if (subMbPartIdx == 3) mvy_mbAddrA[15:8] <= mvy;
|
else if (subMbPartIdx == 3) mvy_mbAddrA[15:8] <= mvy;
|
endcase
|
endcase
|
3:
|
3:
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end
|
0:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end
|
1:if (subMbPartIdx == 0) mvy_mbAddrA[23:16] <= mvy;
|
1:if (subMbPartIdx == 0) mvy_mbAddrA[23:16] <= mvy;
|
else mvy_mbAddrA[31:24] <= mvy;
|
else mvy_mbAddrA[31:24] <= mvy;
|
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy;end
|
2:if (subMbPartIdx == 1) begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy;end
|
3:if (subMbPartIdx == 1) mvy_mbAddrA[23:16] <= mvy;
|
3:if (subMbPartIdx == 1) mvy_mbAddrA[23:16] <= mvy;
|
else if (subMbPartIdx == 3) mvy_mbAddrA[31:24] <= mvy;
|
else if (subMbPartIdx == 3) mvy_mbAddrA[31:24] <= mvy;
|
endcase
|
endcase
|
endcase
|
endcase
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
//mbAddrB RF read and write --> mvx_mbAddrB
|
//mbAddrB RF read and write --> mvx_mbAddrB
|
//-----------------------------------------
|
//-----------------------------------------
|
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF
|
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF
|
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v
|
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v
|
or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] or mvx_CurrMb2 or mvx_CurrMb3
|
or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] or mvx_CurrMb2 or mvx_CurrMb3
|
or refIdxL0_A or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_C)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
//read for DF boundary strength decoding
|
//read for DF boundary strength decoding
|
else if (mv_mbAddrB_rd_for_DF)
|
else if (mv_mbAddrB_rd_for_DF)
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
//P_skip
|
//P_skip
|
else if (slice_data_state == `skip_run_duration)
|
else if (slice_data_state == `skip_run_duration)
|
begin
|
begin
|
if (Is_skipMB_mv_calc) //read
|
if (Is_skipMB_mv_calc) //read
|
begin
|
begin
|
if (mb_num_v == 0)
|
if (mb_num_v == 0)
|
begin mvx_mbAddrB_cs_n <= 1;mvx_mbAddrB_rd_addr <= 0; end
|
begin mvx_mbAddrB_cs_n <= 1;mvx_mbAddrB_rd_addr <= 0; end
|
else
|
else
|
begin mvx_mbAddrB_cs_n <= 0;mvx_mbAddrB_rd_addr <= mb_num_h;end
|
begin mvx_mbAddrB_cs_n <= 0;mvx_mbAddrB_rd_addr <= mb_num_h;end
|
mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
else if (end_of_MB_DEC) //write
|
else if (end_of_MB_DEC) //write
|
begin
|
begin
|
if (mb_num_v == 8)
|
if (mb_num_v == 8)
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_wr_addr <= 0; mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_wr_addr <= 0; mvx_mbAddrB_din <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
|
mvx_mbAddrB_din <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
|
end
|
end
|
mvx_mbAddrB_rd_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
end
|
end
|
//Inter16x16
|
//Inter16x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
begin
|
begin
|
if (mb_num_v == 0) //!read,write
|
if (mb_num_v == 0) //!read,write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
end
|
end
|
else if (mb_num_v == 8) //read,!write
|
else if (mb_num_v == 8) //read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
else //read,write
|
else //read,write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_wr_n <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_wr_n <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
end
|
end
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0: //read,!write
|
0: //read,!write
|
begin
|
begin
|
if (mb_num_v == 0) //!read,!write
|
if (mb_num_v == 0) //!read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
end
|
end
|
1: //!read,write
|
1: //!read,write
|
begin
|
begin
|
if (mb_num_v == 8) //!read,!write
|
if (mb_num_v == 8) //!read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
else //!read,write
|
else //!read,write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx};
|
end
|
end
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0: //read when mbAddrA is not available for inter pred,!write
|
0: //read when mbAddrA is not available for inter pred,!write
|
if (refIdxL0_A == 1'b1)
|
if (refIdxL0_A == 1'b1)
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= mb_num_h;mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= mb_num_h;mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
1: //need read :mb_num_h == 10 && mb_num_v != 0
|
1: //need read :mb_num_h == 10 && mb_num_v != 0
|
//need write:mb_num_v != 8
|
//need write:mb_num_v != 8
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1;
|
mvx_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1;
|
mvx_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0;
|
mvx_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0;
|
mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_rd_addr <= mb_num_h;
|
mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
//8x8
|
//8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0,1: //read,!write
|
0,1: //read,!write
|
if (mb_num_v == 0) //!read,!write
|
if (mb_num_v == 0) //!read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
2: //!read,!write
|
2: //!read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
3: //!read,write
|
3: //!read,write
|
if (mb_num_v == 8) //!read,!write
|
if (mb_num_v == 8) //!read,!write
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
else
|
else
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0: //8x8
|
0: //8x8
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
end
|
end
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1:
|
1:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1:
|
1:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx_CurrMb3[23:16],mvx};
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx_CurrMb3[23:16],mvx};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
3:
|
3:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h;
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],
|
mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],
|
mvx_CurrMb3[23:16],mvx};
|
mvx_CurrMb3[23:16],mvx};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0;
|
mvx_mbAddrB_din <= 0;
|
mvx_mbAddrB_din <= 0;
|
end
|
end
|
|
|
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF
|
always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF
|
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v
|
or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v
|
or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] or mvy_CurrMb2 or mvy_CurrMb3
|
or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] or mvy_CurrMb2 or mvy_CurrMb3
|
or refIdxL0_A or refIdxL0_C)
|
or refIdxL0_A or refIdxL0_C)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
//read for DF boundary strength decoding
|
//read for DF boundary strength decoding
|
else if (mv_mbAddrB_rd_for_DF)
|
else if (mv_mbAddrB_rd_for_DF)
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
//P_skip
|
//P_skip
|
else if (slice_data_state == `skip_run_duration)
|
else if (slice_data_state == `skip_run_duration)
|
begin
|
begin
|
if (Is_skipMB_mv_calc) //read
|
if (Is_skipMB_mv_calc) //read
|
begin
|
begin
|
if (mb_num_v == 0)
|
if (mb_num_v == 0)
|
begin mvy_mbAddrB_cs_n <= 1;mvy_mbAddrB_rd_addr <= 0; end
|
begin mvy_mbAddrB_cs_n <= 1;mvy_mbAddrB_rd_addr <= 0; end
|
else
|
else
|
begin mvy_mbAddrB_cs_n <= 0;mvy_mbAddrB_rd_addr <= mb_num_h;end
|
begin mvy_mbAddrB_cs_n <= 0;mvy_mbAddrB_rd_addr <= mb_num_h;end
|
mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
else if (end_of_MB_DEC) //write
|
else if (end_of_MB_DEC) //write
|
begin
|
begin
|
if (mb_num_v == 8)
|
if (mb_num_v == 8)
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_wr_addr <= 0; mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_wr_addr <= 0; mvy_mbAddrB_din <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]};
|
mvy_mbAddrB_din <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]};
|
end
|
end
|
mvy_mbAddrB_rd_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
end
|
end
|
//Inter16x16
|
//Inter16x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
begin
|
begin
|
if (mb_num_v == 0) //!read,write
|
if (mb_num_v == 0) //!read,write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
end
|
end
|
else if (mb_num_v == 8) //read,!write
|
else if (mb_num_v == 8) //read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
else //read,write
|
else //read,write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_wr_n <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_wr_n <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
end
|
end
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0: //read,!write
|
0: //read,!write
|
begin
|
begin
|
if (mb_num_v == 0) //!read,!write
|
if (mb_num_v == 0) //!read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
end
|
end
|
1: //!read,write
|
1: //!read,write
|
begin
|
begin
|
if (mb_num_v == 8) //!read,!write
|
if (mb_num_v == 8) //!read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
else //!read,write
|
else //!read,write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy};
|
end
|
end
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0: //read when mbAddrA is not available for inter pred,!write
|
0: //read when mbAddrA is not available for inter pred,!write
|
if (refIdxL0_A == 1'b1)
|
if (refIdxL0_A == 1'b1)
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= mb_num_h;mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= mb_num_h;mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
1: //need read :mb_num_h == 10 && mb_num_v != 0
|
1: //need read :mb_num_h == 10 && mb_num_v != 0
|
//need write:mb_num_v != 8
|
//need write:mb_num_v != 8
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1;
|
mvy_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1;
|
mvy_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0;
|
mvy_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0;
|
mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_rd_addr <= mb_num_h;
|
mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
//8x8
|
//8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0,1: //read,!write
|
0,1: //read,!write
|
if (mb_num_v == 0) //!read,!write
|
if (mb_num_v == 0) //!read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
2: //!read,!write
|
2: //!read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
3: //!read,write
|
3: //!read,write
|
if (mb_num_v == 8) //!read,!write
|
if (mb_num_v == 8) //!read,!write
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
else
|
else
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0: //8x8
|
0: //8x8
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
end
|
end
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1:
|
1:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1:
|
1:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy_CurrMb3[23:16],mvy};
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy_CurrMb3[23:16],mvy};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
3:
|
3:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h;
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],
|
mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],
|
mvy_CurrMb3[23:16],mvy};
|
mvy_CurrMb3[23:16],mvy};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0;
|
mvy_mbAddrB_din <= 0;
|
mvy_mbAddrB_din <= 0;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
//mbAddrC RF read and write --> mvx_mbAddrC
|
//mbAddrC RF read and write --> mvx_mbAddrC
|
//-----------------------------------------
|
//-----------------------------------------
|
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state
|
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state
|
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0]
|
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0]
|
or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_B or refIdxL0_C)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
//P_skip
|
//P_skip
|
else if (slice_data_state == `skip_run_duration)
|
else if (slice_data_state == `skip_run_duration)
|
begin
|
begin
|
if (Is_skipMB_mv_calc) //read
|
if (Is_skipMB_mv_calc) //read
|
begin
|
begin
|
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write
|
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write
|
begin mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_rd_addr <= 0; end
|
begin mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_rd_addr <= 0; end
|
else
|
else
|
begin mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_rd_addr <= mb_num_h; end
|
begin mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_rd_addr <= mb_num_h; end
|
mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else if (end_of_MB_DEC) //write
|
else if (end_of_MB_DEC) //write
|
begin
|
begin
|
if (mb_num_v == 8 || mb_num_h == 0) //!write
|
if (mb_num_v == 8 || mb_num_h == 0) //!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else //write
|
else //write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx_CurrMb0[7:0];
|
mvx_mbAddrC_din <= mvx_CurrMb0[7:0];
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
//Inter16x16
|
//Inter16x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
|
begin
|
begin
|
if (mb_num == 0)//!read,!write
|
if (mb_num == 0)//!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else if (mb_num_v == 0)//!read,write
|
else if (mb_num_v == 0)//!read,write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write
|
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else //read,write
|
else //read,write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
|
begin
|
begin
|
if (mbPartIdx == 0) //upper blk,may read,no write
|
if (mbPartIdx == 0) //upper blk,may read,no write
|
begin
|
begin
|
if (refIdxL0_B && !refIdxL0_C) //read,!write
|
if (refIdxL0_B && !refIdxL0_C) //read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else //!read,!write
|
else //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
else //bottom blk,may write,no read
|
else //bottom blk,may write,no read
|
begin
|
begin
|
if (mb_num_h != 0) //!read,write
|
if (mb_num_h != 0) //!read,write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
else //!read,!write
|
else //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0: //!read,write
|
0: //!read,write
|
if (mb_num_v == 8)
|
if (mb_num_v == 8)
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
default: //read,!write
|
default: //read,!write
|
begin
|
begin
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
1: //read,!write
|
1: //read,!write
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0: //8x8
|
0: //8x8
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0: //read,!write
|
0: //read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1: //read,!write
|
1: //read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1: //read,!write
|
1: //read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
2: //!read,write
|
2: //!read,write
|
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write
|
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
else //!read,write
|
else //!read,write
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0: //8x8
|
0: //8x8
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1: //!read,write
|
1: //!read,write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0: //!read,write
|
0: //!read,write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
2: //!read,write
|
2: //!read,write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvx_mbAddrC_din <= mvx;
|
mvx_mbAddrC_din <= mvx;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
default:
|
default:
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0;
|
mvx_mbAddrC_din <= 0;
|
mvx_mbAddrC_din <= 0;
|
end
|
end
|
|
|
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state
|
always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state
|
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0]
|
or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0]
|
or refIdxL0_B or refIdxL0_C)
|
or refIdxL0_B or refIdxL0_C)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
//P_skip
|
//P_skip
|
else if (slice_data_state == `skip_run_duration)
|
else if (slice_data_state == `skip_run_duration)
|
begin
|
begin
|
if (Is_skipMB_mv_calc) //read
|
if (Is_skipMB_mv_calc) //read
|
begin
|
begin
|
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write
|
if (mb_num_v == 0 || mb_num_h == 10)//!read,!write
|
begin mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_rd_addr <= 0; end
|
begin mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_rd_addr <= 0; end
|
else
|
else
|
begin mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_rd_addr <= mb_num_h; end
|
begin mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_rd_addr <= mb_num_h; end
|
mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else if (end_of_MB_DEC) //write
|
else if (end_of_MB_DEC) //write
|
begin
|
begin
|
if (mb_num_v == 8 || mb_num_h == 0) //!write
|
if (mb_num_v == 8 || mb_num_h == 0) //!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else //write
|
else //write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy_CurrMb0[7:0];
|
mvy_mbAddrC_din <= mvy_CurrMb0[7:0];
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
//Inter16x16
|
//Inter16x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
|
begin
|
begin
|
if (mb_num == 0)//!read,!write
|
if (mb_num == 0)//!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else if (mb_num_v == 0)//!read,write
|
else if (mb_num_v == 0)//!read,write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write
|
else if (mb_num_h == 0 || mb_num_v == 8) //read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else //read,write
|
else //read,write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
end
|
end
|
//Inter16x8
|
//Inter16x8
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
|
begin
|
begin
|
if (mbPartIdx == 0) //upper blk,may read,no write
|
if (mbPartIdx == 0) //upper blk,may read,no write
|
begin
|
begin
|
if (refIdxL0_B && !refIdxL0_C) //read,!write
|
if (refIdxL0_B && !refIdxL0_C) //read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else //!read,!write
|
else //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
else //bottom blk,may write,no read
|
else //bottom blk,may write,no read
|
begin
|
begin
|
if (mb_num_h != 0) //!read,write
|
if (mb_num_h != 0) //!read,write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
else //!read,!write
|
else //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
//Inter8x16
|
//Inter8x16
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0: //!read,write
|
0: //!read,write
|
if (mb_num_v == 8)
|
if (mb_num_v == 8)
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
default: //read,!write
|
default: //read,!write
|
begin
|
begin
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
//Inter8x8
|
//Inter8x8
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
1: //read,!write
|
1: //read,!write
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
if (mb_num_v == 0 || mb_num_h == 10) //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else //read,!write
|
else //read,!write
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0: //8x8
|
0: //8x8
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0: //read,!write
|
0: //read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1: //read,!write
|
1: //read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1: //read,!write
|
1: //read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
2: //!read,write
|
2: //!read,write
|
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write
|
if (mb_num_h == 0 || mb_num_v == 8) //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
else //!read,write
|
else //!read,write
|
case (sub_mb_type)
|
case (sub_mb_type)
|
0: //8x8
|
0: //8x8
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
1: //8x4
|
1: //8x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
1: //!read,write
|
1: //!read,write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
2: //4x8
|
2: //4x8
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
0: //!read,write
|
0: //!read,write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
3: //4x4
|
3: //4x4
|
case (subMbPartIdx)
|
case (subMbPartIdx)
|
2: //!read,write
|
2: //!read,write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1;
|
mvy_mbAddrC_din <= mvy;
|
mvy_mbAddrC_din <= mvy;
|
end
|
end
|
default: //!read,!write
|
default: //!read,!write
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
default:
|
default:
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0;
|
mvy_mbAddrC_din <= 0;
|
mvy_mbAddrC_din <= 0;
|
end
|
end
|
|
|
//-------------------------------
|
//-------------------------------
|
//mbAddrD write --> mvx_mbAddrD
|
//mbAddrD write --> mvx_mbAddrD
|
//-------------------------------
|
//-------------------------------
|
//mvx_mbAddrD
|
//mvx_mbAddrD
|
reg [7:0] mvx_mbAddrD_subMB;
|
reg [7:0] mvx_mbAddrD_subMB;
|
reg [7:0] mvx_mbAddrD_MB,mvx_mbAddrD_MB_tmp;
|
reg [7:0] mvx_mbAddrD_MB,mvx_mbAddrD_MB_tmp;
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
mvx_mbAddrD_subMB <= 0;
|
mvx_mbAddrD_subMB <= 0;
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
mvx_mbAddrD_subMB <= mvx_mbAddrA[7:0];
|
mvx_mbAddrD_subMB <= mvx_mbAddrA[7:0];
|
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
mvx_mbAddrD_subMB <= mvx_mbAddrA[23:16];
|
mvx_mbAddrD_subMB <= mvx_mbAddrA[23:16];
|
endcase
|
endcase
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
mvx_mbAddrD_MB_tmp <= 0;
|
mvx_mbAddrD_MB_tmp <= 0;
|
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0)
|
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0)
|
mvx_mbAddrD_MB_tmp <= (mv_is16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb3[31:24];
|
mvx_mbAddrD_MB_tmp <= (mv_is16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb3[31:24];
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
mvx_mbAddrD_MB <= 0;
|
mvx_mbAddrD_MB <= 0;
|
else if (end_of_MB_DEC && mb_num_h == 10)
|
else if (end_of_MB_DEC && mb_num_h == 10)
|
mvx_mbAddrD_MB <= mvx_mbAddrD_MB_tmp;
|
mvx_mbAddrD_MB <= mvx_mbAddrD_MB_tmp;
|
|
|
assign mvx_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvx_mbAddrD_subMB:mvx_mbAddrD_MB;
|
assign mvx_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvx_mbAddrD_subMB:mvx_mbAddrD_MB;
|
|
|
//mvy_mbAddrD
|
//mvy_mbAddrD
|
reg [7:0] mvy_mbAddrD_subMB;
|
reg [7:0] mvy_mbAddrD_subMB;
|
reg [7:0] mvy_mbAddrD_MB,mvy_mbAddrD_MB_tmp;
|
reg [7:0] mvy_mbAddrD_MB,mvy_mbAddrD_MB_tmp;
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
mvy_mbAddrD_subMB <= 0;
|
mvy_mbAddrD_subMB <= 0;
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
|
case (mbPartIdx)
|
case (mbPartIdx)
|
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
mvy_mbAddrD_subMB <= mvy_mbAddrA[7:0];
|
mvy_mbAddrD_subMB <= mvy_mbAddrA[7:0];
|
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk
|
mvy_mbAddrD_subMB <= mvy_mbAddrA[23:16];
|
mvy_mbAddrD_subMB <= mvy_mbAddrA[23:16];
|
endcase
|
endcase
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
mvy_mbAddrD_MB_tmp <= 0;
|
mvy_mbAddrD_MB_tmp <= 0;
|
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0)
|
else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0)
|
mvy_mbAddrD_MB_tmp <= (mv_is16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb3[31:24];
|
mvy_mbAddrD_MB_tmp <= (mv_is16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb3[31:24];
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
mvy_mbAddrD_MB <= 0;
|
mvy_mbAddrD_MB <= 0;
|
else if (end_of_MB_DEC && mb_num_h == 10)
|
else if (end_of_MB_DEC && mb_num_h == 10)
|
mvy_mbAddrD_MB <= mvy_mbAddrD_MB_tmp;
|
mvy_mbAddrD_MB <= mvy_mbAddrD_MB_tmp;
|
|
|
assign mvy_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvy_mbAddrD_subMB:mvy_mbAddrD_MB;
|
assign mvy_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvy_mbAddrD_subMB:mvy_mbAddrD_MB;
|
|
|
|
|
