//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : Intra_pred_top.v
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// File : Intra_pred_top.v
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// Generated : Sep 30,2005
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// Generated : Sep 30,2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Top module of Intra prediction
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// Top module of Intra prediction
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module Intra_pred_top (clk,reset_n,
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module Intra_pred_top (clk,reset_n,
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gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,
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gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,
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gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,gclk_Intra_mbAddrB_RAM,
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gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,gclk_Intra_mbAddrB_RAM,
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mb_num_h,mb_num_v,mb_type_general,NextMB_IsSkip,
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mb_num_h,mb_num_v,mb_type_general,NextMB_IsSkip,
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Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
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Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
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blk4x4_rec_counter,trigger_blk4x4_intra_pred,blk4x4_sum_counter,
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blk4x4_rec_counter,trigger_blk4x4_intra_pred,blk4x4_sum_counter,
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sum_right_column_reg,blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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sum_right_column_reg,blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
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blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
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blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
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blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
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blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
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blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
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blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
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blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
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Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din,
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Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din,
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PE0_out,PE1_out,PE2_out,PE3_out,Intra4x4_predmode,
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PE0_out,PE1_out,PE2_out,PE3_out,Intra4x4_predmode,
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blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
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blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
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end_of_one_blk4x4_intra,Intra_mbAddrB_RAM_rd
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end_of_one_blk4x4_intra,Intra_mbAddrB_RAM_rd
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);
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);
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input clk,reset_n;
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input clk,reset_n;
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input gclk_intra_mbAddrA_luma;
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input gclk_intra_mbAddrA_luma;
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input gclk_intra_mbAddrA_Cb;
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input gclk_intra_mbAddrA_Cb;
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input gclk_intra_mbAddrA_Cr;
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input gclk_intra_mbAddrA_Cr;
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input gclk_intra_mbAddrB;
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input gclk_intra_mbAddrB;
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input gclk_intra_mbAddrC_luma;
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input gclk_intra_mbAddrC_luma;
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input gclk_intra_mbAddrD;
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input gclk_intra_mbAddrD;
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input gclk_seed;
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input gclk_seed;
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input gclk_Intra_mbAddrB_RAM;
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input gclk_Intra_mbAddrB_RAM;
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input [3:0] mb_num_h;
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input [3:0] mb_num_h;
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input [3:0] mb_num_v;
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input [3:0] mb_num_v;
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input [3:0] mb_type_general;
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input [3:0] mb_type_general;
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input NextMB_IsSkip;
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input NextMB_IsSkip;
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input [1:0] Intra16x16_predmode;
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input [1:0] Intra16x16_predmode;
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input [63:0] Intra4x4_predmode_CurrMb;
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input [63:0] Intra4x4_predmode_CurrMb;
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input [1:0] Intra_chroma_predmode;
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input [1:0] Intra_chroma_predmode;
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input [4:0] blk4x4_rec_counter;
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input [4:0] blk4x4_rec_counter;
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input trigger_blk4x4_intra_pred;
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input trigger_blk4x4_intra_pred;
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input [2:0] blk4x4_sum_counter;
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input [2:0] blk4x4_sum_counter;
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input [23:0] sum_right_column_reg;
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input [23:0] sum_right_column_reg;
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input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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input [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
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input [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
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input [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
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input [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
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input [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
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input [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
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input [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
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input [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
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input Intra_mbAddrB_RAM_wr;
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input Intra_mbAddrB_RAM_wr;
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input [6:0] Intra_mbAddrB_RAM_wr_addr;
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input [6:0] Intra_mbAddrB_RAM_wr_addr;
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input [31:0] Intra_mbAddrB_RAM_din;
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input [31:0] Intra_mbAddrB_RAM_din;
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output [7:0] PE0_out;
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output [7:0] PE0_out;
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output [7:0] PE1_out;
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output [7:0] PE1_out;
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output [7:0] PE2_out;
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output [7:0] PE2_out;
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output [7:0] PE3_out;
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output [7:0] PE3_out;
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output [3:0] Intra4x4_predmode;
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output [3:0] Intra4x4_predmode;
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output [2:0] blk4x4_intra_preload_counter;
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output [2:0] blk4x4_intra_preload_counter;
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output [3:0] blk4x4_intra_precompute_counter;
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output [3:0] blk4x4_intra_precompute_counter;
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output [2:0] blk4x4_intra_calculate_counter;
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output [2:0] blk4x4_intra_calculate_counter;
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output end_of_one_blk4x4_intra;
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output end_of_one_blk4x4_intra;
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output Intra_mbAddrB_RAM_rd;
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output Intra_mbAddrB_RAM_rd;
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wire blkAddrA_availability,blkAddrB_availability;
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wire blkAddrA_availability,blkAddrB_availability;
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wire mbAddrA_availability,mbAddrB_availability,mbAddrC_availability;
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wire mbAddrA_availability,mbAddrB_availability,mbAddrC_availability;
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wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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wire [15:0] PE0_sum_out,PE3_sum_out;
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wire [15:0] PE0_sum_out,PE3_sum_out;
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wire Intra_mbAddrB_RAM_rd;
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wire Intra_mbAddrB_RAM_rd;
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wire [6:0] Intra_mbAddrB_RAM_rd_addr;
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wire [6:0] Intra_mbAddrB_RAM_rd_addr;
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wire [31:0] Intra_mbAddrB_RAM_dout;
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wire [31:0] Intra_mbAddrB_RAM_dout;
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wire [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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wire [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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wire [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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wire [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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wire [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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wire [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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wire [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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wire [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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wire [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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wire [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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wire [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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wire [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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wire [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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wire [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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wire [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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wire [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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wire [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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wire [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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wire [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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wire [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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wire [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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wire [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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wire [7:0] Intra_mbAddrD_window;
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wire [7:0] Intra_mbAddrD_window;
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wire [15:0] main_seed,seed;
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wire [15:0] main_seed,seed;
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wire [11:0] plane_b_reg,plane_c_reg;
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wire [11:0] plane_b_reg,plane_c_reg;
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Intra_pred_pipeline Intra_pred_pipeline (
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Intra_pred_pipeline Intra_pred_pipeline (
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.mb_type_general(mb_type_general),
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.mb_type_general(mb_type_general),
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.blk4x4_rec_counter(blk4x4_rec_counter),
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.blk4x4_rec_counter(blk4x4_rec_counter),
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.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
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.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
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.mb_num_v(mb_num_v),
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.mb_num_v(mb_num_v),
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.mb_num_h(mb_num_h),
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.mb_num_h(mb_num_h),
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.blk4x4_sum_counter(blk4x4_sum_counter),
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.blk4x4_sum_counter(blk4x4_sum_counter),
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.NextMB_IsSkip(NextMB_IsSkip),
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.NextMB_IsSkip(NextMB_IsSkip),
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.Intra16x16_predmode(Intra16x16_predmode),
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.Intra16x16_predmode(Intra16x16_predmode),
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.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
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.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
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.Intra_chroma_predmode(Intra_chroma_predmode),
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.Intra_chroma_predmode(Intra_chroma_predmode),
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.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0),
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.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0),
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.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1),
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.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1),
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.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2),
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.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2),
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.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
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.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
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.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4),
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.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4),
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.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5),
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.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5),
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.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6),
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.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6),
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.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
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.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
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.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8),
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.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8),
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.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9),
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.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9),
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.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
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.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
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.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
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.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
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.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
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.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
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.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
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.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
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.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
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.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
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.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
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.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
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.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0),
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.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0),
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.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1),
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.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1),
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.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2),
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.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2),
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.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
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.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
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.Intra_mbAddrB_reg4(Intra_mbAddrB_reg4),
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.Intra_mbAddrB_reg4(Intra_mbAddrB_reg4),
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.Intra_mbAddrB_reg5(Intra_mbAddrB_reg5),
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.Intra_mbAddrB_reg5(Intra_mbAddrB_reg5),
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.Intra_mbAddrB_reg6(Intra_mbAddrB_reg6),
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.Intra_mbAddrB_reg6(Intra_mbAddrB_reg6),
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.Intra_mbAddrB_reg7(Intra_mbAddrB_reg7),
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.Intra_mbAddrB_reg7(Intra_mbAddrB_reg7),
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.Intra_mbAddrB_reg8(Intra_mbAddrB_reg8),
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.Intra_mbAddrB_reg8(Intra_mbAddrB_reg8),
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.Intra_mbAddrB_reg9(Intra_mbAddrB_reg9),
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.Intra_mbAddrB_reg9(Intra_mbAddrB_reg9),
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.Intra_mbAddrB_reg10(Intra_mbAddrB_reg10),
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.Intra_mbAddrB_reg10(Intra_mbAddrB_reg10),
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.Intra_mbAddrB_reg11(Intra_mbAddrB_reg11),
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.Intra_mbAddrB_reg11(Intra_mbAddrB_reg11),
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.Intra_mbAddrB_reg12(Intra_mbAddrB_reg12),
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.Intra_mbAddrB_reg12(Intra_mbAddrB_reg12),
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.Intra_mbAddrB_reg13(Intra_mbAddrB_reg13),
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.Intra_mbAddrB_reg13(Intra_mbAddrB_reg13),
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.Intra_mbAddrB_reg14(Intra_mbAddrB_reg14),
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.Intra_mbAddrB_reg14(Intra_mbAddrB_reg14),
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.Intra_mbAddrB_reg15(Intra_mbAddrB_reg15),
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.Intra_mbAddrB_reg15(Intra_mbAddrB_reg15),
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.Intra_mbAddrD_window(Intra_mbAddrD_window),
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.Intra_mbAddrD_window(Intra_mbAddrD_window),
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|
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.Intra4x4_predmode(Intra4x4_predmode),
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.Intra4x4_predmode(Intra4x4_predmode),
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.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
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.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
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.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
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.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
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.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
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.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
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.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
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.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
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.blkAddrA_availability(blkAddrA_availability),
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.blkAddrA_availability(blkAddrA_availability),
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.blkAddrB_availability(blkAddrB_availability),
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.blkAddrB_availability(blkAddrB_availability),
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.mbAddrA_availability(mbAddrA_availability),
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.mbAddrA_availability(mbAddrA_availability),
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.mbAddrB_availability(mbAddrB_availability),
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.mbAddrB_availability(mbAddrB_availability),
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.mbAddrC_availability(mbAddrC_availability),
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.mbAddrC_availability(mbAddrC_availability),
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.main_seed(main_seed),
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.main_seed(main_seed),
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.plane_b_reg(plane_b_reg),
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.plane_b_reg(plane_b_reg),
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.plane_c_reg(plane_c_reg),
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.plane_c_reg(plane_c_reg),
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.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd),
|
.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd),
|
.Intra_mbAddrB_RAM_rd_addr(Intra_mbAddrB_RAM_rd_addr)
|
.Intra_mbAddrB_RAM_rd_addr(Intra_mbAddrB_RAM_rd_addr)
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);
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);
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|
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Intra_pred_reg_ctrl Intra_pred_reg_ctrl (
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Intra_pred_reg_ctrl Intra_pred_reg_ctrl (
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.reset_n(reset_n),
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.reset_n(reset_n),
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.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
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.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
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.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
|
.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
|
.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
|
.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
|
.gclk_intra_mbAddrB(gclk_intra_mbAddrB),
|
.gclk_intra_mbAddrB(gclk_intra_mbAddrB),
|
.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),
|
.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),
|
.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
|
.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
|
.gclk_seed(gclk_seed),
|
.gclk_seed(gclk_seed),
|
.mbAddrA_availability(mbAddrA_availability),
|
.mbAddrA_availability(mbAddrA_availability),
|
.mbAddrC_availability(mbAddrC_availability),
|
.mbAddrC_availability(mbAddrC_availability),
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
.blk4x4_sum_counter(blk4x4_sum_counter),
|
.blk4x4_sum_counter(blk4x4_sum_counter),
|
.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
|
.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
|
.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
|
.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
|
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
.mb_type_general(mb_type_general),
|
.mb_type_general(mb_type_general),
|
.Intra4x4_predmode(Intra4x4_predmode),
|
.Intra4x4_predmode(Intra4x4_predmode),
|
.Intra16x16_predmode(Intra16x16_predmode),
|
.Intra16x16_predmode(Intra16x16_predmode),
|
.Intra_chroma_predmode(Intra_chroma_predmode),
|
.Intra_chroma_predmode(Intra_chroma_predmode),
|
.Intra_mbAddrB_RAM_dout(Intra_mbAddrB_RAM_dout),
|
.Intra_mbAddrB_RAM_dout(Intra_mbAddrB_RAM_dout),
|
.sum_right_column_reg(sum_right_column_reg),
|
.sum_right_column_reg(sum_right_column_reg),
|
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
.main_seed(main_seed),
|
.main_seed(main_seed),
|
.PE0_sum_out(PE0_sum_out),
|
.PE0_sum_out(PE0_sum_out),
|
.PE3_sum_out(PE3_sum_out),
|
.PE3_sum_out(PE3_sum_out),
|
|
|
.Intra_mbAddrA_window0(Intra_mbAddrA_window0),
|
.Intra_mbAddrA_window0(Intra_mbAddrA_window0),
|
.Intra_mbAddrA_window1(Intra_mbAddrA_window1),
|
.Intra_mbAddrA_window1(Intra_mbAddrA_window1),
|
.Intra_mbAddrA_window2(Intra_mbAddrA_window2),
|
.Intra_mbAddrA_window2(Intra_mbAddrA_window2),
|
.Intra_mbAddrA_window3(Intra_mbAddrA_window3),
|
.Intra_mbAddrA_window3(Intra_mbAddrA_window3),
|
.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0),
|
.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0),
|
.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1),
|
.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1),
|
.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2),
|
.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2),
|
.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
|
.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
|
.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4),
|
.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4),
|
.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5),
|
.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5),
|
.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6),
|
.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6),
|
.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
|
.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
|
.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8),
|
.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8),
|
.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9),
|
.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9),
|
.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
|
.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
|
.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
|
.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
|
.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
|
.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
|
.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
|
.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
|
.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
|
.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
|
.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
|
.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
|
.Intra_mbAddrB_window0(Intra_mbAddrB_window0),
|
.Intra_mbAddrB_window0(Intra_mbAddrB_window0),
|
.Intra_mbAddrB_window1(Intra_mbAddrB_window1),
|
.Intra_mbAddrB_window1(Intra_mbAddrB_window1),
|
.Intra_mbAddrB_window2(Intra_mbAddrB_window2),
|
.Intra_mbAddrB_window2(Intra_mbAddrB_window2),
|
.Intra_mbAddrB_window3(Intra_mbAddrB_window3),
|
.Intra_mbAddrB_window3(Intra_mbAddrB_window3),
|
.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0),
|
.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0),
|
.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1),
|
.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1),
|
.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2),
|
.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2),
|
.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
|
.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
|
.Intra_mbAddrB_reg4(Intra_mbAddrB_reg4),
|
.Intra_mbAddrB_reg4(Intra_mbAddrB_reg4),
|
.Intra_mbAddrB_reg5(Intra_mbAddrB_reg5),
|
.Intra_mbAddrB_reg5(Intra_mbAddrB_reg5),
|
.Intra_mbAddrB_reg6(Intra_mbAddrB_reg6),
|
.Intra_mbAddrB_reg6(Intra_mbAddrB_reg6),
|
.Intra_mbAddrB_reg7(Intra_mbAddrB_reg7),
|
.Intra_mbAddrB_reg7(Intra_mbAddrB_reg7),
|
.Intra_mbAddrB_reg8(Intra_mbAddrB_reg8),
|
.Intra_mbAddrB_reg8(Intra_mbAddrB_reg8),
|
.Intra_mbAddrB_reg9(Intra_mbAddrB_reg9),
|
.Intra_mbAddrB_reg9(Intra_mbAddrB_reg9),
|
.Intra_mbAddrB_reg10(Intra_mbAddrB_reg10),
|
.Intra_mbAddrB_reg10(Intra_mbAddrB_reg10),
|
.Intra_mbAddrB_reg11(Intra_mbAddrB_reg11),
|
.Intra_mbAddrB_reg11(Intra_mbAddrB_reg11),
|
.Intra_mbAddrB_reg12(Intra_mbAddrB_reg12),
|
.Intra_mbAddrB_reg12(Intra_mbAddrB_reg12),
|
.Intra_mbAddrB_reg13(Intra_mbAddrB_reg13),
|
.Intra_mbAddrB_reg13(Intra_mbAddrB_reg13),
|
.Intra_mbAddrB_reg14(Intra_mbAddrB_reg14),
|
.Intra_mbAddrB_reg14(Intra_mbAddrB_reg14),
|
.Intra_mbAddrB_reg15(Intra_mbAddrB_reg15),
|
.Intra_mbAddrB_reg15(Intra_mbAddrB_reg15),
|
.Intra_mbAddrC_window0(Intra_mbAddrC_window0),
|
.Intra_mbAddrC_window0(Intra_mbAddrC_window0),
|
.Intra_mbAddrC_window1(Intra_mbAddrC_window1),
|
.Intra_mbAddrC_window1(Intra_mbAddrC_window1),
|
.Intra_mbAddrC_window2(Intra_mbAddrC_window2),
|
.Intra_mbAddrC_window2(Intra_mbAddrC_window2),
|
.Intra_mbAddrC_window3(Intra_mbAddrC_window3),
|
.Intra_mbAddrC_window3(Intra_mbAddrC_window3),
|
.Intra_mbAddrD_window(Intra_mbAddrD_window),
|
.Intra_mbAddrD_window(Intra_mbAddrD_window),
|
.seed(seed)
|
.seed(seed)
|
);
|
);
|
|
|
Intra_pred_PE Intra_pred_PE (
|
Intra_pred_PE Intra_pred_PE (
|
.clk(clk),
|
.clk(clk),
|
.reset_n(reset_n),
|
.reset_n(reset_n),
|
.mb_type_general(mb_type_general),
|
.mb_type_general(mb_type_general),
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
.Intra4x4_predmode(Intra4x4_predmode),
|
.Intra4x4_predmode(Intra4x4_predmode),
|
.Intra16x16_predmode(Intra16x16_predmode),
|
.Intra16x16_predmode(Intra16x16_predmode),
|
.Intra_chroma_predmode(Intra_chroma_predmode),
|
.Intra_chroma_predmode(Intra_chroma_predmode),
|
.blkAddrA_availability(blkAddrA_availability),
|
.blkAddrA_availability(blkAddrA_availability),
|
.blkAddrB_availability(blkAddrB_availability),
|
.blkAddrB_availability(blkAddrB_availability),
|
.mbAddrA_availability(mbAddrA_availability),
|
.mbAddrA_availability(mbAddrA_availability),
|
.mbAddrB_availability(mbAddrB_availability),
|
.mbAddrB_availability(mbAddrB_availability),
|
.Intra_mbAddrA_window0({8'b0,Intra_mbAddrA_window0}),
|
.Intra_mbAddrA_window0({8'b0,Intra_mbAddrA_window0}),
|
.Intra_mbAddrA_window1({8'b0,Intra_mbAddrA_window1}),
|
.Intra_mbAddrA_window1({8'b0,Intra_mbAddrA_window1}),
|
.Intra_mbAddrA_window2({8'b0,Intra_mbAddrA_window2}),
|
.Intra_mbAddrA_window2({8'b0,Intra_mbAddrA_window2}),
|
.Intra_mbAddrA_window3({8'b0,Intra_mbAddrA_window3}),
|
.Intra_mbAddrA_window3({8'b0,Intra_mbAddrA_window3}),
|
.Intra_mbAddrB_window0({8'b0,Intra_mbAddrB_window0}),
|
.Intra_mbAddrB_window0({8'b0,Intra_mbAddrB_window0}),
|
.Intra_mbAddrB_window1({8'b0,Intra_mbAddrB_window1}),
|
.Intra_mbAddrB_window1({8'b0,Intra_mbAddrB_window1}),
|
.Intra_mbAddrB_window2({8'b0,Intra_mbAddrB_window2}),
|
.Intra_mbAddrB_window2({8'b0,Intra_mbAddrB_window2}),
|
.Intra_mbAddrB_window3({8'b0,Intra_mbAddrB_window3}),
|
.Intra_mbAddrB_window3({8'b0,Intra_mbAddrB_window3}),
|
.Intra_mbAddrC_window0({8'b0,Intra_mbAddrC_window0}),
|
.Intra_mbAddrC_window0({8'b0,Intra_mbAddrC_window0}),
|
.Intra_mbAddrC_window1({8'b0,Intra_mbAddrC_window1}),
|
.Intra_mbAddrC_window1({8'b0,Intra_mbAddrC_window1}),
|
.Intra_mbAddrC_window2({8'b0,Intra_mbAddrC_window2}),
|
.Intra_mbAddrC_window2({8'b0,Intra_mbAddrC_window2}),
|
.Intra_mbAddrC_window3({8'b0,Intra_mbAddrC_window3}),
|
.Intra_mbAddrC_window3({8'b0,Intra_mbAddrC_window3}),
|
.Intra_mbAddrD_window({8'b0,Intra_mbAddrD_window}),
|
.Intra_mbAddrD_window({8'b0,Intra_mbAddrD_window}),
|
.Intra_mbAddrA_reg0({8'b0,Intra_mbAddrA_reg0}),
|
.Intra_mbAddrA_reg0({8'b0,Intra_mbAddrA_reg0}),
|
.Intra_mbAddrA_reg1({8'b0,Intra_mbAddrA_reg1}),
|
.Intra_mbAddrA_reg1({8'b0,Intra_mbAddrA_reg1}),
|
.Intra_mbAddrA_reg2({8'b0,Intra_mbAddrA_reg2}),
|
.Intra_mbAddrA_reg2({8'b0,Intra_mbAddrA_reg2}),
|
.Intra_mbAddrA_reg3({8'b0,Intra_mbAddrA_reg3}),
|
.Intra_mbAddrA_reg3({8'b0,Intra_mbAddrA_reg3}),
|
.Intra_mbAddrA_reg4({8'b0,Intra_mbAddrA_reg4}),
|
.Intra_mbAddrA_reg4({8'b0,Intra_mbAddrA_reg4}),
|
.Intra_mbAddrA_reg5({8'b0,Intra_mbAddrA_reg5}),
|
.Intra_mbAddrA_reg5({8'b0,Intra_mbAddrA_reg5}),
|
.Intra_mbAddrA_reg6({8'b0,Intra_mbAddrA_reg6}),
|
.Intra_mbAddrA_reg6({8'b0,Intra_mbAddrA_reg6}),
|
.Intra_mbAddrA_reg7({8'b0,Intra_mbAddrA_reg7}),
|
.Intra_mbAddrA_reg7({8'b0,Intra_mbAddrA_reg7}),
|
.Intra_mbAddrA_reg8({8'b0,Intra_mbAddrA_reg8}),
|
.Intra_mbAddrA_reg8({8'b0,Intra_mbAddrA_reg8}),
|
.Intra_mbAddrA_reg9({8'b0,Intra_mbAddrA_reg9}),
|
.Intra_mbAddrA_reg9({8'b0,Intra_mbAddrA_reg9}),
|
.Intra_mbAddrA_reg10({8'b0,Intra_mbAddrA_reg10}),
|
.Intra_mbAddrA_reg10({8'b0,Intra_mbAddrA_reg10}),
|
.Intra_mbAddrA_reg11({8'b0,Intra_mbAddrA_reg11}),
|
.Intra_mbAddrA_reg11({8'b0,Intra_mbAddrA_reg11}),
|
.Intra_mbAddrA_reg12({8'b0,Intra_mbAddrA_reg12}),
|
.Intra_mbAddrA_reg12({8'b0,Intra_mbAddrA_reg12}),
|
.Intra_mbAddrA_reg13({8'b0,Intra_mbAddrA_reg13}),
|
.Intra_mbAddrA_reg13({8'b0,Intra_mbAddrA_reg13}),
|
.Intra_mbAddrA_reg14({8'b0,Intra_mbAddrA_reg14}),
|
.Intra_mbAddrA_reg14({8'b0,Intra_mbAddrA_reg14}),
|
.Intra_mbAddrA_reg15({8'b0,Intra_mbAddrA_reg15}),
|
.Intra_mbAddrA_reg15({8'b0,Intra_mbAddrA_reg15}),
|
.Intra_mbAddrB_reg0({8'b0,Intra_mbAddrB_reg0}),
|
.Intra_mbAddrB_reg0({8'b0,Intra_mbAddrB_reg0}),
|
.Intra_mbAddrB_reg1({8'b0,Intra_mbAddrB_reg1}),
|
.Intra_mbAddrB_reg1({8'b0,Intra_mbAddrB_reg1}),
|
.Intra_mbAddrB_reg2({8'b0,Intra_mbAddrB_reg2}),
|
.Intra_mbAddrB_reg2({8'b0,Intra_mbAddrB_reg2}),
|
.Intra_mbAddrB_reg3({8'b0,Intra_mbAddrB_reg3}),
|
.Intra_mbAddrB_reg3({8'b0,Intra_mbAddrB_reg3}),
|
.Intra_mbAddrB_reg4({8'b0,Intra_mbAddrB_reg4}),
|
.Intra_mbAddrB_reg4({8'b0,Intra_mbAddrB_reg4}),
|
.Intra_mbAddrB_reg5({8'b0,Intra_mbAddrB_reg5}),
|
.Intra_mbAddrB_reg5({8'b0,Intra_mbAddrB_reg5}),
|
.Intra_mbAddrB_reg6({8'b0,Intra_mbAddrB_reg6}),
|
.Intra_mbAddrB_reg6({8'b0,Intra_mbAddrB_reg6}),
|
.Intra_mbAddrB_reg7({8'b0,Intra_mbAddrB_reg7}),
|
.Intra_mbAddrB_reg7({8'b0,Intra_mbAddrB_reg7}),
|
.Intra_mbAddrB_reg8({8'b0,Intra_mbAddrB_reg8}),
|
.Intra_mbAddrB_reg8({8'b0,Intra_mbAddrB_reg8}),
|
.Intra_mbAddrB_reg9({8'b0,Intra_mbAddrB_reg9}),
|
.Intra_mbAddrB_reg9({8'b0,Intra_mbAddrB_reg9}),
|
.Intra_mbAddrB_reg10({8'b0,Intra_mbAddrB_reg10}),
|
.Intra_mbAddrB_reg10({8'b0,Intra_mbAddrB_reg10}),
|
.Intra_mbAddrB_reg11({8'b0,Intra_mbAddrB_reg11}),
|
.Intra_mbAddrB_reg11({8'b0,Intra_mbAddrB_reg11}),
|
.Intra_mbAddrB_reg12({8'b0,Intra_mbAddrB_reg12}),
|
.Intra_mbAddrB_reg12({8'b0,Intra_mbAddrB_reg12}),
|
.Intra_mbAddrB_reg13({8'b0,Intra_mbAddrB_reg13}),
|
.Intra_mbAddrB_reg13({8'b0,Intra_mbAddrB_reg13}),
|
.Intra_mbAddrB_reg14({8'b0,Intra_mbAddrB_reg14}),
|
.Intra_mbAddrB_reg14({8'b0,Intra_mbAddrB_reg14}),
|
.Intra_mbAddrB_reg15({8'b0,Intra_mbAddrB_reg15}),
|
.Intra_mbAddrB_reg15({8'b0,Intra_mbAddrB_reg15}),
|
.blk4x4_pred_output0({8'b0,blk4x4_pred_output0}),
|
.blk4x4_pred_output0({8'b0,blk4x4_pred_output0}),
|
.blk4x4_pred_output1({8'b0,blk4x4_pred_output1}),
|
.blk4x4_pred_output1({8'b0,blk4x4_pred_output1}),
|
.blk4x4_pred_output2({8'b0,blk4x4_pred_output2}),
|
.blk4x4_pred_output2({8'b0,blk4x4_pred_output2}),
|
.blk4x4_pred_output4({8'b0,blk4x4_pred_output4}),
|
.blk4x4_pred_output4({8'b0,blk4x4_pred_output4}),
|
.blk4x4_pred_output5({8'b0,blk4x4_pred_output5}),
|
.blk4x4_pred_output5({8'b0,blk4x4_pred_output5}),
|
.blk4x4_pred_output6({8'b0,blk4x4_pred_output6}),
|
.blk4x4_pred_output6({8'b0,blk4x4_pred_output6}),
|
.blk4x4_pred_output8({8'b0,blk4x4_pred_output8}),
|
.blk4x4_pred_output8({8'b0,blk4x4_pred_output8}),
|
.blk4x4_pred_output9({8'b0,blk4x4_pred_output9}),
|
.blk4x4_pred_output9({8'b0,blk4x4_pred_output9}),
|
.blk4x4_pred_output10({8'b0,blk4x4_pred_output10}),
|
.blk4x4_pred_output10({8'b0,blk4x4_pred_output10}),
|
.blk4x4_pred_output12({8'b0,blk4x4_pred_output12}),
|
.blk4x4_pred_output12({8'b0,blk4x4_pred_output12}),
|
.blk4x4_pred_output13({8'b0,blk4x4_pred_output13}),
|
.blk4x4_pred_output13({8'b0,blk4x4_pred_output13}),
|
.blk4x4_pred_output14({8'b0,blk4x4_pred_output14}),
|
.blk4x4_pred_output14({8'b0,blk4x4_pred_output14}),
|
.seed(seed),
|
.seed(seed),
|
.b(plane_b_reg),
|
.b(plane_b_reg),
|
.c(plane_c_reg),
|
.c(plane_c_reg),
|
|
|
.PE0_out(PE0_out),
|
.PE0_out(PE0_out),
|
.PE1_out(PE1_out),
|
.PE1_out(PE1_out),
|
.PE2_out(PE2_out),
|
.PE2_out(PE2_out),
|
.PE3_out(PE3_out),
|
.PE3_out(PE3_out),
|
.PE0_sum_out(PE0_sum_out),
|
.PE0_sum_out(PE0_sum_out),
|
.PE3_sum_out(PE3_sum_out)
|
.PE3_sum_out(PE3_sum_out)
|
);
|
);
|
ram_sync_1r_sync_1w #(`Intra_mbAddrB_RAM_data_width,`Intra_mbAddrB_RAM_data_depth)
|
ram_sync_1r_sync_1w #(`Intra_mbAddrB_RAM_data_width,`Intra_mbAddrB_RAM_data_depth)
|
Intra_mbAddrB_RAM (
|
Intra_mbAddrB_RAM (
|
.clk(gclk_Intra_mbAddrB_RAM),
|
.clk(gclk_Intra_mbAddrB_RAM),
|
.rst_n(reset_n),
|
.rst_n(reset_n),
|
.wr_n(~Intra_mbAddrB_RAM_wr),
|
.wr_n(~Intra_mbAddrB_RAM_wr),
|
.rd_n(~Intra_mbAddrB_RAM_rd),
|
.rd_n(~Intra_mbAddrB_RAM_rd),
|
.wr_addr(Intra_mbAddrB_RAM_wr_addr),
|
.wr_addr(Intra_mbAddrB_RAM_wr_addr),
|
.rd_addr(Intra_mbAddrB_RAM_rd_addr),
|
.rd_addr(Intra_mbAddrB_RAM_rd_addr),
|
.data_in(Intra_mbAddrB_RAM_din),
|
.data_in(Intra_mbAddrB_RAM_din),
|
.data_out(Intra_mbAddrB_RAM_dout)
|
.data_out(Intra_mbAddrB_RAM_dout)
|
);
|
);
|
|
|
