//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : bitstream_gclk_gen.v
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// File : bitstream_gclk_gen.v
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// Generated : Jan 9,2005
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// Generated : Jan 9,2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Gated clock generation module for bitstream controller
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// Gated clock generation module for bitstream controller
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module bitstream_gclk_gen (clk,reset_n,freq_ctrl0,freq_ctrl1,parser_state,nal_unit_state,slice_layer_wo_partitioning_state,
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module bitstream_gclk_gen (clk,reset_n,freq_ctrl0,freq_ctrl1,parser_state,nal_unit_state,slice_layer_wo_partitioning_state,
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slice_header_state,slice_data_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state,
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slice_header_state,slice_data_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state,
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mb_num,TotalCoeff,start_code_prefix_found,pc_2to0,deblocking_filter_control_present_flag,
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mb_num,TotalCoeff,start_code_prefix_found,pc_2to0,deblocking_filter_control_present_flag,
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disable_deblocking_filter_idc,end_of_one_residual_block,
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disable_deblocking_filter_idc,end_of_one_residual_block,
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Intra4x4PredMode_mbAddrB_cs_n,mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n,
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Intra4x4PredMode_mbAddrB_cs_n,mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n,
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LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n,
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LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n,
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trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,disable_DF,bs_dec_counter,
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trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,disable_DF,bs_dec_counter,
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gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps,
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gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps,
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gclk_slice_header,gclk_slice_data,gclk_residual,gclk_cavlc,
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gclk_slice_header,gclk_slice_data,gclk_residual,gclk_cavlc,
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gclk_Intra4x4PredMode_mbAddrB_RF,
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gclk_Intra4x4PredMode_mbAddrB_RF,
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gclk_mvx_mbAddrB_RF,gclk_mvy_mbAddrB_RF,gclk_mvx_mbAddrC_RF,gclk_mvy_mbAddrC_RF,
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gclk_mvx_mbAddrB_RF,gclk_mvy_mbAddrB_RF,gclk_mvx_mbAddrC_RF,gclk_mvy_mbAddrC_RF,
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gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF,gclk_bs_dec,
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gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF,gclk_bs_dec,
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end_of_one_frame);
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end_of_one_frame);
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input clk;
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input clk;
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input reset_n;
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input reset_n;
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input freq_ctrl0;
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input freq_ctrl0;
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input freq_ctrl1;
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input freq_ctrl1;
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input [1:0] parser_state;
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input [1:0] parser_state;
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input [2:0] nal_unit_state;
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input [2:0] nal_unit_state;
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input [1:0] slice_layer_wo_partitioning_state;
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input [1:0] slice_layer_wo_partitioning_state;
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input [3:0] slice_header_state;
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input [3:0] slice_header_state;
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input [3:0] slice_data_state;
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input [3:0] slice_data_state;
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input [3:0] seq_parameter_set_state;
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input [3:0] seq_parameter_set_state;
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input [3:0] pic_parameter_set_state;
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input [3:0] pic_parameter_set_state;
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input [3:0] residual_state;
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input [3:0] residual_state;
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input [3:0] cavlc_decoder_state;
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input [3:0] cavlc_decoder_state;
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input [6:0] mb_num;
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input [6:0] mb_num;
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input [4:0] TotalCoeff;
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input [4:0] TotalCoeff;
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input start_code_prefix_found;
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input start_code_prefix_found;
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input [2:0] pc_2to0;
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input [2:0] pc_2to0;
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input deblocking_filter_control_present_flag;
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input deblocking_filter_control_present_flag;
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input [1:0] disable_deblocking_filter_idc;
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input [1:0] disable_deblocking_filter_idc;
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input end_of_one_residual_block;
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input end_of_one_residual_block;
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input Intra4x4PredMode_mbAddrB_cs_n;
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input Intra4x4PredMode_mbAddrB_cs_n;
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input mvx_mbAddrB_cs_n;
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input mvx_mbAddrB_cs_n;
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input mvy_mbAddrB_cs_n;
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input mvy_mbAddrB_cs_n;
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input mvx_mbAddrC_cs_n;
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input mvx_mbAddrC_cs_n;
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input mvy_mbAddrC_cs_n;
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input mvy_mbAddrC_cs_n;
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input LumaLevel_mbAddrB_cs_n;
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input LumaLevel_mbAddrB_cs_n;
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input ChromaLevel_Cb_mbAddrB_cs_n;
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input ChromaLevel_Cb_mbAddrB_cs_n;
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input ChromaLevel_Cr_mbAddrB_cs_n;
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input ChromaLevel_Cr_mbAddrB_cs_n;
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input trigger_CAVLC;
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input trigger_CAVLC;
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input [4:0] blk4x4_rec_counter;
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input [4:0] blk4x4_rec_counter;
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input end_of_DCBlk_IQIT;
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input end_of_DCBlk_IQIT;
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input end_of_one_blk4x4_sum;
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input end_of_one_blk4x4_sum;
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input end_of_MB_DEC;
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input end_of_MB_DEC;
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input disable_DF;
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input disable_DF;
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input [1:0] bs_dec_counter;
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input [1:0] bs_dec_counter;
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output gclk_parser;
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output gclk_parser;
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output gclk_nal;
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output gclk_nal;
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output gclk_slice;
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output gclk_slice;
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output gclk_sps;
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output gclk_sps;
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output gclk_pps;
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output gclk_pps;
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output gclk_slice_header;
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output gclk_slice_header;
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output gclk_slice_data;
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output gclk_slice_data;
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output gclk_residual;
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output gclk_residual;
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output gclk_cavlc;
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output gclk_cavlc;
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output gclk_Intra4x4PredMode_mbAddrB_RF;
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output gclk_Intra4x4PredMode_mbAddrB_RF;
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output gclk_mvx_mbAddrB_RF;
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output gclk_mvx_mbAddrB_RF;
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output gclk_mvy_mbAddrB_RF;
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output gclk_mvy_mbAddrB_RF;
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output gclk_mvx_mbAddrC_RF;
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output gclk_mvx_mbAddrC_RF;
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output gclk_mvy_mbAddrC_RF;
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output gclk_mvy_mbAddrC_RF;
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output gclk_LumaLevel_mbAddrB_RF;
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output gclk_LumaLevel_mbAddrB_RF;
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output gclk_ChromaLevel_Cb_mbAddrB_RF;
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output gclk_ChromaLevel_Cb_mbAddrB_RF;
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output gclk_ChromaLevel_Cr_mbAddrB_RF;
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output gclk_ChromaLevel_Cr_mbAddrB_RF;
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output gclk_bs_dec;
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output gclk_bs_dec;
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output end_of_one_frame;
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output end_of_one_frame;
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//Input pin freq_ctrl0 & freq_ctrl1 can be used to adjust frequency after the chip is fabricated
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//Input pin freq_ctrl0 & freq_ctrl1 can be used to adjust frequency after the chip is fabricated
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reg [16:0] cycles_per_frame;
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reg [16:0] cycles_per_frame;
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always @ (freq_ctrl0 or freq_ctrl1)
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always @ (freq_ctrl0 or freq_ctrl1)
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case ({freq_ctrl1,freq_ctrl0})
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case ({freq_ctrl1,freq_ctrl0})
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2'b00:cycles_per_frame <= `cycles_per_frame0;
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2'b00:cycles_per_frame <= `cycles_per_frame0;
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2'b01:cycles_per_frame <= `cycles_per_frame1;
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2'b01:cycles_per_frame <= `cycles_per_frame1;
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2'b11:cycles_per_frame <= `cycles_per_frame3;
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2'b11:cycles_per_frame <= `cycles_per_frame3;
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default:cycles_per_frame <= `cycles_per_frame2;
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default:cycles_per_frame <= `cycles_per_frame2;
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endcase
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endcase
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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// decoding rate control
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// decoding rate control
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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reg [16:0] frame_cycle_counter;
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reg [16:0] frame_cycle_counter;
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reg end_of_one_frame;
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reg end_of_one_frame;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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begin
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begin
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frame_cycle_counter <= 0;
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frame_cycle_counter <= 0;
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end_of_one_frame <= 1'b0;
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end_of_one_frame <= 1'b0;
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end
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end
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else if (parser_state == `start_code_prefix)
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else if (parser_state == `start_code_prefix)
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begin
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begin
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frame_cycle_counter <= 0;
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frame_cycle_counter <= 0;
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end_of_one_frame <= 1'b0;
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end_of_one_frame <= 1'b0;
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end
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end
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else if (frame_cycle_counter < cycles_per_frame)
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else if (frame_cycle_counter < cycles_per_frame)
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begin
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begin
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frame_cycle_counter <= frame_cycle_counter + 1;
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frame_cycle_counter <= frame_cycle_counter + 1;
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end_of_one_frame <= 1'b0;
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end_of_one_frame <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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frame_cycle_counter <= 0;
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frame_cycle_counter <= 0;
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end_of_one_frame <= 1'b1;
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end_of_one_frame <= 1'b1;
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end
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end
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//PPS and SPS doesn't need rate control,so after PPS/SPS decoding,bitstream parser should continue
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//PPS and SPS doesn't need rate control,so after PPS/SPS decoding,bitstream parser should continue
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//without waiting for "end_of_one_frame" signal when parser_state == rst_parser.
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//without waiting for "end_of_one_frame" signal when parser_state == rst_parser.
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//PPS_SPS_complete is used to identify whether next nal_unit to be decoded is PPS/SPS or normal frame
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//PPS_SPS_complete is used to identify whether next nal_unit to be decoded is PPS/SPS or normal frame
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reg PPS_SPS_complete;
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reg PPS_SPS_complete;
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always @ (posedge gclk_slice or negedge reset_n)
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always @ (posedge gclk_slice or negedge reset_n)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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PPS_SPS_complete <= 1'b0;
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PPS_SPS_complete <= 1'b0;
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else if (slice_layer_wo_partitioning_state == `slice_header)
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else if (slice_layer_wo_partitioning_state == `slice_header)
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PPS_SPS_complete <= 1'b1;
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PPS_SPS_complete <= 1'b1;
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//1.gclk_parser
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//1.gclk_parser
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wire parser_ena;
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wire parser_ena;
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reg l_parser_ena;
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reg l_parser_ena;
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wire gclk_parser;
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wire gclk_parser;
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assign parser_ena = (
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assign parser_ena = (
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(parser_state == `rst_parser && (!PPS_SPS_complete || (PPS_SPS_complete && end_of_one_frame))) ||
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(parser_state == `rst_parser && (!PPS_SPS_complete || (PPS_SPS_complete && end_of_one_frame))) ||
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(parser_state == `start_code_prefix && start_code_prefix_found == 1'b1) ||
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(parser_state == `start_code_prefix && start_code_prefix_found == 1'b1) ||
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(nal_unit_state == `rbsp_trailing_one_bit && pc_2to0 == 3'b000) ||
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(nal_unit_state == `rbsp_trailing_one_bit && pc_2to0 == 3'b000) ||
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nal_unit_state == `rbsp_trailing_zero_bits)? 1'b1:1'b0;
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nal_unit_state == `rbsp_trailing_zero_bits)? 1'b1:1'b0;
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always @ (clk or parser_ena)
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always @ (clk or parser_ena)
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if (!clk) l_parser_ena <= parser_ena;
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if (!clk) l_parser_ena <= parser_ena;
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assign gclk_parser = l_parser_ena & clk;
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assign gclk_parser = l_parser_ena & clk;
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//2.gclk_nal
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//2.gclk_nal
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//including rate control for end of one frame
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//including rate control for end of one frame
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wire nal_ena;
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wire nal_ena;
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reg l_nal_ena;
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reg l_nal_ena;
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wire gclk_nal;
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wire gclk_nal;
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assign nal_ena = (parser_state == `nal_unit && (
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assign nal_ena = (parser_state == `nal_unit && (
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nal_unit_state == `rst_nal_unit ||
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nal_unit_state == `rst_nal_unit ||
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nal_unit_state == `forbidden_zero_bit_2_nal_unit_type ||
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nal_unit_state == `forbidden_zero_bit_2_nal_unit_type ||
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(((slice_data_state == `skip_run_duration && end_of_MB_DEC)|| slice_data_state == `mb_num_update)
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(((slice_data_state == `skip_run_duration && end_of_MB_DEC)|| slice_data_state == `mb_num_update)
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&& mb_num == 98) ||
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&& mb_num == 98) ||
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seq_parameter_set_state == `vui_parameter_present_flag_s ||
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seq_parameter_set_state == `vui_parameter_present_flag_s ||
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pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag ||
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pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag ||
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nal_unit_state == `rbsp_trailing_one_bit ||
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nal_unit_state == `rbsp_trailing_one_bit ||
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nal_unit_state == `rbsp_trailing_zero_bits))? 1'b1:1'b0;
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nal_unit_state == `rbsp_trailing_zero_bits))? 1'b1:1'b0;
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always @ (clk or nal_ena)
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always @ (clk or nal_ena)
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if (!clk) l_nal_ena <= nal_ena;
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if (!clk) l_nal_ena <= nal_ena;
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assign gclk_nal = l_nal_ena & clk;
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assign gclk_nal = l_nal_ena & clk;
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//3.gclk_slice:for slice_layer_wo_partitioning_state FSM
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//3.gclk_slice:for slice_layer_wo_partitioning_state FSM
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wire slice_ena;
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wire slice_ena;
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reg l_slice_ena;
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reg l_slice_ena;
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wire gclk_slice;
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wire gclk_slice;
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assign slice_ena = (
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assign slice_ena = (
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(nal_unit_state == `slice_layer_non_IDR_rbsp || nal_unit_state == `slice_layer_IDR_rbsp) &&
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(nal_unit_state == `slice_layer_non_IDR_rbsp || nal_unit_state == `slice_layer_IDR_rbsp) &&
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(slice_layer_wo_partitioning_state == `rst_slice_layer_wo_partitioning ||
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(slice_layer_wo_partitioning_state == `rst_slice_layer_wo_partitioning ||
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(slice_header_state == `slice_qp_delta_s && deblocking_filter_control_present_flag == 1'b0) ||
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(slice_header_state == `slice_qp_delta_s && deblocking_filter_control_present_flag == 1'b0) ||
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(slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 2'b01) ||
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(slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 2'b01) ||
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slice_header_state == `slice_beta_offset_div2_s ||
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slice_header_state == `slice_beta_offset_div2_s ||
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(((slice_data_state == `skip_run_duration && end_of_MB_DEC) || slice_data_state == `mb_num_update)
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(((slice_data_state == `skip_run_duration && end_of_MB_DEC) || slice_data_state == `mb_num_update)
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&& mb_num == 98)))? 1'b1:1'b0;
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&& mb_num == 98)))? 1'b1:1'b0;
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always @ (clk or slice_ena)
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always @ (clk or slice_ena)
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if (!clk) l_slice_ena <= slice_ena;
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if (!clk) l_slice_ena <= slice_ena;
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assign gclk_slice = l_slice_ena & clk;
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assign gclk_slice = l_slice_ena & clk;
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//4.gclk_sps
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//4.gclk_sps
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wire sps_ena;
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wire sps_ena;
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reg l_sps_ena;
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reg l_sps_ena;
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wire gclk_sps;
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wire gclk_sps;
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assign sps_ena = (nal_unit_state == `seq_parameter_set_rbsp)? 1'b1:1'b0;
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assign sps_ena = (nal_unit_state == `seq_parameter_set_rbsp)? 1'b1:1'b0;
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always @ (clk or sps_ena)
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always @ (clk or sps_ena)
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if (!clk) l_sps_ena <= sps_ena;
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if (!clk) l_sps_ena <= sps_ena;
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assign gclk_sps = l_sps_ena & clk;
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assign gclk_sps = l_sps_ena & clk;
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//5.gclk_pps
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//5.gclk_pps
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wire pps_ena;
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wire pps_ena;
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reg l_pps_ena;
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reg l_pps_ena;
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wire gclk_pps;
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wire gclk_pps;
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assign pps_ena = (nal_unit_state == `pic_parameter_set_rbsp)? 1'b1:1'b0;
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assign pps_ena = (nal_unit_state == `pic_parameter_set_rbsp)? 1'b1:1'b0;
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always @ (clk or pps_ena)
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always @ (clk or pps_ena)
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if (!clk) l_pps_ena <= pps_ena;
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if (!clk) l_pps_ena <= pps_ena;
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assign gclk_pps = l_pps_ena & clk;
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assign gclk_pps = l_pps_ena & clk;
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//6.gclk_slice_header
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//6.gclk_slice_header
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wire slice_header_ena;
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wire slice_header_ena;
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reg l_slice_header_ena;
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reg l_slice_header_ena;
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wire gclk_slice_header;
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wire gclk_slice_header;
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assign slice_header_ena = (slice_layer_wo_partitioning_state == `slice_header)? 1'b1:1'b0;
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assign slice_header_ena = (slice_layer_wo_partitioning_state == `slice_header)? 1'b1:1'b0;
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always @ (clk or slice_header_ena)
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always @ (clk or slice_header_ena)
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if (!clk) l_slice_header_ena <= slice_header_ena;
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if (!clk) l_slice_header_ena <= slice_header_ena;
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assign gclk_slice_header = l_slice_header_ena & clk;
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assign gclk_slice_header = l_slice_header_ena & clk;
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//7.gclk_slice_data
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//7.gclk_slice_data
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//including rate control for skipped macroblock:skip_run_duration
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//including rate control for skipped macroblock:skip_run_duration
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//including rate control for normal macroblock:mb_num_update
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//including rate control for normal macroblock:mb_num_update
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wire slice_data_ena;
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wire slice_data_ena;
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reg l_slice_data_ena;
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reg l_slice_data_ena;
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wire gclk_slice_data;
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wire gclk_slice_data;
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assign slice_data_ena = (slice_layer_wo_partitioning_state == `slice_data && (
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assign slice_data_ena = (slice_layer_wo_partitioning_state == `slice_data && (
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(slice_data_state != `skip_run_duration && slice_data_state != `residual) ||
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(slice_data_state != `skip_run_duration && slice_data_state != `residual) ||
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(slice_data_state == `skip_run_duration && end_of_MB_DEC == 1'b1) ||
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(slice_data_state == `skip_run_duration && end_of_MB_DEC == 1'b1) ||
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(slice_data_state == `residual && end_of_MB_DEC == 1'b1)))? 1'b1:1'b0;
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(slice_data_state == `residual && end_of_MB_DEC == 1'b1)))? 1'b1:1'b0;
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always @ (clk or slice_data_ena)
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always @ (clk or slice_data_ena)
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if (!clk) l_slice_data_ena <= slice_data_ena;
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if (!clk) l_slice_data_ena <= slice_data_ena;
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assign gclk_slice_data = l_slice_data_ena & clk;
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assign gclk_slice_data = l_slice_data_ena & clk;
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//8.gclk_residual
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//8.gclk_residual
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wire residual_ena;
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wire residual_ena;
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reg l_residual_ena;
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reg l_residual_ena;
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wire gclk_residual;
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wire gclk_residual;
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assign residual_ena = (slice_data_state == `residual &&
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assign residual_ena = (slice_data_state == `residual &&
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(residual_state == `rst_residual ||
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(residual_state == `rst_residual ||
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|
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((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s
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((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s
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|| residual_state == `ChromaDCLevel_Cr_s) &&
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|| residual_state == `ChromaDCLevel_Cr_s) &&
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((end_of_one_residual_block == 1 && TotalCoeff == 0) || end_of_DCBlk_IQIT)) ||
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((end_of_one_residual_block == 1 && TotalCoeff == 0) || end_of_DCBlk_IQIT)) ||
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|
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((residual_state == `Intra16x16ACLevel_s || residual_state == `Intra16x16ACLevel_0_s
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((residual_state == `Intra16x16ACLevel_s || residual_state == `Intra16x16ACLevel_0_s
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|| residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s)
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|| residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s)
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&& blk4x4_rec_counter == 15 && end_of_one_blk4x4_sum == 1) ||
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&& blk4x4_rec_counter == 15 && end_of_one_blk4x4_sum == 1) ||
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(residual_state == `ChromaACLevel_Cb_s && blk4x4_rec_counter == 19 && end_of_one_blk4x4_sum == 1) ||
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(residual_state == `ChromaACLevel_Cb_s && blk4x4_rec_counter == 19 && end_of_one_blk4x4_sum == 1) ||
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(residual_state == `ChromaACLevel_Cr_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1) ||
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(residual_state == `ChromaACLevel_Cr_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1) ||
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(residual_state == `ChromaACLevel_0_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1)))? 1'b1:1'b0;
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(residual_state == `ChromaACLevel_0_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1)))? 1'b1:1'b0;
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|
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always @ (clk or residual_ena)
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always @ (clk or residual_ena)
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if (!clk) l_residual_ena <= residual_ena;
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if (!clk) l_residual_ena <= residual_ena;
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assign gclk_residual = l_residual_ena & clk;
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assign gclk_residual = l_residual_ena & clk;
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|
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//9.gclk_cavlc
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//9.gclk_cavlc
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wire cavlc_ena;
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wire cavlc_ena;
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reg l_cavlc_ena;
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reg l_cavlc_ena;
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wire gclk_cavlc;
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wire gclk_cavlc;
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assign cavlc_ena = (slice_data_state == `residual && (cavlc_decoder_state != `rst_cavlc_decoder ||
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assign cavlc_ena = (slice_data_state == `residual && (cavlc_decoder_state != `rst_cavlc_decoder ||
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(cavlc_decoder_state == `rst_cavlc_decoder && trigger_CAVLC)))? 1'b1:1'b0;
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(cavlc_decoder_state == `rst_cavlc_decoder && trigger_CAVLC)))? 1'b1:1'b0;
|
|
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always @ (clk or cavlc_ena)
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always @ (clk or cavlc_ena)
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if (!clk) l_cavlc_ena <= cavlc_ena;
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if (!clk) l_cavlc_ena <= cavlc_ena;
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assign gclk_cavlc = l_cavlc_ena & clk;
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assign gclk_cavlc = l_cavlc_ena & clk;
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|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
//gclk for bitstream controller register file
|
//gclk for bitstream controller register file
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
//1.gclk_Intra4x4PredMode_mbAddrB_RF
|
//1.gclk_Intra4x4PredMode_mbAddrB_RF
|
reg l_Intra4x4PredMode_mbAddrB_RF_ena;
|
reg l_Intra4x4PredMode_mbAddrB_RF_ena;
|
wire gclk_Intra4x4PredMode_mbAddrB_RF;
|
wire gclk_Intra4x4PredMode_mbAddrB_RF;
|
always @ (clk or Intra4x4PredMode_mbAddrB_cs_n)
|
always @ (clk or Intra4x4PredMode_mbAddrB_cs_n)
|
if (!clk) l_Intra4x4PredMode_mbAddrB_RF_ena <= ~Intra4x4PredMode_mbAddrB_cs_n;
|
if (!clk) l_Intra4x4PredMode_mbAddrB_RF_ena <= ~Intra4x4PredMode_mbAddrB_cs_n;
|
assign gclk_Intra4x4PredMode_mbAddrB_RF = clk & l_Intra4x4PredMode_mbAddrB_RF_ena;
|
assign gclk_Intra4x4PredMode_mbAddrB_RF = clk & l_Intra4x4PredMode_mbAddrB_RF_ena;
|
|
|
//2.gclk_mvx_mbAddrB_RF
|
//2.gclk_mvx_mbAddrB_RF
|
reg l_mvx_mbAddrB_RF_ena;
|
reg l_mvx_mbAddrB_RF_ena;
|
wire gclk_mvx_mbAddrB_RF;
|
wire gclk_mvx_mbAddrB_RF;
|
always @ (clk or mvx_mbAddrB_cs_n)
|
always @ (clk or mvx_mbAddrB_cs_n)
|
if (!clk) l_mvx_mbAddrB_RF_ena <= ~mvx_mbAddrB_cs_n;
|
if (!clk) l_mvx_mbAddrB_RF_ena <= ~mvx_mbAddrB_cs_n;
|
assign gclk_mvx_mbAddrB_RF = clk & l_mvx_mbAddrB_RF_ena;
|
assign gclk_mvx_mbAddrB_RF = clk & l_mvx_mbAddrB_RF_ena;
|
|
|
//3.gclk_mvy_mbAddrB_RF
|
//3.gclk_mvy_mbAddrB_RF
|
reg l_mvy_mbAddrB_RF_ena;
|
reg l_mvy_mbAddrB_RF_ena;
|
wire gclk_mvy_mbAddrB_RF;
|
wire gclk_mvy_mbAddrB_RF;
|
always @ (clk or mvy_mbAddrB_cs_n)
|
always @ (clk or mvy_mbAddrB_cs_n)
|
if (!clk) l_mvy_mbAddrB_RF_ena <= ~mvy_mbAddrB_cs_n;
|
if (!clk) l_mvy_mbAddrB_RF_ena <= ~mvy_mbAddrB_cs_n;
|
assign gclk_mvy_mbAddrB_RF = clk & l_mvy_mbAddrB_RF_ena;
|
assign gclk_mvy_mbAddrB_RF = clk & l_mvy_mbAddrB_RF_ena;
|
|
|
//4.gclk_mvx_mbAddrC_RF
|
//4.gclk_mvx_mbAddrC_RF
|
reg l_mvx_mbAddrC_RF_ena;
|
reg l_mvx_mbAddrC_RF_ena;
|
wire gclk_mvx_mbAddrC_RF;
|
wire gclk_mvx_mbAddrC_RF;
|
always @ (clk or mvx_mbAddrC_cs_n)
|
always @ (clk or mvx_mbAddrC_cs_n)
|
if (!clk) l_mvx_mbAddrC_RF_ena <= ~mvx_mbAddrC_cs_n;
|
if (!clk) l_mvx_mbAddrC_RF_ena <= ~mvx_mbAddrC_cs_n;
|
assign gclk_mvx_mbAddrC_RF = clk & l_mvx_mbAddrC_RF_ena;
|
assign gclk_mvx_mbAddrC_RF = clk & l_mvx_mbAddrC_RF_ena;
|
|
|
//5.gclk_mvy_mbAddrC_RF
|
//5.gclk_mvy_mbAddrC_RF
|
reg l_mvy_mbAddrC_RF_ena;
|
reg l_mvy_mbAddrC_RF_ena;
|
wire gclk_mvy_mbAddrC_RF;
|
wire gclk_mvy_mbAddrC_RF;
|
always @ (clk or mvy_mbAddrC_cs_n)
|
always @ (clk or mvy_mbAddrC_cs_n)
|
if (!clk) l_mvy_mbAddrC_RF_ena <= ~mvy_mbAddrC_cs_n;
|
if (!clk) l_mvy_mbAddrC_RF_ena <= ~mvy_mbAddrC_cs_n;
|
assign gclk_mvy_mbAddrC_RF = clk & l_mvy_mbAddrC_RF_ena;
|
assign gclk_mvy_mbAddrC_RF = clk & l_mvy_mbAddrC_RF_ena;
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
//gclk for CAVLC_decoder related regfiles
|
//gclk for CAVLC_decoder related regfiles
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
//1.gclk_LumaLevel_mbAddrB_RF
|
//1.gclk_LumaLevel_mbAddrB_RF
|
reg l_LumaLevel_mbAddrB_RF_ena;
|
reg l_LumaLevel_mbAddrB_RF_ena;
|
wire gclk_LumaLevel_mbAddrB_RF;
|
wire gclk_LumaLevel_mbAddrB_RF;
|
always @ (clk or LumaLevel_mbAddrB_cs_n)
|
always @ (clk or LumaLevel_mbAddrB_cs_n)
|
if (!clk) l_LumaLevel_mbAddrB_RF_ena <= ~LumaLevel_mbAddrB_cs_n;
|
if (!clk) l_LumaLevel_mbAddrB_RF_ena <= ~LumaLevel_mbAddrB_cs_n;
|
assign gclk_LumaLevel_mbAddrB_RF = clk & l_LumaLevel_mbAddrB_RF_ena;
|
assign gclk_LumaLevel_mbAddrB_RF = clk & l_LumaLevel_mbAddrB_RF_ena;
|
|
|
//2.gclk_ChromaLevel_Cb_mbAddrB_RF
|
//2.gclk_ChromaLevel_Cb_mbAddrB_RF
|
reg l_ChromaLevel_Cb_mbAddrB_RF_ena;
|
reg l_ChromaLevel_Cb_mbAddrB_RF_ena;
|
wire gclk_ChromaLevel_Cb_mbAddrB_RF;
|
wire gclk_ChromaLevel_Cb_mbAddrB_RF;
|
always @ (clk or ChromaLevel_Cb_mbAddrB_cs_n)
|
always @ (clk or ChromaLevel_Cb_mbAddrB_cs_n)
|
if (!clk) l_ChromaLevel_Cb_mbAddrB_RF_ena <= ~ChromaLevel_Cb_mbAddrB_cs_n;
|
if (!clk) l_ChromaLevel_Cb_mbAddrB_RF_ena <= ~ChromaLevel_Cb_mbAddrB_cs_n;
|
assign gclk_ChromaLevel_Cb_mbAddrB_RF = clk & l_ChromaLevel_Cb_mbAddrB_RF_ena;
|
assign gclk_ChromaLevel_Cb_mbAddrB_RF = clk & l_ChromaLevel_Cb_mbAddrB_RF_ena;
|
|
|
//3.gclk_ChromaLevel_Cr_mbAddrB_RF
|
//3.gclk_ChromaLevel_Cr_mbAddrB_RF
|
reg l_ChromaLevel_Cr_mbAddrB_RF_ena;
|
reg l_ChromaLevel_Cr_mbAddrB_RF_ena;
|
wire gclk_ChromaLevel_Cr_mbAddrB_RF;
|
wire gclk_ChromaLevel_Cr_mbAddrB_RF;
|
always @ (clk or ChromaLevel_Cr_mbAddrB_cs_n)
|
always @ (clk or ChromaLevel_Cr_mbAddrB_cs_n)
|
if (!clk) l_ChromaLevel_Cr_mbAddrB_RF_ena <= ~ChromaLevel_Cr_mbAddrB_cs_n;
|
if (!clk) l_ChromaLevel_Cr_mbAddrB_RF_ena <= ~ChromaLevel_Cr_mbAddrB_cs_n;
|
assign gclk_ChromaLevel_Cr_mbAddrB_RF = clk & l_ChromaLevel_Cr_mbAddrB_RF_ena;
|
assign gclk_ChromaLevel_Cr_mbAddrB_RF = clk & l_ChromaLevel_Cr_mbAddrB_RF_ena;
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
//gclk for boundary strength decoding
|
//gclk for boundary strength decoding
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
wire bs_dec_ena;
|
wire bs_dec_ena;
|
reg l_bs_dec_ena;
|
reg l_bs_dec_ena;
|
wire gclk_bs_dec;
|
wire gclk_bs_dec;
|
|
|
assign bs_dec_ena = ((end_of_MB_DEC == 1'b1 && disable_DF == 1'b0) || bs_dec_counter != 0)? 1'b1:1'b0;
|
assign bs_dec_ena = ((end_of_MB_DEC == 1'b1 && disable_DF == 1'b0) || bs_dec_counter != 0)? 1'b1:1'b0;
|
always @ (clk or bs_dec_ena)
|
always @ (clk or bs_dec_ena)
|
if (!clk) l_bs_dec_ena <= bs_dec_ena;
|
if (!clk) l_bs_dec_ena <= bs_dec_ena;
|
assign gclk_bs_dec = l_bs_dec_ena & clk;
|
assign gclk_bs_dec = l_bs_dec_ena & clk;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
