//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : end_of_blk_decoding.v
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// File : end_of_blk_decoding.v
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// Generated : June 12, 2005
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// Generated : June 12, 2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Decoding end_of_one_residual_block signal for 1 cycle duration
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// Decoding end_of_one_residual_block signal for 1 cycle duration
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// 1)for BitStream_parser_FSM to update signals such as i4x4 and direct state switch
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// 1)for BitStream_parser_FSM to update signals such as i4x4 and direct state switch
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// 2)for nC_decoding to update LumaLevel/ChromaLevel CurrMb,mbAddrA,mbAddrB
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// 2)for nC_decoding to update LumaLevel/ChromaLevel CurrMb,mbAddrA,mbAddrB
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// Decoding end_of_residual signal for 1 cycle duration
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// Decoding end_of_residual signal for 1 cycle duration
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// 1)for nC_decoding to update general control regs such as Luma_8x8_AllZeroCoeff_mbAddrA,Luma_8x8_AllZeroCoeff_mbAddrB_reg,Chroma_8x8_AllZeroCoeff_mbAddrA,Chroma_8x8_AllZeroCoeff_mbAddrB_reg
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// 1)for nC_decoding to update general control regs such as Luma_8x8_AllZeroCoeff_mbAddrA,Luma_8x8_AllZeroCoeff_mbAddrB_reg,Chroma_8x8_AllZeroCoeff_mbAddrA,Chroma_8x8_AllZeroCoeff_mbAddrB_reg
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// 2)Note:for P_skip MBs,their general control regs as *8x8_ALLZeroCoeff* are directly controlled by the state instead of end_of_residual signal
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// 2)Note:for P_skip MBs,their general control regs as *8x8_ALLZeroCoeff* are directly controlled by the state instead of end_of_residual signal
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Revise log
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// Revise log
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// 1. March 24,2006
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// 1. March 24,2006
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// Add signal end_of_NonZeroCoeff_CAVLC for IQIT to update res_AC/res_DC/... signals.
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// Add signal end_of_NonZeroCoeff_CAVLC for IQIT to update res_AC/res_DC/... signals.
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// end_of_NonZeroCoeff_CAVLC:combinational logic,active one cycle at the end of CAVLC decoding of one non zero coefficient residual.
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// end_of_NonZeroCoeff_CAVLC:combinational logic,active one cycle at the end of CAVLC decoding of one non zero coefficient residual.
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// 2. March 29,2006
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// 2. March 29,2006
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// Add signal lumaDC_IsAllZero,ChromaDC_Cb_IsAllZero,ChromaDC_Cr_IsAllZero to deal with special case:zero DC coeff,but non-zero AC coeff
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// Add signal lumaDC_IsAllZero,ChromaDC_Cb_IsAllZero,ChromaDC_Cr_IsAllZero to deal with special case:zero DC coeff,but non-zero AC coeff
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module end_of_blk_decoding (reset_n,cavlc_decoder_state,
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module end_of_blk_decoding (reset_n,cavlc_decoder_state,
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TotalCoeff,i_TotalCoeff,end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC
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TotalCoeff,i_TotalCoeff,end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC
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);
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);
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input reset_n;
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input reset_n;
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input [3:0] cavlc_decoder_state;
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input [3:0] cavlc_decoder_state;
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input [4:0] TotalCoeff;
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input [4:0] TotalCoeff;
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input [3:0] i_TotalCoeff;
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input [3:0] i_TotalCoeff;
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output end_of_one_residual_block;
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output end_of_one_residual_block;
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output end_of_NonZeroCoeff_CAVLC;
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output end_of_NonZeroCoeff_CAVLC;
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reg end_of_one_residual_block;
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reg end_of_one_residual_block;
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reg end_of_NonZeroCoeff_CAVLC;
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reg end_of_NonZeroCoeff_CAVLC;
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reg lumaDC_IsAllZero;
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reg lumaDC_IsAllZero;
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reg ChromaDC_Cb_IsAllZero;
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reg ChromaDC_Cb_IsAllZero;
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reg ChromaDC_Cr_IsAllZero;
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reg ChromaDC_Cr_IsAllZero;
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always @ (reset_n or cavlc_decoder_state or TotalCoeff or i_TotalCoeff)
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always @ (reset_n or cavlc_decoder_state or TotalCoeff or i_TotalCoeff)
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if (reset_n == 0)
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if (reset_n == 0)
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end_of_one_residual_block <= 0;
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end_of_one_residual_block <= 0;
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else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && TotalCoeff == 0)
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else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && TotalCoeff == 0)
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end_of_one_residual_block <= 1;
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end_of_one_residual_block <= 1;
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else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0)
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else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0)
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end_of_one_residual_block <= 1;
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end_of_one_residual_block <= 1;
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else
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else
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end_of_one_residual_block <= 0;
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end_of_one_residual_block <= 0;
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always @ (reset_n or cavlc_decoder_state or i_TotalCoeff)
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always @ (reset_n or cavlc_decoder_state or i_TotalCoeff)
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if (reset_n == 0)
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if (reset_n == 0)
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end_of_NonZeroCoeff_CAVLC <= 0;
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end_of_NonZeroCoeff_CAVLC <= 0;
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else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0)
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else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0)
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end_of_NonZeroCoeff_CAVLC <= 1;
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end_of_NonZeroCoeff_CAVLC <= 1;
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else
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else
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end_of_NonZeroCoeff_CAVLC <= 0;
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end_of_NonZeroCoeff_CAVLC <= 0;
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