//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : nova_tb.v
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// File : nova_tb.v
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// Generated : March 13,2006
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// Generated : March 13,2006
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Testbench for nova
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// Testbench for nova
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module nova_tb;
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module nova_tb;
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reg clk;
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reg clk;
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reg reset_n;
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reg reset_n;
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reg pin_disable_DF;
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reg pin_disable_DF;
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reg freq_ctrl0;
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reg freq_ctrl0;
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reg freq_ctrl1;
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reg freq_ctrl1;
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wire BitStream_ram_ren;
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wire BitStream_ram_ren;
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wire [16:0] BitStream_ram_addr;
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wire [16:0] BitStream_ram_addr;
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wire [15:0] BitStream_buffer_input;
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wire [15:0] BitStream_buffer_input;
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wire [5:0] pic_num;
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wire [5:0] pic_num;
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wire [6:0] mb_num;
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wire [6:0] mb_num;
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wire [13:0] ext_frame_RAM0_addr;
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wire [13:0] ext_frame_RAM0_addr;
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wire [31:0] ext_frame_RAM0_data;
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wire [31:0] ext_frame_RAM0_data;
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wire [13:0] ext_frame_RAM1_addr;
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wire [13:0] ext_frame_RAM1_addr;
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wire [31:0] ext_frame_RAM1_data;
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wire [31:0] ext_frame_RAM1_data;
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wire [31:0] dis_frame_RAM_din;
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wire [31:0] dis_frame_RAM_din;
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wire [15:0] temp;
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wire [15:0] temp;
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assign temp = dis_frame_RAM_din[15:0];
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assign temp = dis_frame_RAM_din[15:0];
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//for debug only
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//for debug only
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wire slice_header_s6;
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wire slice_header_s6;
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Beha_BitStream_ram Beha_BitStream_ram (
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Beha_BitStream_ram Beha_BitStream_ram (
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.clk(clk),
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.clk(clk),
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.BitStream_ram_ren(BitStream_ram_ren),
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.BitStream_ram_ren(BitStream_ram_ren),
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.BitStream_ram_addr(BitStream_ram_addr),
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.BitStream_ram_addr(BitStream_ram_addr),
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.BitStream_ram_data(BitStream_buffer_input)
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.BitStream_ram_data(BitStream_buffer_input)
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);
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);
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ext_frame_RAM0_wrapper ext_frame_RAM0_wrapper (
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ext_frame_RAM0_wrapper ext_frame_RAM0_wrapper (
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
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.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
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.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
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.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
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.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
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.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
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.dis_frame_RAM_din(dis_frame_RAM_din),
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.dis_frame_RAM_din(dis_frame_RAM_din),
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.ext_frame_RAM0_data(ext_frame_RAM0_data),
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.ext_frame_RAM0_data(ext_frame_RAM0_data),
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.pic_num(pic_num),
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.pic_num(pic_num),
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.slice_header_s6(slice_header_s6)
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.slice_header_s6(slice_header_s6)
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);
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);
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ext_frame_RAM1_wrapper ext_frame_RAM1_wrapper (
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ext_frame_RAM1_wrapper ext_frame_RAM1_wrapper (
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
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.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
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.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
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.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
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.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
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.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
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.dis_frame_RAM_din(dis_frame_RAM_din),
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.dis_frame_RAM_din(dis_frame_RAM_din),
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.ext_frame_RAM1_data(ext_frame_RAM1_data),
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.ext_frame_RAM1_data(ext_frame_RAM1_data),
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.pic_num(pic_num),
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.pic_num(pic_num),
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.slice_header_s6(slice_header_s6)
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.slice_header_s6(slice_header_s6)
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);
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);
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nova nova (
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nova nova (
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.clk(clk),
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.clk(clk),
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.reset_n(reset_n),
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.reset_n(reset_n),
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.freq_ctrl0(freq_ctrl0),
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.freq_ctrl0(freq_ctrl0),
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.freq_ctrl1(freq_ctrl1),
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.freq_ctrl1(freq_ctrl1),
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.BitStream_buffer_input(BitStream_buffer_input),
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.BitStream_buffer_input(BitStream_buffer_input),
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.BitStream_ram_ren(BitStream_ram_ren),
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.BitStream_ram_ren(BitStream_ram_ren),
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.BitStream_ram_addr(BitStream_ram_addr),
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.BitStream_ram_addr(BitStream_ram_addr),
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.pic_num(pic_num),
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.pic_num(pic_num),
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.pin_disable_DF(pin_disable_DF),
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.pin_disable_DF(pin_disable_DF),
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.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
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.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
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.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
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.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
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.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
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.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
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.ext_frame_RAM0_data(ext_frame_RAM0_data),
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.ext_frame_RAM0_data(ext_frame_RAM0_data),
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.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
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.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
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.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
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.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
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.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
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.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
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.ext_frame_RAM1_data(ext_frame_RAM1_data),
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.ext_frame_RAM1_data(ext_frame_RAM1_data),
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.dis_frame_RAM_din(dis_frame_RAM_din),
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.dis_frame_RAM_din(dis_frame_RAM_din),
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.slice_header_s6(slice_header_s6)
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.slice_header_s6(slice_header_s6)
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);
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);
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initial
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initial
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begin
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begin
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clk = 1'b1;
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clk = 1'b1;
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reset_n = 1'b1;
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reset_n = 1'b1;
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pin_disable_DF = 1'b0;
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pin_disable_DF = 1'b0;
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freq_ctrl0 = 1'b0;
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freq_ctrl0 = 1'b0;
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freq_ctrl1 = 1'b1;
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freq_ctrl1 = 1'b1;
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#1100 reset_n = 1'b0;
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#1100 reset_n = 1'b0;
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#1000 reset_n = 1'b1;
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#1000 reset_n = 1'b1;
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end
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end
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always
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always
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#340 clk = ~clk;
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#340 clk = ~clk;
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endmodule
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endmodule
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