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module Dyna_Tree ( clk, glob_com, dataIn, dataOut );
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module Dyna_Tree ( clk, glob_com, dataIn, dataOut );
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parameter HBIT= 3;
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parameter HBIT= 3;
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parameter TREE_LEVEL= 4;
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parameter TREE_LEVEL= 4;
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parameter IMRIGHT= 0;
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parameter IMRIGHT= 0;
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input clk;
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input clk;
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input [1:0] glob_com;
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input [1:0] glob_com;
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output TPort dataOut;
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output TPort dataOut;
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input TPort dataIn;
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input TPort dataIn;
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TPort fromLeft;
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TPort fromLeft;
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TPort fromRight;
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TPort fromRight;
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Cell_DT_Inner #( HBIT, IMRIGHT ) inner ( clk, glob_com, dataIn, fromLeft, fromRight, dataOut );
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Cell_DT_Inner #( HBIT, IMRIGHT ) inner ( clk, glob_com, dataIn, fromLeft, fromRight, dataOut );
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generate
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generate
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if ( TREE_LEVEL >0 )
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if ( TREE_LEVEL >0 )
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begin
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begin
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Dyna_Tree #( HBIT, TREE_LEVEL-1, 0 ) leftSubTree ( clk, glob_com, dataOut, fromLeft );
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Dyna_Tree #( HBIT, TREE_LEVEL-1, 0 ) leftSubTree ( clk, glob_com, dataOut, fromLeft );
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Dyna_Tree #( HBIT, TREE_LEVEL-1, 1 ) rightSubTree ( clk, glob_com, dataOut, fromRight );
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Dyna_Tree #( HBIT, TREE_LEVEL-1, 1 ) rightSubTree ( clk, glob_com, dataOut, fromRight );
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end
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end
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else
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else
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begin
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begin
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assign fromLeft.msg =VMS_STOP;
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assign fromLeft.msg =VMS_STOP;
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assign fromRight.msg=VMS_STOP;
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assign fromRight.msg=VMS_STOP;
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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typedef enum bit[3:0] { VK_EMPTY=4'h0,
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typedef enum bit[3:0] { VK_EMPTY=4'h0,
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VK_EOF,
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VK_DUMMY1,
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VK_DUMMY1,
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VK_DUMMY2,
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VK_DUMMY2,
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VK_DUMMY3,
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VK_DUMMY3,
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VK_DUMMY4,
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VK_DUMMY4,
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VK_DUMMY5,
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VK_TRANSIT,
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VK_APPLY,
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VK_APPLY,
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VK_K,
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VK_EOF,
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VK_DUMMY6,
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VK_DUMMY7,
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VK_K[2]= 4'h8,
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VK_DUMMY8,
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VK_DUMMY9
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VK_S[3]= 4'd12,
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VK_DUMMY5
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} VKind;
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} VKind;
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function logic [1:0] CH_NUM( logic [3:0] k );
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CH_NUM = k[1:0];
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endfunction
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typedef enum bit[3:0] { VMS_EMPTY=4'h0,
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typedef enum bit[3:0] { VMS_EMPTY=4'h0,
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VMS_EOF,
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VMS_READY,
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VMS_READY,
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VMS_WRITE,
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VMS_PROCESS,
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VMS_BOMB,
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VMS_READ,
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VMS_READ,
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VMS_APPLY,
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VMS_STOP // end of tree
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VMS_STOP // end of tree
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} VMeta;
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} VMeta;
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typedef enum bit[1:0]{ TO_PARENT=2'h0,
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typedef enum bit[1:0]{ TO_PARENT=2'h0,
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TO_CHILDREN,
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TO_CHILDREN,
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TO_LEFT,
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TO_LEFT,
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TO_RIGHT
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TO_RIGHT
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} VTarget;
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} VTarget;
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typedef struct{
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typedef struct{
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bit [3:0] msg;
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bit [3:0] msg;
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bit [1:0] tgt;
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bit [1:0] tgt;
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} TPort;
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} TPort;
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module Cell_DT_Inner ( clk, glob_com, i_fromParent, i_fromLeft, i_fromRight, message );
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module Cell_DT_Inner ( clk, glob_com, i_fromParent, i_fromLeft, i_fromRight, message );
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parameter HBIT= 7;
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parameter HBIT= 7;
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parameter IMRIGHT= 0;
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parameter IMRIGHT= 0;
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input clk;
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input clk;
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input [1:0] glob_com;
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input [1:0] glob_com;
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input TPort i_fromParent;
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input TPort i_fromParent;
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input TPort i_fromLeft;
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input TPort i_fromLeft;
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input TPort i_fromRight;
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input TPort i_fromRight;
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wire [HBIT:0] fromParent= ((IMRIGHT==0) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_LEFT )) ||
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wire [HBIT:0] fromParent= ((IMRIGHT==0) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_LEFT )) ||
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((IMRIGHT==1) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_RIGHT ))
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((IMRIGHT==1) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_RIGHT ))
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? i_fromParent.msg : 4'h0;
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? i_fromParent.msg : 4'h0;
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wire [HBIT:0] fromLeft= ( i_fromLeft.tgt == TO_PARENT ) ? i_fromLeft.msg : 4'h0;
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wire [HBIT:0] fromLeft= ( i_fromLeft.tgt == TO_PARENT ) ? i_fromLeft.msg : 4'h0;
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wire [HBIT:0] fromRight= ( i_fromRight.tgt == TO_PARENT ) ? i_fromRight.msg : 4'h0;
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wire [HBIT:0] fromRight= ( i_fromRight.tgt == TO_PARENT ) ? i_fromRight.msg : 4'h0;
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reg [HBIT:0] value;
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reg [HBIT:0] value;
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output TPort message;
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output TPort message;
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VMeta state;
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VMeta state;
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reg [3:0] step;
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reg [3:0] step;
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always@(posedge clk )
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always@(posedge clk )
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begin
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begin
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case( glob_com )
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case( glob_com )
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0: // working mode
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0: // working mode
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begin
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begin
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case( state )
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case( state )
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VMS_EMPTY: // sleeping
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VMS_EMPTY: // sleeping
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begin
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begin
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value <= fromParent==VK_APPLY || fromParent==VK_K ? fromParent : VK_DUMMY9; // write self
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if ( !value )
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case( fromParent )
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begin // writing left
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VK_EMPTY:; // still sleeping
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value <= fromParent;//==VK_APPLY || fromParent==VK_EMPTY || fromParent==VK_K0 ? fromParent : VK_DUMMY5; // write self
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VK_APPLY: // write subtrees
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if ( fromParent && CH_NUM( fromParent )==0 )
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state <= VMS_WRITE;
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default: // i'm a leaf
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begin
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begin
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message.msg <= VMS_READY;
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message.msg <= VMS_READY;
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message.tgt <= TO_PARENT;
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message.tgt <= TO_PARENT;
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state <= VMS_READY;
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state <= VMS_READY;
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end
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end
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endcase
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end
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end
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else if ( CH_NUM( value )!=0 && ~fromLeft[0] )
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VMS_WRITE:
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begin
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case( step )
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0: // writing left
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if ( fromLeft == VMS_EMPTY )
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begin // write left
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begin // write left
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message.msg <= fromParent;
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message.msg <= fromParent;
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message.tgt <= TO_LEFT;
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message.tgt <= TO_LEFT;
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end
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end
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else
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else if ( CH_NUM( value )==2 && ~fromRight[0] )
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begin // begin writing right
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begin // begin writing right
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message.msg <= fromParent;
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message.msg <= fromParent;
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message.tgt <= TO_RIGHT;
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message.tgt <= TO_RIGHT;
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step <= step+4'h1;
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end
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1: // writing right
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if ( fromRight == VMS_EMPTY )
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begin // write right
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message.msg <= fromParent;
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message.tgt <= TO_RIGHT;
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end
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end
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else
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else
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begin // job well done, notify parent
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begin
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message.msg <= VMS_READY;
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message.msg <= VMS_READY;
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message.tgt <= TO_PARENT;
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message.tgt <= TO_PARENT;
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state <= VMS_READY;
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state <= VMS_READY;
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step <= 0;
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end
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end
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endcase
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end
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end
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VMS_READ:
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VMS_READ:
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begin
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begin
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case( step )
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if ( message.msg == VK_EOF )
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0:
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if ( value != VK_APPLY )
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begin
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begin
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message.msg <= VK_EOF; // leaf's report
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message.msg <= VMS_READY; // end read 2
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message.tgt <= TO_PARENT;
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state <= VMS_READY;
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state <= VMS_READY;
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end
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end
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else if ( fromLeft==VMS_READY )
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// else if ( message.msg == VMS_READY && value != VK_TRANSIT )
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// begin
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// message.msg <= value; // read self
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// message.tgt <= TO_PARENT;
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// end
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else if ( CH_NUM( value )==0 )
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begin
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begin
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message.msg <= VMS_READ; // begin read left
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message.msg <= VK_EOF; // end read 1.1
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message.tgt <= TO_LEFT;
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step <= 4'h1;
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end
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end
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else
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else if ( ~step[0] && fromLeft == VMS_READY )
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message.msg <= VK_EMPTY; // wait for left
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1:
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case( fromLeft )
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VK_EMPTY:;
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VK_EOF:
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begin
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begin
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step <= 4'h2;
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message.msg <= VMS_READ; // command left
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message.msg <= VK_EMPTY;
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message.tgt <= TO_LEFT;
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end
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end
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default: // transfer left
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else if ( ~step[0] && fromLeft != VK_EOF )
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begin
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begin
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message.msg <= fromLeft;
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message.msg <= fromLeft; // transfer left
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message.tgt <= TO_PARENT;
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message.tgt <= TO_PARENT;
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end
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end
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endcase
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else if ( CH_NUM( value )==1 )
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2: // begin read right
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if ( fromRight==VMS_READY )
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begin
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begin
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message.msg <= VMS_READ;
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message.msg <= VK_EOF; // end read 1.2
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message.tgt <= TO_RIGHT;
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step <= 4'h3;
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end
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end
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else
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else if ( fromRight == VMS_READY )
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message.msg <= VK_EMPTY; // wait for right
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3:
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case( fromRight )
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VK_EMPTY:;
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VK_EOF:
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begin
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begin
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message.msg <= fromRight;
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message.msg <= VMS_READ; // command right
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state <= VMS_READY;
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message.tgt <= TO_RIGHT;
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step <= 0;
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step[0] <= 1;
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end
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end
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default: // transfer right
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else if ( fromRight != VK_EOF )
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begin
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begin
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message.msg <= fromRight;
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message.msg <= fromRight; // transfer right
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message.tgt <= TO_PARENT;
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message.tgt <= TO_PARENT;
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end
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end
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endcase
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else
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endcase
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begin
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message.msg <= VK_EOF; // end read 1.3
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step[0] <= 0;
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end
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end
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end
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VMS_READY:
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VMS_READY:
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begin
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begin
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case( fromParent )
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case( fromParent )
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VMS_BOMB: // clear
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begin
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message.msg <= VMS_BOMB;
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message.tgt <= TO_CHILDREN;
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state <= VMS_EMPTY;
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value <= VK_EMPTY;
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end
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VMS_READ: // read self
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VMS_READ: // read self
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begin
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begin
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if ( value != VK_TRANSIT )
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begin
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message.msg <= value;
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message.msg <= value;
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message.tgt <= TO_PARENT;
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message.tgt <= TO_PARENT;
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end
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state <= VMS_READ;
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state <= VMS_READ;
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end
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end
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VMS_APPLY: // apply string from parent to itself
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begin
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if ( CH_NUM( value )!=0 )
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begin
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message.msg <= VMS_APPLY;
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message.tgt <= TO_CHILDREN;
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end
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begin
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case( value )
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VK_K0,
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VK_S0,
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VK_S1:
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begin // add argument
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value[1:0] <= value[1:0] +1; // K0 -> K1, S0 -> S1, S1 -> S2
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state <= VMS_EMPTY; // WRITE
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end
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VK_K1: // K main
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begin
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value <= VK_TRANSIT;
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state <= VMS_READY;
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message.msg <= VMS_BOMB;
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message.tgt <= TO_RIGHT;
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end
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VK_S2: // S main
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begin
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state <= VMS_APPLY;
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end
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endcase
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end
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end
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default:
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default:
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begin
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begin
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message.msg <= VMS_READY;
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message.msg <= VMS_READY;
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message.tgt <= TO_PARENT;
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message.tgt <= TO_PARENT;
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end
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end
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endcase
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endcase
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end
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end
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VMS_APPLY:
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if ( fromParent != VK_EOF )
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begin
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message.msg <= fromParent; // Sxyz -> `(_`_xz) (_`_yz)
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message.tgt <= TO_CHILDREN;
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end
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else
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begin
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message.msg <= VK_EMPTY;
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state <= VMS_READY;
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value <= VK_APPLY; // Sxyz -> _`_ (`xz) (`yz)
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end
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endcase
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endcase
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end
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end
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default: // reset mode
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default: // reset mode
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begin
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begin
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state <= VMS_EMPTY;
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state <= VMS_EMPTY;
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value <= VK_EMPTY;
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message.msg <= VMS_EMPTY;
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message.msg <= VMS_EMPTY;
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step <= 0;
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step <= 0;
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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