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module VGA_Pattern ( // Read Out Side
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module VGA_Pattern ( // Read Out Side
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oRed,
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oRed,
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oGreen,
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oGreen,
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oBlue,
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oBlue,
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iVGA_X,
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iVGA_X,
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iVGA_Y,
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iVGA_Y,
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iVGA_CLK,
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iVGA_CLK,
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// Control Signals
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// Control Signals
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iRST_n,
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iRST_n,
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iColor_SW,
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iColor_SW,
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endFrame,
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endFrame,
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dbg_val );
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dbg_val );
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parameter R_SZ= 64;
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parameter R_SZ= 64;
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// Read Out Side
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// Read Out Side
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output reg [9:0] oRed;
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output reg [9:0] oRed;
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output reg [9:0] oGreen;
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output reg [9:0] oGreen;
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output reg [9:0] oBlue;
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output reg [9:0] oBlue;
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input [11:0] iVGA_X;
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input [11:0] iVGA_X;
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input [11:0] iVGA_Y;
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input [11:0] iVGA_Y;
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input iVGA_CLK;
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input iVGA_CLK;
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// Control Signals
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// Control Signals
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input iRST_n;
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input iRST_n;
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input [9:0] iColor_SW;
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input [9:0] iColor_SW;
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input endFrame;
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input endFrame;
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output wire [63:0] dbg_val;
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output wire [63:0] dbg_val;
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wire [63:0] dbg_val_i;
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wire [63:0] dbg_val_i;
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parameter ENABLE_HEAVIES= 1;
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parameter ENABLE_HEAVIES= 1;
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reg [15:0] chrono;
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reg [15:0] chrono;
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reg endFrame2;
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reg endFrame2;
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reg endFrame3;
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reg endFrame3;
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wire [3:0] x;
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wire [3:0] x;
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wire [3:0] y;
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wire [3:0] y;
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wire [7:0] rv_a_2;
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wire [7:0] rv_a_2;
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wire [7:0] gv_a_2;
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wire [7:0] gv_a_2;
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wire [7:0] bv_a_2;
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wire [7:0] bv_a_2;
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Test_Sorting_Stack #( 15, R_SZ ) high_end_2( .clk( iVGA_CLK ), .rst( ~iRST_n ),
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Test_Sorting_Stack #( 15, R_SZ ) high_end_2( .clk( iVGA_CLK ), .rst( ~iRST_n ),
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.iX_video( iVGA_X ), .iY_video( iVGA_Y ),
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.iX_video( iVGA_X ), .iY_video( iVGA_Y ),
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.oR_video( rv_a_2 ), .oG_video( gv_a_2 ), .oB_video( bv_a_2 ),
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.oR_video( rv_a_2 ), .oG_video( gv_a_2 ), .oB_video( bv_a_2 ),
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.tumblers( iColor_SW ), .endFrame(endFrame3),
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.tumblers( iColor_SW ), .endFrame(endFrame3),
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.dbg_val(_)
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.dbg_val(_)
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);
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);
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wire [7:0] mp_test_out;
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wire [7:0] mp_test_out;
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assign dbg_val= iColor_SW[7] ? dbg_val_i:chrono;
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assign dbg_val= iColor_SW[7] ? dbg_val_i:chrono;
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always@(posedge iVGA_CLK or negedge iRST_n)
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always@(posedge iVGA_CLK or negedge iRST_n)
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begin
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begin
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if(!iRST_n)
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if(!iRST_n)
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begin
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begin
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oRed <= 0;
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oRed <= 0;
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oGreen <= 0;
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oGreen <= 0;
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oBlue <= 0;
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oBlue <= 0;
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chrono <= 0;
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chrono <= 0;
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end
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end
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else
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else
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begin
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begin
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if ( endFrame2==0 && endFrame==1 )
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if ( endFrame2==0 && endFrame==1 )
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begin
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begin
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chrono<= chrono +1;
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chrono<= chrono +1;
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endFrame3<= 1;
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endFrame3<= 1;
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end
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end
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else
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else
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begin
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begin
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endFrame3<= 0;
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endFrame3<= 0;
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end
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end
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endFrame2<= endFrame;
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endFrame2<= endFrame;
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begin
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begin
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// oBlue <= iVGA_X[4] ? -1: iVGA_X;
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// oBlue <= iVGA_X[4] ? -1: iVGA_X;
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// oGreen <= iVGA_X[5] ? -1: iVGA_X;
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// oGreen <= iVGA_X[5] ? -1: iVGA_X;
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// oRed <= iVGA_X[6] ? -1: iVGA_Y;
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// oRed <= iVGA_X[6] ? -1: iVGA_Y;
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oBlue <= bv_a_2;
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oBlue <= bv_a_2;
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oGreen <= gv_a_2;
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oGreen <= gv_a_2;
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oRed <= rv_a_2;
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oRed <= rv_a_2;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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module Test_Sorting_Stack ( clk, rst,
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module Test_Sorting_Stack ( clk, rst,
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iX_video, iY_video,
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iX_video, iY_video,
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oR_video, oG_video, oB_video,
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oR_video, oG_video, oB_video,
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tumblers, endFrame, dbg_val );
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tumblers, endFrame, dbg_val );
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parameter HBIT= 15;
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parameter HBIT= 15;
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parameter R_SZ= 64;
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parameter R_SZ= 64;
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input clk;
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input clk;
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input rst;
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input rst;
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input signed [11:0] iX_video;
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input signed [11:0] iX_video;
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input signed [11:0] iY_video;
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input signed [11:0] iY_video;
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output reg [7:0] oR_video;
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output reg [7:0] oR_video;
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output reg [7:0] oG_video;
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output reg [7:0] oG_video;
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output reg [7:0] oB_video;
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output reg [7:0] oB_video;
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input [9:0] tumblers;
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input [9:0] tumblers;
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input endFrame;
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input endFrame;
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output wire [63:0] dbg_val= count;
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output wire [63:0] dbg_val= count;
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reg [HBIT*3+2:0]generator;
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reg [HBIT*3+2:0]generator;
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reg [HBIT*3+2:0]prev_generator;
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reg [HBIT*3+2:0]prev_generator;
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reg prev_btn;
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reg prev_btn;
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wire cell_rst= ( iX_video==1 && iY_video==1);
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wire cell_rst= ( iX_video==1 && iY_video==1);
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wire cell_clk= ( iX_video==1 );
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wire cell_clk= ( iX_video==1 );
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reg err_unsorted;
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reg err_unsorted;
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reg err_checksum;
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reg err_checksum;
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reg err_disagreement;
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reg err_disagreement;
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wire [HBIT:0] data_in= generator;
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wire [HBIT:0] data_in= generator;
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wire [HBIT:0] _data_out;
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wire [HBIT:0] _data_out;
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wire [HBIT:0] _d_out_3;
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wire [HBIT:0] _d_out_3;
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reg [HBIT:0] last_data;
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reg [HBIT:0] last_data;
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reg [31:0] stack_sum;
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reg [31:0] stack_sum;
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reg [15:0] stack_pos_count;
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reg [15:0] stack_pos_count;
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reg [31:0] old_sum;
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reg [31:0] old_sum;
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// tumblers[4] ? increasing order : decreasing order
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// tumblers[4] ? increasing order : decreasing order
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wire [HBIT:0] _data_in= tumblers[4] ? -1-data_in : data_in;
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wire [HBIT:0] _data_in= tumblers[4] ? -1-data_in : data_in;
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Sorting_Tree #(HBIT,R_SZ) ctree ( clk, ~cell_clk, is_input, _data_in, _d_out_3 );
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Sorting_Tree #(HBIT,R_SZ) ctree ( clk, ~cell_clk, is_input, _data_in, _d_out_3 );
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wire [HBIT:0] d_out_3 = tumblers[4] ? -1-_d_out_3 : _d_out_3;
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wire [HBIT:0] d_out_3 = tumblers[4] ? -1-_d_out_3 : _d_out_3;
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Sorting_Tree #(HBIT,R_SZ) cstack ( clk, ~cell_clk, is_input, _data_in, _data_out );
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Sorting_Stack #(HBIT,R_SZ) cstack ( clk, ~cell_clk, is_input, _data_in, _data_out );
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wire [HBIT:0] data_out= tumblers[4] ? -1-_data_out : _data_out;
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wire [HBIT:0] data_out= tumblers[4] ? -1-_data_out : _data_out;
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reg [11:0]count;
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reg [11:0]count;
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wire is_input= !cell_rst && count<R_SZ;
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wire is_input= !cell_rst && count<R_SZ;
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wire is_enable=!cell_rst && count<R_SZ*2;
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wire is_enable=!cell_rst && count<R_SZ*2;
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always@( posedge clk or posedge rst )
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always@( posedge clk or posedge rst )
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begin
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begin
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if ( rst )
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if ( rst )
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begin
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begin
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generator<= 32'h12345678;
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generator<= 32'h12345678;
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prev_generator <= 32'h12345678;
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prev_generator <= 32'h12345678;
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err_unsorted<= 0;
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err_unsorted<= 0;
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err_checksum<= 0;
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err_checksum<= 0;
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err_disagreement<= 0;
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err_disagreement<= 0;
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last_data<= -1;
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last_data<= -1;
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stack_sum<= 0;
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stack_sum<= 0;
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stack_pos_count<=0;
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stack_pos_count<=0;
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end
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end
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else
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else
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if ( cell_rst )
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if ( cell_rst )
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begin
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begin
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count<= 0;
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count<= 0;
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stack_pos_count<= 0;
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stack_pos_count<= 0;
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if ( count )
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if ( count )
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begin
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begin
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err_checksum<= ( tumblers[0] &err_checksum ) | ( stack_sum !=0 );
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err_checksum<= ( tumblers[0] &err_checksum ) | ( stack_sum !=0 );
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stack_sum<= 0;
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stack_sum<= 0;
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old_sum<= stack_sum;
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old_sum<= stack_sum;
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end
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end
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prev_btn <= tumblers[2];
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prev_btn <= tumblers[2];
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if ( tumblers[1] && !( tumblers[2] && ~prev_btn ) )
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if ( tumblers[1] && !( tumblers[2] && ~prev_btn ) )
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begin
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begin
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generator <= prev_generator;
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generator <= prev_generator;
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end
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end
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else
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else
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begin
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begin
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prev_generator <= generator;
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prev_generator <= generator;
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end
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end
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end
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end
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else
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else
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begin
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begin
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if ( cell_clk )
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if ( cell_clk )
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begin
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begin
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if ( is_input )
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if ( is_input )
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begin
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begin
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last_data <= -1;
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last_data <= -1;
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stack_sum <= stack_sum + data_in;
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stack_sum <= stack_sum + data_in;
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stack_pos_count<= stack_pos_count+ (data_in==0 ? 0:1);
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stack_pos_count<= stack_pos_count+ (data_in==0 ? 0:1);
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end
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end
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else if ( is_enable )
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else if ( is_enable )
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begin
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begin
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stack_sum <= stack_sum - data_out;
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stack_sum <= stack_sum - data_out;
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last_data<= data_out;
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last_data<= data_out;
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stack_pos_count<= stack_pos_count- (data_out==0 ? 0:1);
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stack_pos_count<= stack_pos_count- (data_out==0 ? 0:1);
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err_unsorted<= ( tumblers[0] & err_unsorted) |
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err_unsorted<= ( tumblers[0] & err_unsorted) |
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( tumblers[4] && ( last_data > data_out ))|
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( tumblers[4] && ( last_data > data_out ))|
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( ~tumblers[4] && ( last_data < data_out ));
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( ~tumblers[4] && ( last_data < data_out ));
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err_disagreement<= ( tumblers[0] & err_disagreement) | ( data_out != d_out_3 );
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err_disagreement<= ( tumblers[0] & err_disagreement) | ( data_out != d_out_3 );
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end
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end
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generator<= generator*11 + ( generator >> 16 );
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generator<= generator*11 + ( generator >> 16 );
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count<= count +1;
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count<= count +1;
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end
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end
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// oR_video<= (is_input ? data_in[HBIT:HBIT-9] : data_out[HBIT:HBIT-9]) > iX_video && !err_unsorted ? -1:0;
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// oR_video<= (is_input ? data_in[HBIT:HBIT-9] : data_out[HBIT:HBIT-9]) > iX_video && !err_unsorted ? -1:0;
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// oG_video<= stack_sum[HBIT:HBIT-9] > iX_video ? -1:0;
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// oG_video<= stack_sum[HBIT:HBIT-9] > iX_video ? -1:0;
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oR_video<= (is_input ? show_data_in : show_d_out_3 ) > iX_video ? -1:(8'h0-err_unsorted);
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oR_video<= (is_input ? show_data_in : show_d_out_3 ) > iX_video ? -1:(8'h0-err_unsorted);
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oG_video<= (is_input ? show_data_in : show_data_out) > iX_video ? -1:(8'h0-err_checksum);
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oG_video<= (is_input ? show_data_in : show_data_out) > iX_video ? -1:(8'h0-err_checksum);
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oB_video<= (is_input ? 0 : show_data_out) > iX_video ? -1:(8'h0-err_disagreement);
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oB_video<= (is_input ? 0 : show_data_out) > iX_video ? -1:(8'h0-err_disagreement);
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end
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end
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end
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end
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wire [9:0] show_data_in = tumblers[3] ? data_in [9:0] : data_in [HBIT:HBIT-9];
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wire [9:0] show_data_in = tumblers[3] ? data_in [9:0] : data_in [HBIT:HBIT-9];
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wire [9:0] show_data_out= tumblers[3] ? data_out[9:0] : data_out[HBIT:HBIT-9];
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wire [9:0] show_data_out= tumblers[3] ? data_out[9:0] : data_out[HBIT:HBIT-9];
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wire [9:0] show_d_out_3 = tumblers[3] ? d_out_3 [9:0] : d_out_3 [HBIT:HBIT-9];
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wire [9:0] show_d_out_3 = tumblers[3] ? d_out_3 [9:0] : d_out_3 [HBIT:HBIT-9];
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endmodule
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endmodule
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