nysa-sata-stack
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nysa-sata-stack
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===============
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===============
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Sata stack written in Verilog
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Sata stack written in Verilog
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Staus: TLDR Version: Simulations are working
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Staus: TLDR Version: Simulations are working
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This code was written a long time ago and I've learned much more about verilog and project organization
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This code was written a long time ago and I've learned much more about verilog and project organization
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since then. It has been proven in a Virtex 6 FPGA reading and writing to/from four Sata 2 hard drives at
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since then. It has been proven in a Virtex 6 FPGA reading and writing to/from four Sata 2 hard drives at
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the same time. There were some issues found when the internal buffers inside the hard drives began to
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fill up requiring a lot of starting and stopping of this stack. It lead to some dropped data. There was
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a horrible fix for it in the sata_link_write.v involving a small buffer. This made if very difficult to
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debug because the stack wouldn't allow me to read the non-scrambled data within the logic analyzer.
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There should be a more elegant solution to it.
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Most of the license is MIT but some of the licenses are GPL
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Most of the license is MIT but some of the licenses are GPL
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TODO: Fix Link layer... there is a small FIFO in there that is used to handle all starting and stopping
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TODO: Fix Link layer... there is a small FIFO in there that is used to handle all starting and stopping
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of the read, it's a work around and needs to be fixed
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of the read, it's a work around and needs to be fixed
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TODO: Fix Link layer so that it only instantiates one instance of the scrambler, not two
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TODO: Fix Link layer so that it only instantiates one instance of the scrambler, not two
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Code Organization:
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Code Organization:
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rtl/
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rtl/
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sata_stack.v (Top File that applications interface with)
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sata_stack.v (Top File that applications interface with)
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sata_defines.v (Set defines for the stack in here)
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sata_defines.v (Set defines for the stack in here)
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generic/ (small modules used throughout the design)
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generic/ (small modules used throughout the design)
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blk_mem.v (wraps around an infered block memory generator)
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blk_mem.v (wraps around an infered block memory generator)
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cross_clock_enable.v (simple module that allows users to
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cross_clock_enable.v (simple module that allows users to
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send enables across a clock domain)
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send enables across a clock domain)
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debounce.v (debounce)
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debounce.v (debounce)
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ppfifo.v (ping pong FIFO, similar to a ping pong buffer
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ppfifo.v (ping pong FIFO, similar to a ping pong buffer
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except the user doesn't need to track the
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except the user doesn't need to track the
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addresses)
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addresses)
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command/
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command/
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sata_command_layer.v (Sata Command Layer)
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sata_command_layer.v (Sata Command Layer)
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transport/
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transport/
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sata_transport_layer.v (Sata Transport Layer)
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sata_transport_layer.v (Sata Transport Layer)
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link/
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link/
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sata_link_layer.v (Sata Link Layer)
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sata_link_layer.v (Sata Link Layer)
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sata_link_layer_read.v (Sata link layer read side)
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sata_link_layer_read.v (Sata link layer read side)
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sata_link_layer_write.v (Sata link layer write side)
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sata_link_layer_write.v (Sata link layer write side)
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scrambler.v (scrambles/descrambles primitives)
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scrambler.v (scrambles/descrambles primitives)
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crc.v (Cyclical Redundancy Check/ creator)
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crc.v (Cyclical Redundancy Check/ creator)
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cont_controller.v (controls the scrambling of primitives)
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cont_controller.v (controls the scrambling of primitives)
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phy/
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phy/
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sata_phy_layer.v (Sata phy layer)
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sata_phy_layer.v (Sata phy layer)
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oob_controller.v (out of band controller)
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oob_controller.v (out of band controller)
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platform/
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platform/
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sata_platform.v (This is a template file you can use to interface with the gigabit transceivers)
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sata_platform.v (This is a template file you can use to interface with the gigabit transceivers)
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Soapbox:
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Soapbox:
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Although I believe this code should be distributed for free and people should redistribute their software
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Although I believe this code should be distributed for free and people should redistribute their software
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I leave the ethics up to the user and have licensesed most of the code as MIT but I did use some GPL cores
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I leave the ethics up to the user and have licensesed most of the code as MIT but I did use some GPL cores
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and if the user desires to use this in their closed source project be warned about the GPL'ed modules in
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and if the user desires to use this in their closed source project be warned about the GPL'ed modules in
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this stack.
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this stack.
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