//sata_command_layer.v
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//sata_command_layer.v
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/*
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/*
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Distributed under the MIT license.
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Distributed under the MIT license.
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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SOFTWARE.
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*/
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*/
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`include "sata_defines.v"
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`include "sata_defines.v"
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`define RESET_TIMEOUT 32'h00000002
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`define RESET_TIMEOUT 32'h00000002
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module sata_command_layer (
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module sata_command_layer (
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input rst, //reset
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input rst, //reset
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input linkup,
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input linkup,
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input clk,
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input clk,
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input data_in_clk,
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input data_in_clk,
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input data_in_clk_valid,
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input data_in_clk_valid,
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input data_out_clk,
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input data_out_clk,
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input data_out_clk_valid,
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input data_out_clk_valid,
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//User Interface
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//User Interface
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output sata_init,
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output command_layer_ready,
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output command_layer_ready,
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output reg busy,
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output reg sata_busy,
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input send_sync_escape,
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input send_sync_escape,
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input [15:0] user_features,
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input [15:0] user_features,
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//XXX: New Stb
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//XXX: New Stb
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input write_data_en,
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// input write_data_stb,
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input single_rdwr,
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// input read_data_stb,
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input read_data_en,
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output hard_drive_error,
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output dev_error,
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input send_user_command_stb,
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input execute_command_stb,
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input soft_reset_en,
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input command_layer_reset,
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output reg pio_data_ready,
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output reg pio_data_ready,
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input [7:0] command,
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input [7:0] hard_drive_command,
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input [15:0] sector_count,
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input [15:0] sector_count,
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input [47:0] sector_address,
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input [47:0] sector_address,
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input [31:0] user_din,
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input [31:0] user_din,
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input user_din_stb,
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input user_din_stb,
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output [1:0] user_din_ready,
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output [1:0] user_din_ready,
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input [1:0] user_din_activate,
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input [1:0] user_din_activate,
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output [23:0] user_din_size,
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output [23:0] user_din_size,
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output user_din_empty,
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output [31:0] user_dout,
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output [31:0] user_dout,
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output user_dout_ready,
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output user_dout_ready,
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input user_dout_activate,
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input user_dout_activate,
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input user_dout_stb,
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input user_dout_stb,
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output [23:0] user_dout_size,
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output [23:0] user_dout_size,
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//Transfer Layer Interface
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//Transfer Layer Interface
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input transport_layer_ready,
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input transport_layer_ready,
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output reg sync_escape,
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output reg sync_escape,
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output t_send_command_stb,
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output t_send_command_stb,
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output reg t_send_control_stb,
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output reg t_send_control_stb,
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output t_send_data_stb,
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output t_send_data_stb,
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input t_dma_activate_stb,
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input t_dma_activate_stb,
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input t_d2h_reg_stb,
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input t_d2h_reg_stb,
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input t_pio_setup_stb,
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input t_pio_setup_stb,
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input t_d2h_data_stb,
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input t_d2h_data_stb,
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input t_dma_setup_stb,
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input t_dma_setup_stb,
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input t_set_device_bits_stb,
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input t_set_device_bits_stb,
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input t_remote_abort,
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input t_remote_abort,
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input t_xmit_error,
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input t_xmit_error,
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input t_read_crc_error,
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input t_read_crc_error,
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//PIO
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//PIO
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input t_pio_response,
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input t_pio_response,
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input t_pio_direction,
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input t_pio_direction,
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input [15:0] t_pio_transfer_count,
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input [15:0] t_pio_transfer_count,
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input [7:0] t_pio_e_status,
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input [7:0] t_pio_e_status,
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//Host to Device Register Values
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//Host to Device Register Values
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output [7:0] h2d_command,
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output [7:0] h2d_command,
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output reg [15:0] h2d_features,
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output reg [15:0] h2d_features,
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output [7:0] h2d_control,
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output [7:0] h2d_control,
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output [3:0] h2d_port_mult,
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output [3:0] h2d_port_mult,
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output [7:0] h2d_device,
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output [7:0] h2d_device,
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output [47:0] h2d_lba,
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output [47:0] h2d_lba,
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output [15:0] h2d_sector_count,
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output [15:0] h2d_sector_count,
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//Device to Host Register Values
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//Device to Host Register Values
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input d2h_interrupt,
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input d2h_interrupt,
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input d2h_notification,
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input d2h_notification,
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input [3:0] d2h_port_mult,
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input [3:0] d2h_port_mult,
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input [7:0] d2h_device,
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input [7:0] d2h_device,
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input [47:0] d2h_lba,
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input [47:0] d2h_lba,
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input [15:0] d2h_sector_count,
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input [15:0] d2h_sector_count,
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input [7:0] d2h_status,
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input [7:0] d2h_status,
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input [7:0] d2h_error,
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input [7:0] d2h_error,
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output d2h_error_bbk, //Bad Block
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output d2h_error_unc, //Uncorrectable Error
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output d2h_error_mc, //Removable Media Error
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output d2h_error_idnf, //request sector's ID Field could not be found
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output d2h_error_mcr, //Removable Media Error
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output d2h_error_abrt, //Abort (from invalid command, drive not ready, write fault)
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output d2h_error_tk0nf, //Track 0 not found
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output d2h_error_amnf, //Data Address Mark is not found after finding correct ID
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output d2h_status_bsy, //Set to 1 when drive has access to command block, no other bits are valid when 1
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// Set after reset
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// Set after soft reset (srst)
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// Set immediately after host writes to command register
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output d2h_status_drdy, //Drive is ready to accept command
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output d2h_status_dwf, //Drive Write Fault
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output d2h_status_dsc, //Drive Seek Complete
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output d2h_status_drq, //Data Request, Drive is ready to send data to the host
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output d2h_status_corr, //Correctable Data bit (an error that was encountered but was corrected)
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output d2h_status_idx, //once per disc revolution this bit is set to one then back to zero
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output d2h_status_err, //error bit, if this bit is high check the error flags
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//command layer data interface
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//command layer data interface
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input t_if_strobe,
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input t_if_strobe,
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output [31:0] t_if_data,
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output [31:0] t_if_data,
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output t_if_ready,
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output t_if_ready,
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input t_if_activate,
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input t_if_activate,
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output [23:0] t_if_size,
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output [23:0] t_if_size,
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input t_of_strobe,
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input t_of_strobe,
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input [31:0] t_of_data,
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input [31:0] t_of_data,
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output [1:0] t_of_ready,
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output [1:0] t_of_ready,
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input [1:0] t_of_activate,
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input [1:0] t_of_activate,
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output [23:0] t_of_size,
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output [23:0] t_of_size,
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//Debug
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//Debug
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output [3:0] cl_c_state,
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output [3:0] cl_c_state,
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output [3:0] cl_w_state,
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output [3:0] cl_w_state
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output [3:0] cl_r_state
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);
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);
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//Parameters
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//Parameters
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parameter IDLE = 4'h0;
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parameter IDLE = 4'h0;
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parameter PIO_WAIT_FOR_DATA = 4'h1;
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parameter PIO_WAIT_FOR_DATA = 4'h1;
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parameter PIO_WRITE_DATA = 4'h2;
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parameter PIO_WRITE_DATA = 4'h2;
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parameter WAIT_FOR_DATA = 4'h1;
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parameter WAIT_FOR_DMA_ACT = 4'h1;
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parameter WAIT_FOR_DMA_ACT = 4'h1;
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parameter WAIT_FOR_WRITE_DATA = 4'h2;
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parameter WAIT_FOR_WRITE_DATA = 4'h2;
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parameter SEND_DATA = 4'h3;
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parameter SEND_DATA = 4'h3;
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parameter WAIT_FOR_STATUS = 4'h4;
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//Registers/Wires
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//Registers/Wires
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reg [3:0] cntrl_state;
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reg [3:0] cntrl_state;
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reg srst;
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reg srst;
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reg [7:0] status;
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reg [7:0] status;
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wire idle;
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wire idle;
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reg cntrl_send_data_stb;
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reg cntrl_send_data_stb;
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reg send_command_stb;
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reg send_command_stb;
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reg prev_send_command;
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wire dev_busy;
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wire dev_busy;
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wire dev_data_req;
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wire dev_data_req;
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reg [31:0] reset_count;
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wire reset_timeout;
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//Read State Machine
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reg [3:0] read_state;
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reg read_data_stb;
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reg single_read_prev;
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//Write State Machine
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//Write State Machine
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reg [3:0] write_state;
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reg [3:0] write_state;
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reg write_data_stb;
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reg single_write_prev;
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reg dma_send_data_stb;
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reg dma_send_data_stb;
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reg dma_act_detected;
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reg dma_act_detected_en;
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wire write_data_available;
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reg first_write;
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reg first_read;
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reg enable_tl_data_ready;
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reg enable_tl_data_ready;
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//Ping Pong FIFOs
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//Ping Pong FIFOs
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wire [1:0] if_write_ready;
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wire [1:0] if_write_ready;
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wire [1:0] if_write_activate;
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wire [1:0] if_write_activate;
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wire [23:0] if_write_size;
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wire [23:0] if_write_size;
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wire if_write_strobe;
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wire if_write_strobe;
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wire if_starved;
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wire [31:0] if_write_data;
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wire [31:0] if_write_data;
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wire if_read_strobe;
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wire if_read_strobe;
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wire if_read_ready;
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wire if_read_ready;
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wire if_read_activate;
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wire if_read_activate;
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wire [23:0] if_read_size;
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wire [23:0] if_read_size;
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wire [31:0] if_read_data;
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wire [31:0] if_read_data;
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wire if_reset;
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wire if_reset;
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wire [31:0] of_write_data;
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wire [31:0] of_write_data;
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wire [1:0] of_write_ready;
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wire [1:0] of_write_ready;
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wire [1:0] of_write_activate;
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wire [1:0] of_write_activate;
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wire [23:0] of_read_size;
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wire [23:0] of_read_size;
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wire of_write_strobe;
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wire of_write_strobe;
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wire out_fifo_starved;
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wire out_fifo_starved;
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wire of_read_ready;
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wire of_read_ready;
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wire [31:0] of_read_data;
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wire [31:0] of_read_data;
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wire of_read_activate;
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wire of_read_activate;
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wire [23:0] of_write_size;
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wire [23:0] of_write_size;
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wire of_read_strobe;
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wire of_read_strobe;
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wire of_reset;
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wire of_reset;
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//ping pong FIFO
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//ping pong FIFO
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//Input FIFO
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//Input FIFO
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ppfifo # (
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ppfifo # (
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.DATA_WIDTH (`DATA_SIZE ),
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.DATA_WIDTH (`DATA_SIZE ),
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.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
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.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
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) fifo_in (
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) fifo_in (
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.reset (if_reset ), //XXX: Veify that new PPFIFO doesn't need an external reset
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.reset (if_reset ), //XXX: Veify that new PPFIFO doesn't need an external reset
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//write side
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//write side
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//XXX: This can be different clocks
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//XXX: This can be different clocks
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.write_clock (data_in_clk ),
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.write_clock (data_in_clk ),
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.write_data (if_write_data ),
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.write_data (if_write_data ),
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.write_ready (if_write_ready ),
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.write_ready (if_write_ready ),
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.write_activate (if_write_activate ),
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.write_activate (if_write_activate ),
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.write_fifo_size (if_write_size ),
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.write_fifo_size (if_write_size ),
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.write_strobe (if_write_strobe ),
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.write_strobe (if_write_strobe ),
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.starved (if_starved ),
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//.starved (if_starved ),
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.starved (user_din_empty ),
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//read side
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//read side
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//XXX: This can be different clocks
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//XXX: This can be different clocks
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.read_clock (clk ),
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.read_clock (clk ),
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.read_strobe (if_read_strobe ),
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.read_strobe (if_read_strobe ),
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.read_ready (if_read_ready ),
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.read_ready (if_read_ready ),
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.read_activate (if_read_activate ),
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.read_activate (if_read_activate ),
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.read_count (if_read_size ),
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.read_count (if_read_size ),
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.read_data (if_read_data )
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.read_data (if_read_data ),
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.inactive ( )
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);
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);
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//Output FIFO
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//Output FIFO
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ppfifo # (
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ppfifo # (
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.DATA_WIDTH (`DATA_SIZE ),
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.DATA_WIDTH (`DATA_SIZE ),
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.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
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.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
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) fifo_out (
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) fifo_out (
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.reset (of_reset ),
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.reset (of_reset ),
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//.reset (0),
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//.reset (0),
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//write side
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//write side
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//XXX: This can be different clocks
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//XXX: This can be different clocks
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.write_clock (clk ),
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.write_clock (clk ),
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.write_data (of_write_data ),
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.write_data (of_write_data ),
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.write_ready (of_write_ready ),
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.write_ready (of_write_ready ),
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.write_activate (of_write_activate ),
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.write_activate (of_write_activate ),
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.write_fifo_size (of_write_size ),
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.write_fifo_size (of_write_size ),
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.write_strobe (of_write_strobe ),
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.write_strobe (of_write_strobe ),
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.starved (out_fifo_starved ),
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//.starved (out_fifo_starved ),
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.starved ( ),
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//read side
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//read side
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//XXX: This can be different clocks
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//XXX: This can be different clocks
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.read_clock (data_out_clk ),
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.read_clock (data_out_clk ),
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.read_strobe (of_read_strobe ),
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.read_strobe (of_read_strobe ),
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.read_ready (of_read_ready ),
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.read_ready (of_read_ready ),
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.read_activate (of_read_activate ),
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.read_activate (of_read_activate ),
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.read_count (of_read_size ),
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.read_count (of_read_size ),
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.read_data (of_read_data )
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.read_data (of_read_data ),
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.inactive ( )
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);
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);
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//Asynchronous Logic
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//Asynchronous Logic
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//Attach output of Input FIFO to TL
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//Attach output of Input FIFO to TL
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assign t_if_ready = if_read_ready && enable_tl_data_ready;
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assign t_if_ready = if_read_ready && enable_tl_data_ready;
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assign t_if_size = if_read_size;
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assign t_if_size = if_read_size;
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assign t_if_data = if_read_data;
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assign t_if_data = if_read_data;
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assign if_read_activate = t_if_activate;
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assign if_read_activate = t_if_activate;
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assign if_read_strobe = t_if_strobe;
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assign if_read_strobe = t_if_strobe;
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//Attach input of output FIFO to TL
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//Attach input of output FIFO to TL
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assign t_of_ready = of_write_ready;
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assign t_of_ready = of_write_ready;
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//assign t_of_size = of_write_size;
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//assign t_of_size = of_write_size;
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assign t_of_size = 24'h00800;
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assign t_of_size = 24'h00800;
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assign of_write_data = t_of_data;
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assign of_write_data = t_of_data;
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assign of_write_activate = t_of_activate;
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assign of_write_activate = t_of_activate;
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assign of_write_strobe = t_of_strobe;
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assign of_write_strobe = t_of_strobe;
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assign of_reset = (rst && data_out_clk_valid);
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assign of_reset = (rst && data_out_clk_valid);
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assign if_reset = (rst && data_in_clk_valid);
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assign if_reset = (rst && data_in_clk_valid);
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assign if_write_data = user_din;
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assign if_write_data = user_din;
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assign if_write_strobe = user_din_stb;
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assign if_write_strobe = user_din_stb;
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assign user_din_ready = if_write_ready;
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assign user_din_ready = if_write_ready;
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assign if_write_activate = user_din_activate;
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assign if_write_activate = user_din_activate;
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//assign user_din_size = if_write_size;
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assign user_din_size = if_write_size;
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assign user_din_size = 24'h00800;
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//assign user_din_size = 24'h00400;
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//assign user_din_size = 24'h00200;
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assign user_dout = of_read_data;
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assign user_dout = of_read_data;
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assign user_dout_ready = of_read_ready;
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assign user_dout_ready = of_read_ready;
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assign of_read_activate = user_dout_activate;
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assign of_read_activate = user_dout_activate;
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assign user_dout_size = of_read_size;
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assign user_dout_size = of_read_size;
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assign of_read_strobe = user_dout_stb;
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assign of_read_strobe = user_dout_stb;
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assign d2h_status_bsy = d2h_status[7];
|
assign write_data_available = (if_read_ready || if_read_activate) || (if_write_ready != 2'b11);
|
assign d2h_status_drdy = d2h_status[6];
|
|
assign d2h_status_dwf = d2h_status[5];
|
|
assign d2h_status_dsc = d2h_status[4];
|
|
assign d2h_status_drq = d2h_status[3];
|
|
assign d2h_status_corr = d2h_status[2];
|
|
assign d2h_status_idx = d2h_status[1];
|
|
assign d2h_status_err = d2h_status[0];
|
|
|
|
assign d2h_error_bbk = d2h_error[7];
|
|
assign d2h_error_unc = d2h_error[6];
|
|
assign d2h_error_mc = d2h_error[5];
|
|
assign d2h_error_idnf = d2h_error[4];
|
|
assign d2h_error_mcr = d2h_error[3];
|
|
assign d2h_error_abrt = d2h_error[2];
|
|
assign d2h_error_tk0nf = d2h_error[1];
|
|
assign d2h_error_amnf = d2h_error[0];
|
|
|
//Strobes
|
//Strobes
|
assign t_send_command_stb = read_data_stb || write_data_stb || send_command_stb;
|
//assign t_send_command_stb = read_data_stb || write_data_stb || execute_command_stb;
|
|
assign t_send_command_stb = execute_command_stb;
|
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
|
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
|
|
|
//IDLE
|
//IDLE
|
assign idle = (cntrl_state == IDLE) &&
|
assign idle = (cntrl_state == IDLE) &&
|
(read_state == IDLE) &&
|
|
(write_state == IDLE) &&
|
(write_state == IDLE) &&
|
transport_layer_ready;
|
transport_layer_ready;
|
|
|
assign command_layer_ready = idle;
|
assign command_layer_ready = idle;
|
assign sata_init = reset_timeout;
|
|
|
|
assign h2d_command = (write_data_en) ? `COMMAND_DMA_WRITE_EX :
|
|
(read_data_en) ? `COMMAND_DMA_READ_EX :
|
|
(send_user_command_stb) ? command :
|
|
h2d_command;
|
|
|
|
|
assign h2d_command = hard_drive_command;
|
assign h2d_sector_count = sector_count;
|
assign h2d_sector_count = sector_count;
|
assign h2d_lba = (write_data_en) ? (!single_rdwr && !first_write) ? d2h_lba + 1 : sector_address :
|
assign h2d_lba = sector_address;
|
(read_data_en) ? (!single_rdwr && !first_read) ? d2h_lba + 1 : sector_address :
|
|
sector_address;
|
|
|
|
//XXX: The individual bits should be controlled directly
|
//XXX: The individual bits should be controlled directly
|
assign h2d_control = {5'h00, srst, 2'b00};
|
assign h2d_control = {5'h00, srst, 2'b00};
|
//XXX: This should be controlled from a higher level
|
//XXX: This should be controlled from a higher level
|
assign h2d_port_mult = 4'h0;
|
assign h2d_port_mult = 4'h0;
|
//XXX: This should be controlled from a higher level
|
//XXX: This should be controlled from a higher level
|
assign h2d_device = `D2H_REG_DEVICE;
|
assign h2d_device = `D2H_REG_DEVICE;
|
|
|
assign dev_busy = status[`STATUS_BUSY_BIT];
|
assign dev_busy = status[`STATUS_BUSY_BIT];
|
assign dev_data_req = status[`STATUS_DRQ_BIT];
|
assign dev_data_req = status[`STATUS_DRQ_BIT];
|
assign dev_error = status[`STATUS_ERR_BIT];
|
assign hard_drive_error = status[`STATUS_ERR_BIT];
|
|
|
assign cl_c_state = cntrl_state;
|
assign cl_c_state = cntrl_state;
|
assign cl_r_state = read_state;
|
|
assign cl_w_state = write_state;
|
assign cl_w_state = write_state;
|
|
|
assign reset_timeout = (reset_count >= `RESET_TIMEOUT);
|
|
|
|
//Synchronous Logic
|
//Synchronous Logic
|
|
|
//Control State Machine
|
//Control State Machine
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if (rst || (!linkup)) begin
|
if (rst || (!linkup)) begin
|
cntrl_state <= IDLE;
|
cntrl_state <= IDLE;
|
|
|
h2d_features <= `D2H_REG_FEATURES;
|
h2d_features <= `D2H_REG_FEATURES;
|
srst <= 0;
|
srst <= 0;
|
|
|
//Strobes
|
//Strobes
|
t_send_control_stb <= 0;
|
t_send_control_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
pio_data_ready <= 0;
|
pio_data_ready <= 0;
|
status <= 0;
|
status <= 0;
|
|
|
prev_send_command <= 0;
|
sata_busy <= 0;
|
send_command_stb <= 0;
|
sync_escape <= 0;
|
|
|
reset_count <= 0;
|
|
busy <= 1;
|
|
end
|
end
|
else begin
|
else begin
|
t_send_control_stb <= 0;
|
t_send_control_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
pio_data_ready <= 0;
|
pio_data_ready <= 0;
|
send_command_stb <= 0;
|
|
|
|
//Reset Count
|
//Reset Count
|
if (reset_count < `RESET_TIMEOUT) begin
|
|
reset_count <= reset_count + 1;
|
|
end
|
|
if (!reset_timeout) begin
|
|
cntrl_state <= IDLE;
|
|
end
|
|
|
|
//detected the first a user attempting to send a command
|
|
if (send_user_command_stb && !prev_send_command) begin
|
|
prev_send_command <= 1;
|
|
send_command_stb <= 1;
|
|
end
|
|
if (!send_user_command_stb) begin
|
|
prev_send_command <= 0;
|
|
end
|
|
|
|
if (t_d2h_reg_stb) begin
|
if (t_d2h_reg_stb) begin
|
busy <= 0;
|
//Receiving a register strobe from the device
|
|
sata_busy <= 0;
|
h2d_features <= `D2H_REG_FEATURES;
|
h2d_features <= `D2H_REG_FEATURES;
|
end
|
end
|
if (t_send_command_stb || t_send_control_stb || send_user_command_stb) begin
|
/*
|
busy <= 1;
|
if (t_send_command_stb || t_send_control_stb) begin
|
if (send_user_command_stb) begin
|
sata_busy <= 1;
|
|
end
|
|
*/
|
|
if (execute_command_stb) begin
|
h2d_features <= user_features;
|
h2d_features <= user_features;
|
end
|
sata_busy <= 1;
|
end
|
end
|
|
|
case (cntrl_state)
|
case (cntrl_state)
|
IDLE: begin
|
IDLE: begin
|
|
|
//Soft Reset will break out of any flow
|
//Soft Reset will break out of any flow
|
if ((soft_reset_en) && !srst) begin
|
if (command_layer_reset && !srst) begin
|
srst <= 1;
|
srst <= 1;
|
t_send_control_stb <= 1;
|
t_send_control_stb <= 1;
|
reset_count <= 0;
|
|
end
|
end
|
|
|
if (idle) begin
|
if (idle) begin
|
//The only way to transition to another state is if CL is IDLE
|
//The only way to transition to another state is if CL is IDLE
|
|
|
//User Initiated commands
|
//User Initiated commands
|
if (!soft_reset_en && srst && reset_timeout) begin
|
if (!command_layer_reset && srst) begin
|
srst <= 0;
|
srst <= 0;
|
t_send_control_stb <= 1;
|
t_send_control_stb <= 1;
|
end
|
end
|
end
|
end
|
|
|
//Device Initiated Transfers
|
//Device Initiated Transfers
|
if(t_pio_setup_stb) begin
|
if(t_pio_setup_stb) begin
|
if (t_pio_direction) begin
|
if (t_pio_direction) begin
|
//Read from device
|
//Read from device
|
cntrl_state <= PIO_WAIT_FOR_DATA;
|
cntrl_state <= PIO_WAIT_FOR_DATA;
|
end
|
end
|
else begin
|
else begin
|
//Write to device
|
//Write to device
|
cntrl_state <= PIO_WRITE_DATA;
|
cntrl_state <= PIO_WRITE_DATA;
|
end
|
end
|
end
|
end
|
if (t_set_device_bits_stb) begin
|
if (t_set_device_bits_stb) begin
|
status <= d2h_status;
|
status <= d2h_status;
|
//status register was updated
|
//status register was updated
|
end
|
end
|
if (t_d2h_reg_stb) begin
|
if (t_d2h_reg_stb) begin
|
status <= d2h_status;
|
status <= d2h_status;
|
end
|
end
|
end
|
end
|
PIO_WAIT_FOR_DATA: begin
|
PIO_WAIT_FOR_DATA: begin
|
if (t_d2h_data_stb) begin
|
if (t_d2h_data_stb) begin
|
//the next peice of data is related to the PIO
|
//the next peice of data is related to the PIO
|
pio_data_ready <= 1;
|
pio_data_ready <= 1;
|
cntrl_state <= IDLE;
|
cntrl_state <= IDLE;
|
status <= t_pio_e_status;
|
status <= t_pio_e_status;
|
end
|
end
|
end
|
end
|
PIO_WRITE_DATA: begin
|
PIO_WRITE_DATA: begin
|
if (if_read_activate) begin
|
if (if_read_activate) begin
|
cntrl_send_data_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
cntrl_state <= IDLE;
|
cntrl_state <= IDLE;
|
status <= t_pio_e_status;
|
status <= t_pio_e_status;
|
end
|
end
|
end
|
end
|
|
|
default: begin
|
default: begin
|
cntrl_state <= IDLE;
|
cntrl_state <= IDLE;
|
end
|
end
|
endcase
|
endcase
|
|
|
if (send_sync_escape) begin
|
if (send_sync_escape) begin
|
cntrl_state <= IDLE;
|
cntrl_state <= IDLE;
|
busy <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
//Read State Machine
|
|
always @ (posedge clk) begin
|
|
if (rst || (!linkup)) begin
|
|
read_state <= IDLE;
|
|
sync_escape <= 0;
|
|
read_data_stb <= 0;
|
|
single_read_prev <= 0;
|
|
first_read <= 1;
|
|
end
|
|
else begin
|
|
read_data_stb <= 0;
|
|
sync_escape <= 0;
|
|
|
|
if (!read_data_en) begin
|
|
single_read_prev <= 0;
|
|
end
|
|
|
|
case (read_state)
|
|
IDLE: begin
|
|
if (idle) begin
|
|
sync_escape <= 0;
|
|
//The only way to transition to another state is if CL is IDLE
|
|
if (read_data_en) begin
|
|
if (single_rdwr) begin
|
|
if (!single_read_prev) begin
|
|
single_read_prev <= 1;
|
|
read_data_stb <= 1;
|
|
read_state <= WAIT_FOR_DATA;
|
|
end
|
|
end
|
|
else begin
|
|
//send a request to read data
|
|
read_data_stb <= 1;
|
|
read_state <= WAIT_FOR_DATA;
|
|
end
|
|
end
|
|
else begin
|
|
first_read <= 1;
|
|
end
|
|
end
|
|
end
|
|
WAIT_FOR_DATA: begin
|
|
//This state seems useless because it only sets a value but the state is used to indicate the system is idle or not
|
|
if (t_d2h_data_stb) begin
|
|
first_read <= 0;
|
|
end
|
|
/*
|
|
if (soft_reset_en) begin
|
|
//XXX: Issue a SYNC ESCAPE to cancel a large read request otherwise let it play out
|
|
//sync_escape <= 1;
|
|
end
|
|
*/
|
|
end
|
|
default: begin
|
|
read_state <= IDLE;
|
|
end
|
|
endcase
|
|
|
|
if (soft_reset_en || !reset_timeout || send_sync_escape) begin
|
|
if (read_state != IDLE) begin
|
|
sync_escape <= 1;
|
sync_escape <= 1;
|
end
|
sata_busy <= 0;
|
if (send_sync_escape) begin
|
|
sync_escape <= 1;
|
|
end
|
|
read_state <= IDLE;
|
|
end
|
|
|
|
//If this is received go back to IDLE
|
|
if (t_d2h_reg_stb) begin
|
|
read_state <= IDLE;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//Write State Machine
|
//Write State Machine
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if (rst || (!linkup)) begin
|
if (rst || !linkup) begin
|
write_state <= IDLE;
|
write_state <= IDLE;
|
|
|
dma_send_data_stb <= 0;
|
dma_send_data_stb <= 0;
|
|
|
write_data_stb <= 0;
|
|
single_write_prev <= 0;
|
|
first_write <= 1;
|
|
enable_tl_data_ready <= 0;
|
enable_tl_data_ready <= 0;
|
|
dma_act_detected_en <= 0;
|
dma_act_detected <= 0;
|
|
end
|
end
|
else begin
|
else begin
|
dma_send_data_stb <= 0;
|
dma_send_data_stb <= 0;
|
write_data_stb <= 0;
|
|
|
|
if (enable_tl_data_ready && if_read_activate) begin
|
|
//Closes the loop on the data write feedback
|
|
enable_tl_data_ready <= 0;
|
|
end
|
|
|
|
if (!write_data_en) begin
|
|
single_write_prev <= 0;
|
|
end
|
|
|
|
if (t_dma_activate_stb) begin
|
if (t_dma_activate_stb) begin
|
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
|
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
|
dma_act_detected <= 1;
|
dma_act_detected_en <= 1;
|
end
|
end
|
|
|
case (write_state)
|
case (write_state)
|
IDLE: begin
|
IDLE: begin
|
|
enable_tl_data_ready <= 0;
|
if (idle) begin
|
if (idle) begin
|
//The only way to transition to another state is if CL is IDLE
|
//The only way to transition to another state is if CL is IDLE
|
if (write_data_en) begin
|
//if (write_data_stb) begin
|
if (single_rdwr) begin
|
if (dma_act_detected_en) begin
|
if (!single_write_prev) begin
|
|
single_write_prev <= 1;
|
|
write_state <= WAIT_FOR_DMA_ACT;
|
|
write_data_stb <= 1;
|
|
end
|
|
end
|
|
else begin
|
|
//send a request to write data
|
//send a request to write data
|
write_state <= WAIT_FOR_DMA_ACT;
|
write_state <= WAIT_FOR_DMA_ACT;
|
write_data_stb <= 1;
|
|
end
|
|
end
|
|
else begin
|
|
//reset the the first write when the user deassertes the write_data_en
|
|
first_write <= 1;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
WAIT_FOR_DMA_ACT: begin
|
WAIT_FOR_DMA_ACT: begin
|
if (dma_act_detected) begin
|
if (dma_act_detected_en) begin
|
dma_act_detected <= 0;
|
dma_act_detected_en <= 0;
|
first_write <= 0;
|
|
enable_tl_data_ready <= 1;
|
enable_tl_data_ready <= 1;
|
write_state <= WAIT_FOR_WRITE_DATA;
|
write_state <= WAIT_FOR_WRITE_DATA;
|
end
|
end
|
end
|
end
|
WAIT_FOR_WRITE_DATA: begin
|
WAIT_FOR_WRITE_DATA: begin
|
if (if_read_activate) begin
|
if (if_read_activate) begin
|
|
enable_tl_data_ready <= 0;
|
write_state <= SEND_DATA;
|
write_state <= SEND_DATA;
|
end
|
end
|
end
|
end
|
SEND_DATA: begin
|
SEND_DATA: begin
|
if (transport_layer_ready) begin
|
if (transport_layer_ready) begin
|
//Send the Data FIS
|
//Send the Data FIS
|
dma_send_data_stb <= 1;
|
dma_send_data_stb <= 1;
|
write_state <= WAIT_FOR_DMA_ACT;
|
dma_act_detected_en <= 0;
|
end
|
|
end
|
|
WAIT_FOR_STATUS: begin
|
|
if (t_d2h_reg_stb) begin
|
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
end
|
end
|
default: begin
|
default: begin
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
endcase
|
endcase
|
|
|
|
|
if (soft_reset_en || !reset_timeout) begin
|
//if (command_layer_reset || !reset_timeout) begin
|
|
if (command_layer_reset) begin
|
//Break out of the normal flow and return to IDLE
|
//Break out of the normal flow and return to IDLE
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
if (t_d2h_reg_stb) begin
|
if (t_d2h_reg_stb) begin
|
//Whenever I read a register transfer from the device I need to go back to IDLE
|
//Whenever I read a register transfer from the device I need to go back to IDLE
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
if (send_sync_escape) begin
|
if (send_sync_escape) begin
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
