//cont_controller.v
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//cont_controller.v
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/*
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/*
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Distributed under the MIT license.
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Distributed under the MIT license.
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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SOFTWARE.
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*/
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*/
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`include "sata_defines.v"
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`include "sata_defines.v"
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module cont_controller (
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module cont_controller (
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input rst, //reset
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input rst, //reset
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input clk,
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input clk,
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input phy_ready,
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input phy_ready,
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input xmit_cont_en, //enable the transmit cont primative (slows simulations WAY!!! down)
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input xmit_cont_en, //enable the transmit cont primative (slows simulations WAY!!! down)
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input last_prim,
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input last_prim,
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input [31:0] ll_tx_din,
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input [31:0] ll_tx_din,
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input ll_tx_isk,
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input ll_tx_is_k,
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output [31:0] cont_tx_dout,
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output [31:0] cont_tx_dout,
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output cont_tx_isk,
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output cont_tx_is_k,
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input [31:0] rx_din,
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input [31:0] rx_din,
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input [3:0] rx_isk,
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input [3:0] rx_is_k,
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output detect_sync,
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output detect_sync,
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output detect_r_rdy,
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output detect_r_rdy,
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output detect_r_ip,
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output detect_r_ip,
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output detect_r_err,
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output detect_r_err,
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output detect_r_ok,
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output detect_r_ok,
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output detect_x_rdy,
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output detect_x_rdy,
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output detect_sof,
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output detect_sof,
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output detect_eof,
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output detect_eof,
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output detect_wtrm,
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output detect_wtrm,
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output detect_cont,
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output detect_cont,
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output detect_hold,
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output detect_hold,
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output detect_holda,
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output detect_holda,
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output detect_preq_s,
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output detect_preq_s,
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output detect_preq_p,
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output detect_preq_p,
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output detect_align,
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output detect_align,
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output detect_xrdy_xrdy
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output detect_xrdy_xrdy
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);
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);
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//Parameters
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//Parameters
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//Registers/Wires
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//Registers/Wires
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//CONT detect State Machine
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//CONT detect State Machine
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wire hold_cont;
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wire hold_cont;
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wire holda_cont;
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wire holda_cont;
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wire pmreq_p_cont;
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wire pmreq_p_cont;
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wire pmreq_s_cont;
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wire pmreq_s_cont;
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wire r_err_cont;
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wire r_err_cont;
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wire r_ip_cont;
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wire r_ip_cont;
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wire r_ok_cont;
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wire r_ok_cont;
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wire r_rdy_cont;
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wire r_rdy_cont;
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wire sync_cont;
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wire sync_cont;
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wire wtrm_cont;
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wire wtrm_cont;
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wire x_rdy_cont;
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wire x_rdy_cont;
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reg cont_detect;
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reg cont_detect;
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reg [31:0] prev_prim;
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reg [31:0] prev_prim;
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reg hold_cont_ready;
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reg hold_cont_ready;
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reg holda_cont_ready;
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reg holda_cont_ready;
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reg pmreq_p_cont_ready;
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reg pmreq_p_cont_ready;
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reg pmreq_s_cont_ready;
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reg pmreq_s_cont_ready;
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reg r_err_cont_ready;
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reg r_err_cont_ready;
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reg r_ip_cont_ready;
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reg r_ip_cont_ready;
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reg r_ok_cont_ready;
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reg r_ok_cont_ready;
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reg r_rdy_cont_ready;
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reg r_rdy_cont_ready;
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reg sync_cont_ready;
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reg sync_cont_ready;
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reg wtrm_cont_ready;
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reg wtrm_cont_ready;
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reg x_rdy_cont_ready;
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reg x_rdy_cont_ready;
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//CONT generate state machine
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//CONT generate state machine
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reg [31:0] tx_prev_prim;
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reg [31:0] tx_prev_prim;
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reg tx_cont_enable;
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reg tx_cont_enable;
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reg tx_cont_sent;
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reg tx_cont_sent;
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reg send_cont;
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reg send_cont;
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//Scrambler control
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//Scrambler control
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wire scram_en;
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wire scram_en;
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wire [31:0] scram_dout;
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wire [31:0] scram_dout;
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//Submodules
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//Submodules
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scrambler scram (
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scrambler scram (
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.rst (rst ),
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.rst (rst ),
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.clk (clk ),
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.clk (clk ),
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.prim_scrambler (1'b1 ),
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.prim_scrambler (1'b1 ),
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.en (scram_en ),
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.en (scram_en ),
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.din (ll_tx_din ),
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.din (ll_tx_din ),
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.dout (scram_dout )
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.dout (scram_dout )
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);
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);
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//Asynchronous Logic
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//Asynchronous Logic
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assign detect_sync = ((rx_isk[0]) && (rx_din == `PRIM_SYNC )) || sync_cont; //sync (normal) == sync(cont)
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assign detect_sync = ((rx_is_k[0]) && (rx_din == `PRIM_SYNC )) || sync_cont; //sync (normal) == sync(cont)
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assign detect_r_rdy = ((rx_isk[0]) && (rx_din == `PRIM_R_RDY )) || r_rdy_cont;
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assign detect_r_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_R_RDY )) || r_rdy_cont;
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assign detect_r_ip = ((rx_isk[0]) && (rx_din == `PRIM_R_IP )) || r_ip_cont;
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assign detect_r_ip = ((rx_is_k[0]) && (rx_din == `PRIM_R_IP )) || r_ip_cont;
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assign detect_r_err = ((rx_isk[0]) && (rx_din == `PRIM_R_ERR )) || r_err_cont;
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assign detect_r_err = ((rx_is_k[0]) && (rx_din == `PRIM_R_ERR )) || r_err_cont;
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assign detect_r_ok = ((rx_isk[0]) && (rx_din == `PRIM_R_OK )) || r_ok_cont;
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assign detect_r_ok = ((rx_is_k[0]) && (rx_din == `PRIM_R_OK )) || r_ok_cont;
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assign detect_x_rdy = ((rx_isk[0]) && (rx_din == `PRIM_X_RDY )) || x_rdy_cont;
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assign detect_x_rdy = ((rx_is_k[0]) && (rx_din == `PRIM_X_RDY )) || x_rdy_cont;
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assign detect_sof = (rx_isk[0]) && (rx_din == `PRIM_SOF );
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assign detect_sof = (rx_is_k[0]) && (rx_din == `PRIM_SOF );
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assign detect_eof = (rx_isk[0]) && (rx_din == `PRIM_EOF );
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assign detect_eof = (rx_is_k[0]) && (rx_din == `PRIM_EOF );
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assign detect_wtrm = ((rx_isk[0]) && (rx_din == `PRIM_WTRM )) || wtrm_cont;
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assign detect_wtrm = ((rx_is_k[0]) && (rx_din == `PRIM_WTRM )) || wtrm_cont;
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assign detect_cont = (rx_isk[0]) && (rx_din == `PRIM_CONT );
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assign detect_cont = (rx_is_k[0]) && (rx_din == `PRIM_CONT );
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assign detect_hold = ((rx_isk[0]) && (rx_din == `PRIM_HOLD )) || hold_cont; //hold (normal) == hold (cont)
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assign detect_hold = ((rx_is_k[0]) && (rx_din == `PRIM_HOLD )) || hold_cont; //hold (normal) == hold (cont)
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assign detect_holda = ((rx_isk[0]) && (rx_din == `PRIM_HOLDA )) || holda_cont; //holda (normal) == holda (cont)
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assign detect_holda = ((rx_is_k[0]) && (rx_din == `PRIM_HOLDA )) || holda_cont; //holda (normal) == holda (cont)
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assign detect_preq_s = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_S )) || pmreq_s_cont;
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assign detect_preq_s = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_S )) || pmreq_s_cont;
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assign detect_preq_p = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_P )) || pmreq_p_cont;
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assign detect_preq_p = ((rx_is_k[0]) && (rx_din == `PRIM_PREQ_P )) || pmreq_p_cont;
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assign detect_align = (rx_isk[0]) && (rx_din == `PRIM_ALIGN );
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assign detect_align = (rx_is_k[0]) && (rx_din == `PRIM_ALIGN );
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assign detect_xrdy_xrdy = ((((rx_isk[0])&& (rx_din == `PRIM_X_RDY )) || x_rdy_cont) && ll_tx_isk && (ll_tx_din == `PRIM_X_RDY));
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assign detect_xrdy_xrdy = ((((rx_is_k[0])&& (rx_din == `PRIM_X_RDY )) || x_rdy_cont) && ll_tx_is_k && (ll_tx_din == `PRIM_X_RDY));
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assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
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assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_is_k[0] || detect_align));
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assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable
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assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable
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((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_din : //if the prev != curr (exit)
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((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_din : //if the prev != curr (exit)
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(last_prim) ? ll_tx_din:
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(last_prim) ? ll_tx_din:
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(tx_cont_enable) ? //if the cont is enabled
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(tx_cont_enable) ? //if the cont is enabled
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send_cont ? `PRIM_CONT : //need to first send the cont
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send_cont ? `PRIM_CONT : //need to first send the cont
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scram_dout : //send the junk
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scram_dout : //send the junk
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ll_tx_din; //tx cont is not enabled
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ll_tx_din; //tx cont is not enabled
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assign cont_tx_isk = (!xmit_cont_en) ? ll_tx_isk :
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assign cont_tx_is_k = (!xmit_cont_en) ? ll_tx_is_k :
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((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_isk ://if the prev != curr (exit)
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((tx_prev_prim != ll_tx_din) && ll_tx_is_k) ? ll_tx_is_k ://if the prev != curr (exit)
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(last_prim) ?ll_tx_isk:
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(last_prim) ?ll_tx_is_k:
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(tx_cont_enable) ? //if the cont is enabled
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(tx_cont_enable) ? //if the cont is enabled
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send_cont ? 1 : //need to first send the cont
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send_cont ? 1'b1 : //need to first send the cont
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0 : //send the junk
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1'b0 : //send the junk
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ll_tx_isk; //tx cont is not enabled
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ll_tx_is_k; //tx cont is not enabled
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assign scram_en = tx_cont_enable;
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assign scram_en = tx_cont_enable;
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//Synchronous logic
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//Synchronous logic
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//Cont detect
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//Cont detect
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if (rst) begin
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if (rst) begin
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cont_detect <= 0;
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cont_detect <= 0;
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hold_cont_ready <= 0;
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hold_cont_ready <= 0;
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holda_cont_ready <= 0;
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holda_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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r_err_cont_ready <= 0;
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r_err_cont_ready <= 0;
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r_ip_cont_ready <= 0;
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r_ip_cont_ready <= 0;
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r_ok_cont_ready <= 0;
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r_ok_cont_ready <= 0;
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r_rdy_cont_ready <= 0;
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r_rdy_cont_ready <= 0;
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sync_cont_ready <= 0;
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sync_cont_ready <= 0;
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wtrm_cont_ready <= 0;
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wtrm_cont_ready <= 0;
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x_rdy_cont_ready <= 0;
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x_rdy_cont_ready <= 0;
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end
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end
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else begin
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else begin
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if (!detect_align) begin
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if (!detect_align) begin
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if (rx_isk) begin
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if (rx_is_k) begin
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if (rx_din == `PRIM_CONT) begin
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if (rx_din == `PRIM_CONT) begin
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cont_detect <= 1;
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cont_detect <= 1;
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end
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end
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else if (prev_prim == rx_din) begin
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else if (prev_prim == rx_din) begin
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case (prev_prim)
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case (prev_prim)
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`PRIM_SYNC : begin
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`PRIM_SYNC : begin
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sync_cont_ready <= 1;
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sync_cont_ready <= 1;
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end
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end
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`PRIM_R_RDY : begin
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`PRIM_R_RDY : begin
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r_rdy_cont_ready <= 1;
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r_rdy_cont_ready <= 1;
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end
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end
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`PRIM_R_IP : begin
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`PRIM_R_IP : begin
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r_ip_cont_ready <= 1;
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r_ip_cont_ready <= 1;
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end
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end
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`PRIM_R_ERR : begin
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`PRIM_R_ERR : begin
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r_err_cont_ready <= 1;
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r_err_cont_ready <= 1;
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end
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end
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`PRIM_R_OK : begin
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`PRIM_R_OK : begin
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r_ok_cont_ready <= 1;
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r_ok_cont_ready <= 1;
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end
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end
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`PRIM_X_RDY : begin
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`PRIM_X_RDY : begin
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x_rdy_cont_ready <= 1;
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x_rdy_cont_ready <= 1;
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end
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end
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`PRIM_WTRM : begin
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`PRIM_WTRM : begin
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wtrm_cont_ready <= 1;
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wtrm_cont_ready <= 1;
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end
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end
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`PRIM_HOLD : begin
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`PRIM_HOLD : begin
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if (cont_detect) begin
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if (cont_detect) begin
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hold_cont_ready <= 0;
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hold_cont_ready <= 0;
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cont_detect <= 0;
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cont_detect <= 0;
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end
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end
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else begin
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else begin
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hold_cont_ready <= 1;
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hold_cont_ready <= 1;
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end
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end
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end
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end
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`PRIM_HOLDA : begin
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`PRIM_HOLDA : begin
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if (cont_detect) begin
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if (cont_detect) begin
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holda_cont_ready <= 0;
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holda_cont_ready <= 0;
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cont_detect <= 0;
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cont_detect <= 0;
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end
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end
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else begin
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else begin
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holda_cont_ready <= 1;
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holda_cont_ready <= 1;
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end
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end
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end
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end
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`PRIM_PREQ_S : begin
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`PRIM_PREQ_S : begin
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pmreq_s_cont_ready <= 1;
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pmreq_s_cont_ready <= 1;
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end
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end
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`PRIM_PREQ_P : begin
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`PRIM_PREQ_P : begin
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pmreq_p_cont_ready <= 1;
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pmreq_p_cont_ready <= 1;
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end
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end
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`PRIM_ALIGN : begin
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`PRIM_ALIGN : begin
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end
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end
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default: begin
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default: begin
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hold_cont_ready <= 0;
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hold_cont_ready <= 0;
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holda_cont_ready <= 0;
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holda_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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r_err_cont_ready <= 0;
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r_err_cont_ready <= 0;
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r_ip_cont_ready <= 0;
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r_ip_cont_ready <= 0;
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r_ok_cont_ready <= 0;
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r_ok_cont_ready <= 0;
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r_rdy_cont_ready <= 0;
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r_rdy_cont_ready <= 0;
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sync_cont_ready <= 0;
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sync_cont_ready <= 0;
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wtrm_cont_ready <= 0;
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wtrm_cont_ready <= 0;
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x_rdy_cont_ready <= 0;
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x_rdy_cont_ready <= 0;
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end
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end
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endcase
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endcase
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end
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end
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//save the previous primative
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//save the previous primative
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else begin
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else begin
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prev_prim <= rx_din;
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prev_prim <= rx_din;
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//previous primative doesn't equal current primitive
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//previous primative doesn't equal current primitive
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cont_detect <= 0;
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cont_detect <= 0;
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hold_cont_ready <= 0;
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hold_cont_ready <= 0;
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holda_cont_ready <= 0;
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holda_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_p_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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pmreq_s_cont_ready <= 0;
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r_err_cont_ready <= 0;
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r_err_cont_ready <= 0;
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r_ip_cont_ready <= 0;
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r_ip_cont_ready <= 0;
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r_ok_cont_ready <= 0;
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r_ok_cont_ready <= 0;
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r_rdy_cont_ready <= 0;
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r_rdy_cont_ready <= 0;
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sync_cont_ready <= 0;
|
sync_cont_ready <= 0;
|
wtrm_cont_ready <= 0;
|
wtrm_cont_ready <= 0;
|
x_rdy_cont_ready <= 0;
|
x_rdy_cont_ready <= 0;
|
|
|
end
|
end
|
end
|
end
|
if (!rx_isk[0] && !cont_detect) begin
|
if (!rx_is_k[0] && !cont_detect) begin
|
cont_detect <= 0;
|
cont_detect <= 0;
|
hold_cont_ready <= 0;
|
hold_cont_ready <= 0;
|
holda_cont_ready <= 0;
|
holda_cont_ready <= 0;
|
pmreq_p_cont_ready <= 0;
|
pmreq_p_cont_ready <= 0;
|
pmreq_s_cont_ready <= 0;
|
pmreq_s_cont_ready <= 0;
|
r_err_cont_ready <= 0;
|
r_err_cont_ready <= 0;
|
r_ip_cont_ready <= 0;
|
r_ip_cont_ready <= 0;
|
r_ok_cont_ready <= 0;
|
r_ok_cont_ready <= 0;
|
r_rdy_cont_ready <= 0;
|
r_rdy_cont_ready <= 0;
|
sync_cont_ready <= 0;
|
sync_cont_ready <= 0;
|
wtrm_cont_ready <= 0;
|
wtrm_cont_ready <= 0;
|
x_rdy_cont_ready <= 0;
|
x_rdy_cont_ready <= 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
//Cont Generator
|
//Cont Generator
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if (rst || !xmit_cont_en) begin
|
if (rst || !xmit_cont_en) begin
|
tx_prev_prim <= 0;
|
tx_prev_prim <= 0;
|
tx_cont_enable <= 0;
|
tx_cont_enable <= 0;
|
tx_cont_sent <= 0;
|
tx_cont_sent <= 0;
|
send_cont <= 0;
|
send_cont <= 0;
|
end
|
end
|
else begin
|
else begin
|
if (phy_ready) begin
|
if (phy_ready) begin
|
|
|
send_cont <= 0;
|
send_cont <= 0;
|
|
|
if (ll_tx_isk) begin
|
if (ll_tx_is_k) begin
|
|
|
//reset everything because the previous primative is not equal to the current one
|
//reset everything because the previous primative is not equal to the current one
|
if (tx_prev_prim != ll_tx_din) begin
|
if (tx_prev_prim != ll_tx_din) begin
|
send_cont <= 0;
|
send_cont <= 0;
|
tx_cont_sent <= 0;
|
tx_cont_sent <= 0;
|
tx_cont_enable <= 0;
|
tx_cont_enable <= 0;
|
end
|
end
|
else begin
|
else begin
|
|
|
//see if we need to send the cont primative
|
//see if we need to send the cont primative
|
if (tx_cont_enable && send_cont) begin
|
if (tx_cont_enable && send_cont) begin
|
tx_cont_sent <= 1;
|
tx_cont_sent <= 1;
|
end
|
end
|
|
|
//previous primative == current primative
|
//previous primative == current primative
|
case (tx_prev_prim)
|
case (tx_prev_prim)
|
`PRIM_SYNC : begin
|
`PRIM_SYNC : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_R_RDY : begin
|
`PRIM_R_RDY : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_R_IP : begin
|
`PRIM_R_IP : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_R_ERR : begin
|
`PRIM_R_ERR : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_R_OK : begin
|
`PRIM_R_OK : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_X_RDY : begin
|
`PRIM_X_RDY : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_WTRM : begin
|
`PRIM_WTRM : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_HOLD : begin
|
`PRIM_HOLD : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_HOLDA : begin
|
`PRIM_HOLDA : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_PREQ_S : begin
|
`PRIM_PREQ_S : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
`PRIM_PREQ_P : begin
|
`PRIM_PREQ_P : begin
|
tx_cont_enable <= 1;
|
tx_cont_enable <= 1;
|
if (!tx_cont_sent && !send_cont) begin
|
if (!tx_cont_sent && !send_cont) begin
|
send_cont <= 1;
|
send_cont <= 1;
|
end
|
end
|
end
|
end
|
default: begin
|
default: begin
|
send_cont <= 0;
|
send_cont <= 0;
|
tx_cont_enable <= 0;
|
tx_cont_enable <= 0;
|
tx_cont_sent <= 0;
|
tx_cont_sent <= 0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
//it is not a k value so don't read it
|
//it is not a k value so don't read it
|
tx_prev_prim <= 0;
|
tx_prev_prim <= 0;
|
end
|
end
|
//k value record the PRIM
|
//k value record the PRIM
|
tx_prev_prim <= ll_tx_din;
|
tx_prev_prim <= ll_tx_din;
|
|
|
if (last_prim) begin
|
if (last_prim) begin
|
tx_cont_enable <= 0;
|
tx_cont_enable <= 0;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|