`timescale 1ns/1ps
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`timescale 1ns/1ps
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`include "sata_defines.v"
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`include "sata_defines.v"
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module tb_cocotb (
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module tb_cocotb (
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//Parameters
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//Parameters
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//Registers/Wires
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//Registers/Wires
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input rst, //reset
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input rst, //reset
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input clk,
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input clk,
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output linkup, //link is finished
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output linkup, //link is finished
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output sata_ready,
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output sata_ready,
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output busy,
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output sata_busy,
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input write_data_en,
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//input write_data_stb,
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input read_data_en,
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//input read_data_stb,
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input [7:0] hard_drive_command,
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input execute_command_stb,
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input soft_reset_en,
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input command_layer_reset,
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input [15:0] sector_count,
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input [15:0] sector_count,
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input [47:0] sector_address,
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input [47:0] sector_address,
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output d2h_interrupt,
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output d2h_interrupt,
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output d2h_notification,
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output d2h_notification,
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output [3:0] d2h_port_mult,
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output [3:0] d2h_port_mult,
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output [7:0] d2h_device,
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output [7:0] d2h_device,
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output [47:0] d2h_lba,
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output [47:0] d2h_lba,
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output [15:0] d2h_sector_count,
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output [15:0] d2h_sector_count,
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output [7:0] d2h_status,
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output [7:0] d2h_status,
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output [7:0] d2h_error,
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output [7:0] d2h_error,
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input u2h_write_enable,
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input u2h_write_enable,
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output u2h_write_finished,
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output u2h_write_finished,
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input [23:0] u2h_write_count,
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input [23:0] u2h_write_count,
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input h2u_read_enable,
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input h2u_read_enable,
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output [23:0] h2u_read_total_count,
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output [23:0] h2u_read_total_count,
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output h2u_read_error,
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output h2u_read_error,
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output h2u_read_busy,
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output h2u_read_busy,
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output u2h_read_error,
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output u2h_read_error,
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output transport_layer_ready,
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output transport_layer_ready,
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output link_layer_ready,
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output link_layer_ready,
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output phy_ready,
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output phy_ready,
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input prim_scrambler_en,
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input prim_scrambler_en,
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input data_scrambler_en,
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input data_scrambler_en,
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//Data Interface
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//Data Interface
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output tx_set_elec_idle,
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output tx_set_elec_idle,
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output rx_is_elec_idle,
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output rx_is_elec_idle,
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output hd_ready,
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output hd_ready,
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input platform_ready,
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input platform_ready,
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//Debug
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//Debug
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input hold,
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input hold,
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input single_rdwr
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input single_rdwr
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);
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);
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reg [31:0] test_id = 0;
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reg [31:0] test_id = 0;
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wire [31:0] tx_dout;
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wire [31:0] tx_dout;
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wire tx_isk;
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wire tx_is_k;
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wire tx_comm_reset;
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wire tx_comm_reset;
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wire tx_comm_wake;
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wire tx_comm_wake;
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wire tx_elec_idle;
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wire tx_elec_idle;
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wire [31:0] rx_din;
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wire [31:0] rx_din;
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wire [3:0] rx_isk;
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wire [3:0] rx_is_k;
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wire rx_elec_idle;
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wire rx_elec_idle;
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wire comm_init_detect;
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wire comm_init_detect;
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wire comm_wake_detect;
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wire comm_wake_detect;
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wire rx_byte_is_aligned;
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reg r_rst;
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reg r_rst;
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reg r_write_data_en;
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reg r_write_data_stb;
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reg r_read_data_en;
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reg r_read_data_stb;
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reg r_soft_reset_en;
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reg r_command_layer_reset;
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reg [15:0] r_sector_count;
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reg [15:0] r_sector_count;
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reg [47:0] r_sector_address;
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reg [47:0] r_sector_address;
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reg r_prim_scrambler_en;
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reg r_prim_scrambler_en;
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reg r_data_scrambler_en;
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reg r_data_scrambler_en;
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reg r_platform_ready;
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reg r_platform_ready;
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reg r_dout_count;
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reg r_dout_count;
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reg r_hold;
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reg r_hold;
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reg r_single_rdwr;
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reg r_u2h_write_enable;
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reg r_u2h_write_enable;
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reg [23:0] r_u2h_write_count;
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reg [23:0] r_u2h_write_count;
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reg r_h2u_read_enable;
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reg r_h2u_read_enable;
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reg [7:0] r_hard_drive_command;
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reg r_execute_command_stb;
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wire hd_read_from_host;
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wire hd_read_from_host;
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wire [31:0] hd_data_from_host;
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wire [31:0] hd_data_from_host;
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wire hd_write_to_host;
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wire hd_write_to_host;
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wire [31:0] hd_data_to_host;
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wire [31:0] hd_data_to_host;
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wire [31:0] user_dout;
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wire [31:0] user_dout;
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wire user_dout_ready;
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wire user_dout_ready;
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wire user_dout_activate;
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wire user_dout_activate;
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wire user_dout_stb;
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wire user_dout_stb;
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wire [23:0] user_dout_size;
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wire [23:0] user_dout_size;
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wire [31:0] user_din;
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wire [31:0] user_din;
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wire user_din_stb;
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wire user_din_stb;
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wire [1:0] user_din_ready;
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wire [1:0] user_din_ready;
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wire [1:0] user_din_activate;
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wire [1:0] user_din_activate;
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wire [23:0] user_din_size;
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wire [23:0] user_din_size;
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wire dma_activate_stb;
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wire d2h_reg_stb;
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wire pio_setup_stb;
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wire d2h_data_stb;
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wire dma_setup_stb;
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wire set_device_bits_stb;
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wire [7:0] d2h_fis;
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wire i_rx_byte_is_aligned;
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//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
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//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
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always @ (*) r_rst = rst;
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always @ (*) r_rst = rst;
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always @ (*) r_write_data_en = write_data_en;
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//always @ (*) r_write_data_stb = write_data_stb;
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always @ (*) r_read_data_en = read_data_en;
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//always @ (*) r_read_data_stb = read_data_stb;
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always @ (*) r_soft_reset_en = soft_reset_en;
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always @ (*) r_command_layer_reset= command_layer_reset;
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always @ (*) r_sector_count = sector_count;
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always @ (*) r_sector_count = sector_count;
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always @ (*) r_sector_address = sector_address;
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always @ (*) r_sector_address = sector_address;
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always @ (*) r_prim_scrambler_en = prim_scrambler_en;
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always @ (*) r_prim_scrambler_en = prim_scrambler_en;
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always @ (*) r_data_scrambler_en = data_scrambler_en;
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always @ (*) r_data_scrambler_en = data_scrambler_en;
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always @ (*) r_platform_ready = platform_ready;
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always @ (*) r_platform_ready = platform_ready;
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always @ (*) r_hold = hold;
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always @ (*) r_hold = hold;
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always @ (*) r_single_rdwr = single_rdwr;
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always @ (*) r_u2h_write_enable = u2h_write_enable;
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always @ (*) r_u2h_write_enable = u2h_write_enable;
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always @ (*) r_u2h_write_count = u2h_write_count;
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always @ (*) r_u2h_write_count = u2h_write_count;
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always @ (*) r_h2u_read_enable = h2u_read_enable;
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always @ (*) r_h2u_read_enable = h2u_read_enable;
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always @ (*) r_hard_drive_command = hard_drive_command;
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always @ (*) r_execute_command_stb= execute_command_stb;
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//Submodules
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//Submodules
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//User Generated Test Data
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//User Generated Test Data
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test_in user_2_hd_generator(
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test_in user_2_hd_generator(
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.clk (clk ),
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.clk (clk ),
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.rst (rst ),
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.rst (rst ),
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.enable (r_u2h_write_enable ),
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.enable (r_u2h_write_enable ),
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.finished (u2h_write_finished ),
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.finished (u2h_write_finished ),
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.write_count (r_u2h_write_count ),
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.write_count (r_u2h_write_count ),
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.ready (user_din_ready ),
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.ready (user_din_ready ),
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.activate (user_din_activate ),
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.activate (user_din_activate ),
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.fifo_data (user_din ),
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.fifo_data (user_din ),
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.fifo_size (user_din_size ),
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.fifo_size (user_din_size ),
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.strobe (user_din_stb )
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.strobe (user_din_stb )
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);
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);
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//Module to process data from Hard Drive to User
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//Module to process data from Hard Drive to User
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test_out hd_2_user_reader(
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test_out hd_2_user_reader(
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.clk (clk ),
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.clk (clk ),
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.rst (rst ),
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.rst (rst ),
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.busy (h2u_read_busy ),
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.busy (h2u_read_busy ),
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.enable (r_h2u_read_enable ),
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.enable (r_h2u_read_enable ),
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.error (h2u_read_error ),
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.error (h2u_read_error ),
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.total_count (h2u_read_total_count ),
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.total_count (h2u_read_total_count ),
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.ready (user_dout_ready ),
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.ready (user_dout_ready ),
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.activate (user_dout_activate ),
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.activate (user_dout_activate ),
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.size (user_dout_size ),
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.size (user_dout_size ),
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.data (user_dout ),
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.data (user_dout ),
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.strobe (user_dout_stb )
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.strobe (user_dout_stb )
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);
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);
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//hd data reader core
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//hd data reader core
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hd_data_reader user_2_hd_reader(
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hd_data_reader user_2_hd_reader(
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.clk (clk ),
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.clk (clk ),
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.rst (rst ),
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.rst (rst ),
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.enable (r_u2h_write_enable ),
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.enable (r_u2h_write_enable ),
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.error (u2h_read_error ),
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.error (u2h_read_error ),
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.hd_read_from_host (hd_read_from_host ),
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.hd_read_from_host (hd_read_from_host ),
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.hd_data_from_host (hd_data_from_host )
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.hd_data_from_host (hd_data_from_host )
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);
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);
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//hd data writer core
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//hd data writer core
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hd_data_writer hd_2_user_generator(
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hd_data_writer hd_2_user_generator(
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.clk (clk ),
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.clk (clk ),
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.rst (rst ),
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.rst (rst ),
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.enable (r_h2u_read_enable ),
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.enable (r_h2u_read_enable ),
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.data (hd_data_to_host ),
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.data (hd_data_to_host ),
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.strobe (hd_write_to_host )
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.strobe (hd_write_to_host )
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);
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);
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sata_stack ss (
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sata_stack ss (
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.rst (r_rst ), //reset
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.rst (r_rst ), //reset
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.clk (clk ), //clock used to run the stack
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.clk (clk ), //clock used to run the stack
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.data_in_clk (clk ),
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.command_layer_reset (r_command_layer_reset),
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.data_in_clk_valid (1'b1 ),
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.data_out_clk (clk ),
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.data_out_clk_valid (1'b1 ),
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.platform_ready (platform_ready ), //the underlying physical platform is
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.platform_ready (platform_ready ), //the underlying physical platform is
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.platform_error ( ),
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.linkup (linkup ), //link is finished
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.linkup (linkup ), //link is finished
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.sata_ready (sata_ready ),
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.sata_ready (sata_ready ),
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.sata_busy (sata_busy ),
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.busy (busy ),
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.send_sync_escape (1'b0 ),
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.hard_drive_error ( ),
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.write_data_en (r_write_data_en ),
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.pio_data_ready ( ),
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.single_rdwr (r_single_rdwr ),
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.read_data_en (r_read_data_en ),
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.send_user_command_stb (1'b0 ),
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.soft_reset_en (r_soft_reset_en ),
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.command (1'b0 ),
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//Host to Device Control
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// .write_data_stb (r_write_data_stb ),
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// .read_data_stb (r_read_data_stb ),
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.hard_drive_command (r_hard_drive_command ),
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.execute_command_stb (r_execute_command_stb),
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.user_features (16'h0000 ),
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.sector_count (r_sector_count ),
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.sector_count (r_sector_count ),
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.sector_address (r_sector_address ),
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.sector_address (r_sector_address ),
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.dma_activate_stb (dma_activate_stb ),
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.d2h_reg_stb (d2h_reg_stb ),
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.pio_setup_stb (pio_setup_stb ),
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.d2h_data_stb (d2h_data_stb ),
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.dma_setup_stb (dma_setup_stb ),
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.set_device_bits_stb (set_device_bits_stb ),
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.d2h_fis (d2h_fis ),
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.d2h_interrupt (d2h_interrupt ),
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.d2h_interrupt (d2h_interrupt ),
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.d2h_notification (d2h_notification ),
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.d2h_notification (d2h_notification ),
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.d2h_port_mult (d2h_port_mult ),
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.d2h_port_mult (d2h_port_mult ),
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.d2h_device (d2h_device ),
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.d2h_device (d2h_device ),
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.d2h_lba (d2h_lba ),
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.d2h_lba (d2h_lba ),
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.d2h_sector_count (d2h_sector_count ),
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.d2h_sector_count (d2h_sector_count ),
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.d2h_status (d2h_status ),
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.d2h_status (d2h_status ),
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.d2h_error (d2h_error ),
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.d2h_error (d2h_error ),
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//Data from host to the hard drive path
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.data_in_clk (clk ),
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.data_in_clk_valid (1'b1 ),
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.user_din (user_din ), //User Data Here
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.user_din (user_din ), //User Data Here
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.user_din_stb (user_din_stb ), //Strobe Each Data word in here
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.user_din_stb (user_din_stb ), //Strobe Each Data word in here
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.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
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.user_din_ready (user_din_ready ), //Using PPFIFO Ready Signal
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.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
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.user_din_activate (user_din_activate ), //Activate PPFIFO Channel
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.user_din_size (user_din_size ), //Find the size of the data to write to the device
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.user_din_size (user_din_size ), //Find the size of the data to write to the device
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//Data from hard drive to host path
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.data_out_clk (clk ),
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.data_out_clk_valid (1'b1 ),
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.user_dout (user_dout ),
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.user_dout (user_dout ),
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.user_dout_ready (user_dout_ready ),
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.user_dout_ready (user_dout_ready ),
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.user_dout_activate (user_dout_activate ),
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.user_dout_activate (user_dout_activate ),
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.user_dout_stb (user_dout_stb ),
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.user_dout_stb (user_dout_stb ),
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.user_dout_size (user_dout_size ),
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.user_dout_size (user_dout_size ),
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.transport_layer_ready (transport_layer_ready),
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.transport_layer_ready (transport_layer_ready),
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.link_layer_ready (link_layer_ready ),
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.link_layer_ready (link_layer_ready ),
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.phy_ready (phy_ready ),
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.phy_ready (phy_ready ),
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.phy_error (1'b0 ),
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.tx_dout (tx_dout ),
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.tx_dout (tx_dout ),
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.tx_isk (tx_isk ),
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.tx_is_k (tx_is_k ),
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.tx_comm_reset (tx_comm_reset ),
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.tx_comm_reset (tx_comm_reset ),
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.tx_comm_wake (tx_comm_wake ),
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.tx_comm_wake (tx_comm_wake ),
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.tx_elec_idle (tx_elec_idle ),
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.tx_elec_idle (tx_elec_idle ),
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.tx_oob_complete (1'b1 ),
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.rx_din (rx_din ),
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.rx_din (rx_din ),
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.rx_isk (rx_isk ),
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.rx_is_k (rx_is_k ),
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.rx_elec_idle (rx_elec_idle ),
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.rx_elec_idle (rx_elec_idle ),
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.rx_byte_is_aligned (i_rx_byte_is_aligned ),
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.comm_init_detect (comm_init_detect ),
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.comm_init_detect (comm_init_detect ),
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.comm_wake_detect (comm_wake_detect ),
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.comm_wake_detect (comm_wake_detect ),
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.rx_byte_is_aligned (rx_byte_is_aligned ),
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.prim_scrambler_en (r_prim_scrambler_en ),
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//.prim_scrambler_en (r_prim_scrambler_en ),
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.data_scrambler_en (r_data_scrambler_en )
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.prim_scrambler_en (1'b1 ),
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//.data_scrambler_en (r_data_scrambler_en )
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.data_scrambler_en (1'b1 )
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);
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);
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|
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faux_sata_hd fshd (
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faux_sata_hd fshd (
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.rst (r_rst ),
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.rst (r_rst ),
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.clk (clk ),
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.clk (clk ),
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.tx_dout (rx_din ),
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.tx_dout (rx_din ),
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.tx_isk (rx_isk ),
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.tx_is_k (rx_is_k ),
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.rx_din (tx_dout ),
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.rx_din (tx_dout ),
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.rx_isk ({3'b000, tx_isk} ),
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.rx_is_k ({3'b000, tx_is_k} ),
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.rx_is_elec_idle (tx_elec_idle ),
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.rx_is_elec_idle (tx_elec_idle ),
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.rx_byte_is_aligned (rx_byte_is_aligned ),
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.rx_byte_is_aligned (i_rx_byte_is_aligned ),
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.comm_reset_detect (tx_comm_reset ),
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.comm_reset_detect (tx_comm_reset ),
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.comm_wake_detect (tx_comm_wake ),
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.comm_wake_detect (tx_comm_wake ),
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.tx_comm_reset (comm_init_detect ),
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.tx_comm_reset (comm_init_detect ),
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.tx_comm_wake (comm_wake_detect ),
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.tx_comm_wake (comm_wake_detect ),
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.hd_ready (hd_ready ),
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.hd_ready (hd_ready ),
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// .phy_ready (phy_ready ),
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// .phy_ready (phy_ready ),
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.dbg_data_scrambler_en (r_data_scrambler_en ),
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//.dbg_data_scrambler_en (r_data_scrambler_en ),
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.dbg_data_scrambler_en (1'b1 ),
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.dbg_hold (r_hold ),
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.dbg_hold (r_hold ),
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.dbg_ll_write_start (0 ),
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.dbg_ll_write_start (1'b0 ),
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.dbg_ll_write_data (0 ),
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.dbg_ll_write_data (32'h0 ),
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.dbg_ll_write_size (0 ),
|
.dbg_ll_write_size (0 ),
|
.dbg_ll_write_hold (0 ),
|
.dbg_ll_write_hold (1'b0 ),
|
.dbg_ll_write_abort (0 ),
|
.dbg_ll_write_abort (1'b0 ),
|
|
|
|
.dbg_ll_read_ready (1'b0 ),
|
|
.dbg_t_en (1'b0 ),
|
|
|
.dbg_ll_read_ready (0 ),
|
.dbg_send_reg_stb (1'b0 ),
|
.dbg_t_en (0 ),
|
.dbg_send_dma_act_stb (1'b0 ),
|
|
.dbg_send_data_stb (1'b0 ),
|
|
.dbg_send_pio_stb (1'b0 ),
|
|
.dbg_send_dev_bits_stb (1'b0 ),
|
|
|
|
.dbg_pio_transfer_count(16'h0000 ),
|
|
.dbg_pio_direction (1'b0 ),
|
|
.dbg_pio_e_status (8'h00 ),
|
|
|
|
.dbg_d2h_interrupt (1'b0 ),
|
|
.dbg_d2h_notification (1'b0 ),
|
|
.dbg_d2h_status (8'b0 ),
|
|
.dbg_d2h_error (8'b0 ),
|
|
.dbg_d2h_port_mult (4'b0000 ),
|
|
.dbg_d2h_device (8'h00 ),
|
|
.dbg_d2h_lba (48'h000000000000 ),
|
|
.dbg_d2h_sector_count (16'h0000 ),
|
|
|
|
.dbg_cl_if_data (32'b0 ),
|
|
.dbg_cl_if_ready (1'b0 ),
|
|
.dbg_cl_if_size (24'h0 ),
|
|
|
.dbg_send_reg_stb (0 ),
|
.dbg_cl_of_ready (2'b0 ),
|
.dbg_send_dma_act_stb (0 ),
|
.dbg_cl_of_size (24'h0 ),
|
.dbg_send_data_stb (0 ),
|
|
.dbg_send_pio_stb (0 ),
|
|
.dbg_send_dev_bits_stb (0 ),
|
|
|
|
.dbg_pio_transfer_count(0 ),
|
|
.dbg_pio_direction (0 ),
|
|
.dbg_pio_e_status (0 ),
|
|
|
|
.dbg_d2h_interrupt (0 ),
|
|
.dbg_d2h_notification (0 ),
|
|
.dbg_d2h_status (0 ),
|
|
.dbg_d2h_error (0 ),
|
|
.dbg_d2h_port_mult (0 ),
|
|
.dbg_d2h_device (0 ),
|
|
.dbg_d2h_lba (0 ),
|
|
.dbg_d2h_sector_count (0 ),
|
|
|
|
.dbg_cl_if_data (0 ),
|
|
.dbg_cl_if_ready (0 ),
|
|
.dbg_cl_if_size (0 ),
|
|
.dbg_cl_of_ready (0 ),
|
|
.dbg_cl_of_size (0 ),
|
|
.hd_read_from_host (hd_read_from_host ),
|
.hd_read_from_host (hd_read_from_host ),
|
.hd_data_from_host (hd_data_from_host ),
|
.hd_data_from_host (hd_data_from_host ),
|
|
|
|
|
.hd_write_to_host (hd_write_to_host ),
|
.hd_write_to_host (hd_write_to_host ),
|
.hd_data_to_host (hd_data_to_host )
|
.hd_data_to_host (hd_data_to_host )
|
|
|
|
|
);
|
);
|
|
|
//Asynchronous Logic
|
//Asynchronous Logic
|
//Synchronous Logic
|
//Synchronous Logic
|
//Simulation Control
|
//Simulation Control
|
initial begin
|
initial begin
|
$dumpfile ("design.vcd");
|
$dumpfile ("design.vcd");
|
$dumpvars(0, tb_cocotb);
|
$dumpvars(0, tb_cocotb);
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|