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TOPLEVEL_LANG ?= verilog
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TOPLEVEL_LANG ?= verilog
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PWD=$(shell pwd)
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PWD=$(shell pwd)
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TOPDIR=$(PWD)/..
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TOPDIR=$(PWD)/..
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COCOTB=/home/cospan/Projects/cocotb
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COCOTB=/home/cospan/Projects/cocotb
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PYTHONPATH := ./model:$(PYTHONPATH)
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PYTHONPATH := ./model:$(PYTHONPATH)
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export PYTHONPATH
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export PYTHONPATH
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EXTRA_ARGS+=-I$(TOPDIR)/rtl/
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EXTRA_ARGS+=-I$(TOPDIR)/rtl/
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|
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VERILOG_SOURCES = $(TOPDIR)/sim/test_in.v
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VERILOG_SOURCES = $(TOPDIR)/sim/test_in.v
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VERILOG_SOURCES += $(TOPDIR)/sim/test_out.v
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VERILOG_SOURCES += $(TOPDIR)/sim/test_out.v
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|
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VERILOG_SOURCES += $(TOPDIR)/sim/hd_data_writer.v
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VERILOG_SOURCES += $(TOPDIR)/sim/hd_data_writer.v
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VERILOG_SOURCES += $(TOPDIR)/sim/hd_data_reader.v
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VERILOG_SOURCES += $(TOPDIR)/sim/hd_data_reader.v
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|
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/blk_mem.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/blk_mem.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/cross_clock_enable.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/cross_clock_enable.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/debounce.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/debounce.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/ppfifo.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/generic/ppfifo.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/cont_controller.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/cont_controller.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/crc.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/crc.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/sata_link_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/sata_link_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/sata_link_layer_read.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/sata_link_layer_read.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/sata_link_layer_write.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/sata_link_layer_write.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/scrambler.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/link/scrambler.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/phy/oob_controller.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/phy/oob_controller.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/phy/sata_phy_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/phy/sata_phy_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/transport/sata_transport_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/transport/sata_transport_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/command/sata_command_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/command/sata_command_layer.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/sata_stack.v
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VERILOG_SOURCES += $(TOPDIR)/rtl/sata_stack.v
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|
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd_phy.v
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd_phy.v
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd_transport.v
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd_transport.v
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd_command_layer.v
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd_command_layer.v
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd.v
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VERILOG_SOURCES += $(TOPDIR)/sim/faux_sata_hd.v
|
|
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VERILOG_SOURCES += $(TOPDIR)/sim/tb_cocotb.v
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VERILOG_SOURCES += $(TOPDIR)/sim/tb_cocotb.v
|
|
|
|
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TOPLEVEL = tb_cocotb
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TOPLEVEL = tb_cocotb
|
|
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GPI_IMPL := vpi
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GPI_IMPL := vpi
|
|
|
export TOPLEVEL_LANG
|
export TOPLEVEL_LANG
|
MODULE=test_sata
|
MODULE=test_sata
|
|
|
include $(COCOTB)/makefiles/Makefile.inc
|
include $(COCOTB)/makefiles/Makefile.inc
|
include $(COCOTB)/makefiles/Makefile.sim
|
include $(COCOTB)/makefiles/Makefile.sim
|
|
|
wave:
|
wave:
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gtkwave waveforms.gtkw &
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gtkwave waveforms.gtkw &
|
|
|
