/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OpenCores54 DSP, MAC ////
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//// OpenCores54 DSP, MAC ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// richard@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// Xilinx Virtex-E WC: 296 CLB slices @ 64MHz
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// Xilinx Virtex-E WC: 296 CLB slices @ 64MHz
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//
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//
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// CVS Log
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// CVS Log
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//
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//
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// $Id: oc54_mac.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $
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// $Id: oc54_mac.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $
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//
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//
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// $Date: 2002-04-10 09:34:41 $
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// $Date: 2002-04-10 09:34:41 $
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// $Revision: 1.1.1.1 $
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// $Revision: 1.1.1.1 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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`include "timescale.v"
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`include "timescale.v"
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module oc54_mac (
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module oc54_mac (
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clk, ena,
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clk, ena,
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a, b, t, p, c, d,
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a, b, t, p, c, d,
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sel_xm, sel_ym, sel_ya,
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sel_xm, sel_ym, sel_ya,
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bp_a, bp_b, bp_ar, bp_br,
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bp_a, bp_b, bp_ar, bp_br,
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xm_s, ym_s,
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xm_s, ym_s,
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ovm, frct, smul, add_sub,
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ovm, frct, smul, add_sub,
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result
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result
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);
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);
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//
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//
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// parameters
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// parameters
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//
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//
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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input clk;
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input clk;
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input ena;
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input ena;
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input [15:0] t, p, c, d; // TREG, p-bus, c-bus, d-bus inputs
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input [15:0] t, p, c, d; // TREG, p-bus, c-bus, d-bus inputs
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input [39:0] a, b; // accumulator inputs
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input [39:0] a, b; // accumulator inputs
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input [ 1:0] sel_xm, sel_ym, sel_ya; // input selects
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input [ 1:0] sel_xm, sel_ym, sel_ya; // input selects
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input [39:0] bp_ar, bp_br; // bypass accumulator a / b
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input [39:0] bp_ar, bp_br; // bypass accumulator a / b
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input bp_a, bp_b; // bypass selects
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input bp_a, bp_b; // bypass selects
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input xm_s, ym_s; // sign extend xm, ym
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input xm_s, ym_s; // sign extend xm, ym
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input ovm, frct, smul, add_sub;
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input ovm, frct, smul, add_sub;
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output [39:0] result;
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output [39:0] result;
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reg [39:0] result;
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reg [39:0] result;
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//
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//
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// variables
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// variables
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//
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//
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reg [16:0] xm, ym; // multiplier inputs
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reg [16:0] xm, ym; // multiplier inputs
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reg [39:0] ya; // adder Y-input
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reg [39:0] ya; // adder Y-input
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reg [33:0] mult_res; // multiplier result
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reg [33:0] mult_res; // multiplier result
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wire [33:0] imult_res; // actual multiplier
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wire [33:0] imult_res; // actual multiplier
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reg [39:0] iresult; // mac-result
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reg [39:0] iresult; // mac-result
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/////////////////
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/////////////////
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// module body //
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// module body //
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/////////////////
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/////////////////
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//
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//
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// generate input selection
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// generate input selection
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//
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//
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// xm
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// xm
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always@(posedge clk)
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always@(posedge clk)
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if (ena)
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if (ena)
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case(sel_xm) // synopsis full_case parallel_case
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case(sel_xm) // synopsis full_case parallel_case
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2'b00 : xm <= #1 {xm_s ? t[15] : 1'b0, t};
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2'b00 : xm <= #1 {xm_s ? t[15] : 1'b0, t};
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2'b01 : xm <= #1 {xm_s ? d[15] : 1'b0, d};
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2'b01 : xm <= #1 {xm_s ? d[15] : 1'b0, d};
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2'b10 : xm <= #1 bp_a ? bp_ar[32:16] : a[32:16];
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2'b10 : xm <= #1 bp_a ? bp_ar[32:16] : a[32:16];
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2'b11 : xm <= #1 17'h0;
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2'b11 : xm <= #1 17'h0;
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endcase
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endcase
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// ym
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// ym
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always@(posedge clk)
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always@(posedge clk)
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if (ena)
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if (ena)
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case(sel_ym) // synopsis full_case parallel_case
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case(sel_ym) // synopsis full_case parallel_case
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2'b00 : ym <= #1 {ym_s ? p[15] : 1'b0, p};
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2'b00 : ym <= #1 {ym_s ? p[15] : 1'b0, p};
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2'b01 : ym <= #1 bp_a ? bp_ar[32:16] : a[32:16];
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2'b01 : ym <= #1 bp_a ? bp_ar[32:16] : a[32:16];
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2'b10 : ym <= #1 {ym_s ? d[15] : 1'b0, d};
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2'b10 : ym <= #1 {ym_s ? d[15] : 1'b0, d};
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2'b11 : ym <= #1 {ym_s ? c[15] : 1'b0, c};
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2'b11 : ym <= #1 {ym_s ? c[15] : 1'b0, c};
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endcase
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endcase
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// ya
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// ya
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always@(posedge clk)
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always@(posedge clk)
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if (ena)
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if (ena)
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casex(sel_ya) // synopsis full_case parallel_case
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casex(sel_ya) // synopsis full_case parallel_case
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2'b00 : ya <= #1 bp_a ? bp_ar : a;
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2'b00 : ya <= #1 bp_a ? bp_ar : a;
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2'b01 : ya <= #1 bp_b ? bp_br : b;
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2'b01 : ya <= #1 bp_b ? bp_br : b;
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2'b1? : ya <= #1 40'h0;
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2'b1? : ya <= #1 40'h0;
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endcase
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endcase
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//
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//
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// generate multiplier
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// generate multiplier
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//
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//
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assign imult_res = (xm * ym); // actual multiplier
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assign imult_res = (xm * ym); // actual multiplier
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always@(xm or ym or smul or ovm or frct or imult_res)
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always@(xm or ym or smul or ovm or frct or imult_res)
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if (smul && ovm && frct && (xm[15:0] == 16'h8000) && (ym[15:0] == 16'h8000) )
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if (smul && ovm && frct && (xm[15:0] == 16'h8000) && (ym[15:0] == 16'h8000) )
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mult_res = 34'h7ff_ffff;
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mult_res = 34'h7ff_ffff;
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else if (frct)
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else if (frct)
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mult_res = {imult_res[32:0], 1'b0}; // (imult_res << 1)
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mult_res = {imult_res[32:0], 1'b0}; // (imult_res << 1)
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else
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else
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mult_res = imult_res;
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mult_res = imult_res;
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//
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//
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// generate mac-unit
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// generate mac-unit
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//
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//
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always@(mult_res or ya or add_sub)
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always@(mult_res or ya or add_sub)
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if (add_sub)
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if (add_sub)
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iresult = mult_res + ya;
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iresult = mult_res + ya;
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else
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else
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iresult = mult_res - ya;
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iresult = mult_res - ya;
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//
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//
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// generate registers
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// generate registers
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//
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//
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// result
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// result
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always@(posedge clk)
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always@(posedge clk)
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if (ena)
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if (ena)
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result <= #1 iresult;
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result <= #1 iresult;
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endmodule
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endmodule
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