---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Title : blockram
|
-- Title : blockram
|
-- Design : cfft
|
-- Design : cfft
|
-- Author : MENG Lin
|
-- Author : MENG Lin
|
-- email :
|
-- email :
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- File : blockram.vhd
|
-- File : blockram.vhd
|
-- Generated : unknown
|
-- Generated : unknown
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Description : Dual port ram
|
-- Description : Dual port ram
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
--library synplify;
|
--library synplify;
|
--use synplify.attributes.all;
|
--use synplify.attributes.all;
|
|
|
entity blockdram is
|
entity blockdram is
|
generic(
|
generic(
|
depth: natural;
|
depth: natural;
|
Dwidth: natural;
|
Dwidth: natural;
|
Awidth: natural
|
Awidth: natural
|
);
|
);
|
port (
|
port (
|
clkin : in std_logic;
|
clkin : in std_logic;
|
wen : in std_logic;
|
wen : in std_logic;
|
addrin : in std_logic_vector(Awidth-1 downto 0);
|
addrin : in std_logic_vector(Awidth-1 downto 0);
|
din : in std_logic_vector(Dwidth-1 downto 0);
|
din : in std_logic_vector(Dwidth-1 downto 0);
|
clkout : in std_logic;
|
clkout : in std_logic;
|
addrout : in std_logic_vector(Awidth-1 downto 0);
|
addrout : in std_logic_vector(Awidth-1 downto 0);
|
dout : out std_logic_vector(Dwidth-1 downto 0));
|
dout : out std_logic_vector(Dwidth-1 downto 0));
|
end blockdram;
|
end blockdram;
|
|
|
architecture blockdram of blockdram is
|
architecture blockdram of blockdram is
|
|
|
type ram_memtype is array (depth-1 downto 0) of std_logic_vector
|
type ram_memtype is array (depth-1 downto 0) of std_logic_vector
|
(Dwidth-1 downto 0);
|
(Dwidth-1 downto 0);
|
signal mem : ram_memtype := (others => (others => '0'));
|
signal mem : ram_memtype := (others => (others => '0'));
|
--attribute syn_ramstyle of mem : signal is "block_ram";
|
--attribute syn_ramstyle of mem : signal is "block_ram";
|
|
|
signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
|
signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
|
|
|
begin
|
begin
|
wr: process( clkin )
|
wr: process( clkin )
|
begin
|
begin
|
if rising_edge(clkin) then
|
if rising_edge(clkin) then
|
if wen = '1' then
|
if wen = '1' then
|
mem(conv_integer(addrin)) <= din;
|
mem(conv_integer(addrin)) <= din;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process wr;
|
end process wr;
|
|
|
rd: process( clkout )
|
rd: process( clkout )
|
begin
|
begin
|
if rising_edge(clkout) then
|
if rising_edge(clkout) then
|
addrb_reg <= addrout;
|
addrb_reg <= addrout;
|
end if;
|
end if;
|
end process rd;
|
end process rd;
|
dout <= mem(conv_integer(addrb_reg));
|
dout <= mem(conv_integer(addrb_reg));
|
end blockdram;
|
end blockdram;
|
|
|
|
|
