---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Title : cfft
|
-- Title : cfft
|
-- Design : cfft
|
-- Design : cfft
|
-- Author : ZHAO Ming
|
-- Author : ZHAO Ming
|
-- email : sradio@opencores.org
|
-- email : sradio@opencores.org
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- File : cfft.vhd
|
-- File : cfft.vhd
|
-- Generated : Thu Oct 3 03:03:58 2002
|
-- Generated : Thu Oct 3 03:03:58 2002
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with
|
-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with
|
-- limit and overfall processing internal
|
-- limit and overfall processing internal
|
--
|
--
|
-- The gain is 0.0287 for FFT and 29.4 for IFFT
|
-- The gain is 0.0287 for FFT and 29.4 for IFFT
|
--
|
--
|
-- The output is 4-based reversed ordered, it means
|
-- The output is 4-based reversed ordered, it means
|
-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
|
-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
|
--
|
--
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- port :
|
-- port :
|
-- clk : main clk -- I have test 90M with Xilinx virtex600E
|
-- clk : main clk -- I have test 90M with Xilinx virtex600E
|
-- rst : globe reset -- '1' for reset
|
-- rst : globe reset -- '1' for reset
|
-- start : start fft -- one clock '1' before data input
|
-- start : start fft -- one clock '1' before data input
|
-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'
|
-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'
|
-- Iin,Qin : data input-- following start immediately, input data
|
-- Iin,Qin : data input-- following start immediately, input data
|
-- -- power should not be too big
|
-- -- power should not be too big
|
-- inputbusy : if it change to '0' then next fft is enable
|
-- inputbusy : if it change to '0' then next fft is enable
|
-- outdataen : when it is '1', the valid data is output
|
-- outdataen : when it is '1', the valid data is output
|
-- Iout,Qout : fft data output when outdataen is '1'
|
-- Iout,Qout : fft data output when outdataen is '1'
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Revisions : 0
|
-- Revisions : 0
|
-- Revision Number : 1
|
-- Revision Number : 1
|
-- Version : 1.1.0
|
-- Version : 1.1.0
|
-- Date : Oct 17 2002
|
-- Date : Oct 17 2002
|
-- Modifier : ZHAO Ming
|
-- Modifier : ZHAO Ming
|
-- Desccription : Data width configurable
|
-- Desccription : Data width configurable
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Revisions : 0
|
-- Revisions : 0
|
-- Revision Number : 2
|
-- Revision Number : 2
|
-- Version : 1.2.0
|
-- Version : 1.2.0
|
-- Date : Oct 18 2002
|
-- Date : Oct 18 2002
|
-- Modifier : ZHAO Ming
|
-- Modifier : ZHAO Ming
|
-- Desccription : Point configurable
|
-- Desccription : Point configurable
|
-- FFT Gain IFFT GAIN
|
-- FFT Gain IFFT GAIN
|
-- 256 0.0698 17.9
|
-- 256 0.0698 17.9
|
-- 1024 0.0287 29.4
|
-- 1024 0.0287 29.4
|
-- 4096 0.0118 48.2742
|
-- 4096 0.0118 48.2742
|
--
|
--
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Revisions : 0
|
-- Revisions : 0
|
-- Revision Number : 3
|
-- Revision Number : 3
|
-- Version : 1.3.0
|
-- Version : 1.3.0
|
-- Date : Nov 19 2002
|
-- Date : Nov 19 2002
|
-- Modifier : ZHAO Ming
|
-- Modifier : ZHAO Ming
|
-- Desccription : add output data position indication
|
-- Desccription : add output data position indication
|
--
|
--
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.all;
|
use IEEE.STD_LOGIC_1164.all;
|
use IEEE.STD_LOGIC_ARITH.all;
|
use IEEE.STD_LOGIC_ARITH.all;
|
use IEEE.STD_LOGIC_UNSIGNED.all;
|
use IEEE.STD_LOGIC_UNSIGNED.all;
|
|
|
entity cfft is
|
entity cfft is
|
generic (
|
generic (
|
Tx_nRx : natural :=1; -- tx = 1, rx = 0
|
Tx_nRx : natural :=1; -- tx = 1, rx = 0
|
WIDTH : natural := 12;
|
WIDTH : natural := 12;
|
POINT : natural := 64;
|
POINT : natural := 64;
|
STAGE : natural := 3 -- STAGE=log4(POINT)
|
STAGE : natural := 3 -- STAGE=log4(POINT)
|
);
|
);
|
port(
|
port(
|
rst : in std_logic;
|
rst : in std_logic;
|
Iin : in std_logic_vector(WIDTH-1 downto 0);
|
Iin : in std_logic_vector(WIDTH-1 downto 0);
|
Qin : in std_logic_vector(WIDTH-1 downto 0);
|
Qin : in std_logic_vector(WIDTH-1 downto 0);
|
Iout : out std_logic_vector(WIDTH+1 downto 0);
|
Iout : out std_logic_vector(WIDTH+1 downto 0);
|
Qout : out std_logic_vector(WIDTH+1 downto 0);
|
Qout : out std_logic_vector(WIDTH+1 downto 0);
|
factorstart : in std_logic;
|
factorstart : in std_logic;
|
cfft4start : in std_logic;
|
cfft4start : in std_logic;
|
|
|
ClkIn : in std_logic;
|
ClkIn : in std_logic;
|
|
|
sel_mux : in std_logic;
|
sel_mux : in std_logic;
|
inv : in std_logic;
|
inv : in std_logic;
|
|
|
wen_in : in std_logic;
|
wen_in : in std_logic;
|
addrin_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
|
addrin_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
|
addrout_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
|
addrout_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
|
|
|
wen_proc : in std_logic;
|
wen_proc : in std_logic;
|
addrin_proc : in std_logic_vector(2*stage-1 downto 0);
|
addrin_proc : in std_logic_vector(2*stage-1 downto 0);
|
addrout_proc : in std_logic_vector(2*stage-1 downto 0);
|
addrout_proc : in std_logic_vector(2*stage-1 downto 0);
|
|
|
wen_out : in std_logic;
|
wen_out : in std_logic;
|
addrin_out : in std_logic_vector(2*stage-1 downto 0);
|
addrin_out : in std_logic_vector(2*stage-1 downto 0);
|
addrout_out : in std_logic_vector(2*stage-1 downto 0));
|
addrout_out : in std_logic_vector(2*stage-1 downto 0));
|
|
|
end cfft;
|
end cfft;
|
|
|
|
|
architecture cfft of cfft is
|
architecture cfft of cfft is
|
|
|
component mux
|
component mux
|
generic (
|
generic (
|
width : natural);
|
width : natural);
|
port (
|
port (
|
inRa : in std_logic_vector(WIDTH-1 downto 0);
|
inRa : in std_logic_vector(WIDTH-1 downto 0);
|
inIa : in std_logic_vector(WIDTH-1 downto 0);
|
inIa : in std_logic_vector(WIDTH-1 downto 0);
|
inRb : in std_logic_vector(WIDTH-1 downto 0);
|
inRb : in std_logic_vector(WIDTH-1 downto 0);
|
inIb : in std_logic_vector(WIDTH-1 downto 0);
|
inIb : in std_logic_vector(WIDTH-1 downto 0);
|
outR : out std_logic_vector(WIDTH-1 downto 0);
|
outR : out std_logic_vector(WIDTH-1 downto 0);
|
outI : out std_logic_vector(WIDTH-1 downto 0);
|
outI : out std_logic_vector(WIDTH-1 downto 0);
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
sel : in std_logic);
|
sel : in std_logic);
|
end component;
|
end component;
|
|
|
component conj
|
component conj
|
generic (
|
generic (
|
width : natural);
|
width : natural);
|
port (
|
port (
|
|
|
inR : in std_logic_vector(WIDTH-1 downto 0);
|
inR : in std_logic_vector(WIDTH-1 downto 0);
|
inI : in std_logic_vector(WIDTH-1 downto 0);
|
inI : in std_logic_vector(WIDTH-1 downto 0);
|
outR : out std_logic_vector(WIDTH-1 downto 0);
|
outR : out std_logic_vector(WIDTH-1 downto 0);
|
outI : out std_logic_vector(WIDTH-1 downto 0);
|
outI : out std_logic_vector(WIDTH-1 downto 0);
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
conj : in std_logic);
|
conj : in std_logic);
|
end component;
|
end component;
|
|
|
component ram
|
component ram
|
generic (
|
generic (
|
width : natural;
|
width : natural;
|
depth : natural;
|
depth : natural;
|
Addr_width : natural);
|
Addr_width : natural);
|
port (
|
port (
|
clkin : in std_logic;
|
clkin : in std_logic;
|
wen : in std_logic;
|
wen : in std_logic;
|
addrin : in std_logic_vector(Addr_width-1 downto 0);
|
addrin : in std_logic_vector(Addr_width-1 downto 0);
|
dinR : in std_logic_vector(width-1 downto 0);
|
dinR : in std_logic_vector(width-1 downto 0);
|
dinI : in std_logic_vector(width-1 downto 0);
|
dinI : in std_logic_vector(width-1 downto 0);
|
clkout : in std_logic;
|
clkout : in std_logic;
|
addrout : in std_logic_vector(Addr_width-1 downto 0);
|
addrout : in std_logic_vector(Addr_width-1 downto 0);
|
doutR : out std_logic_vector(width-1 downto 0);
|
doutR : out std_logic_vector(width-1 downto 0);
|
doutI : out std_logic_vector(width-1 downto 0));
|
doutI : out std_logic_vector(width-1 downto 0));
|
end component;
|
end component;
|
|
|
component cfft4
|
component cfft4
|
generic (
|
generic (
|
width : natural
|
width : natural
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
start : in std_logic;
|
start : in std_logic;
|
invert : in std_logic;
|
invert : in std_logic;
|
I : in std_logic_vector(WIDTH-1 downto 0);
|
I : in std_logic_vector(WIDTH-1 downto 0);
|
Q : in std_logic_vector(WIDTH-1 downto 0);
|
Q : in std_logic_vector(WIDTH-1 downto 0);
|
Iout : out std_logic_vector(WIDTH+1 downto 0);
|
Iout : out std_logic_vector(WIDTH+1 downto 0);
|
Qout : out std_logic_vector(WIDTH+1 downto 0)
|
Qout : out std_logic_vector(WIDTH+1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component div4limit
|
component div4limit
|
generic (
|
generic (
|
WIDTH : natural
|
WIDTH : natural
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
D : in std_logic_vector(WIDTH+3 downto 0);
|
D : in std_logic_vector(WIDTH+3 downto 0);
|
Q : out std_logic_vector(WIDTH-1 downto 0)
|
Q : out std_logic_vector(WIDTH-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component mulfactor
|
component mulfactor
|
generic (
|
generic (
|
WIDTH : natural;
|
WIDTH : natural;
|
STAGE : natural
|
STAGE : natural
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
angle : in signed(2*STAGE-1 downto 0);
|
angle : in signed(2*STAGE-1 downto 0);
|
I : in signed(WIDTH+1 downto 0);
|
I : in signed(WIDTH+1 downto 0);
|
Q : in signed(WIDTH+1 downto 0);
|
Q : in signed(WIDTH+1 downto 0);
|
Iout : out signed(WIDTH+3 downto 0);
|
Iout : out signed(WIDTH+3 downto 0);
|
Qout : out signed(WIDTH+3 downto 0)
|
Qout : out signed(WIDTH+3 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component rofactor
|
component rofactor
|
generic (
|
generic (
|
POINT : natural;
|
POINT : natural;
|
STAGE : natural
|
STAGE : natural
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
start : in std_logic;
|
start : in std_logic;
|
invert : in std_logic;
|
invert : in std_logic;
|
angle : out std_logic_vector(2*STAGE-1 downto 0)
|
angle : out std_logic_vector(2*STAGE-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
component blockdram
|
component blockdram
|
generic (
|
generic (
|
depth : natural;
|
depth : natural;
|
Dwidth : natural;
|
Dwidth : natural;
|
Awidth : natural);
|
Awidth : natural);
|
port (
|
port (
|
clkin : in std_logic;
|
clkin : in std_logic;
|
wen : in std_logic;
|
wen : in std_logic;
|
addrin : in std_logic_vector(Awidth-1 downto 0);
|
addrin : in std_logic_vector(Awidth-1 downto 0);
|
din : in std_logic_vector(Dwidth-1 downto 0);
|
din : in std_logic_vector(Dwidth-1 downto 0);
|
clkout : in std_logic;
|
clkout : in std_logic;
|
addrout : in std_logic_vector(Awidth-1 downto 0);
|
addrout : in std_logic_vector(Awidth-1 downto 0);
|
dout : out std_logic_vector(Dwidth-1 downto 0));
|
dout : out std_logic_vector(Dwidth-1 downto 0));
|
end component;
|
end component;
|
|
|
signal MuxInRa, MuxInIa, MuxInRb, MuxInIb : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal MuxInRa, MuxInIa, MuxInRb, MuxInIb : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal conjInR, conjInI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal conjInR, conjInI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal cfft4InR, cfft4InI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal cfft4InR, cfft4InI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal cfft4outR, cfft4outI : std_logic_vector(WIDTH+1 downto 0) := (others => '0');
|
signal cfft4outR, cfft4outI : std_logic_vector(WIDTH+1 downto 0) := (others => '0');
|
signal MulOutR, MulOutI : signed(WIDTH+3 downto 0) := (others => '0');
|
signal MulOutR, MulOutI : signed(WIDTH+3 downto 0) := (others => '0');
|
signal fftR, fftI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal fftR, fftI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
|
signal angle : std_logic_vector(2*STAGE-1 downto 0 ) := ( others => '0');
|
signal angle : std_logic_vector(2*STAGE-1 downto 0 ) := ( others => '0');
|
signal invert : std_logic;
|
signal invert : std_logic;
|
|
|
begin
|
begin
|
|
|
TX:if Tx_nRx = 1 generate
|
TX:if Tx_nRx = 1 generate
|
RamIn : ram
|
RamIn : ram
|
generic map (
|
generic map (
|
width => WIDTH,
|
width => WIDTH,
|
depth => POINT,
|
depth => POINT,
|
Addr_width => 2*STAGE)
|
Addr_width => 2*STAGE)
|
port map (
|
port map (
|
clkin => ClkIn,
|
clkin => ClkIn,
|
wen => wen_in,
|
wen => wen_in,
|
addrin => addrin_in,
|
addrin => addrin_in,
|
dinR => Iin,
|
dinR => Iin,
|
dinI => Qin,
|
dinI => Qin,
|
clkout => ClkIn,
|
clkout => ClkIn,
|
addrout => addrout_in,
|
addrout => addrout_in,
|
doutR => MuxInRa,
|
doutR => MuxInRa,
|
doutI => MuxInIa);
|
doutI => MuxInIa);
|
|
|
RamOut : ram
|
RamOut : ram
|
generic map (
|
generic map (
|
width => WIDTH+2,
|
width => WIDTH+2,
|
depth => POINT,
|
depth => POINT,
|
Addr_width => 2*STAGE)
|
Addr_width => 2*STAGE)
|
port map (
|
port map (
|
clkin => ClkIn,
|
clkin => ClkIn,
|
wen => wen_out,
|
wen => wen_out,
|
addrin => addrin_out,
|
addrin => addrin_out,
|
dinR => cfft4outR,
|
dinR => cfft4outR,
|
dinI => cfft4outR,
|
dinI => cfft4outR,
|
clkout => ClkIn,
|
clkout => ClkIn,
|
addrout => addrout_out,
|
addrout => addrout_out,
|
doutR => Iout,
|
doutR => Iout,
|
doutI => open);
|
doutI => open);
|
end generate;
|
end generate;
|
|
|
RX:if Tx_nRx = 0 generate
|
RX:if Tx_nRx = 0 generate
|
RamIn : ram
|
RamIn : ram
|
generic map (
|
generic map (
|
width => WIDTH,
|
width => WIDTH,
|
depth => 2*POINT,
|
depth => 2*POINT,
|
Addr_width => 2*STAGE+1)
|
Addr_width => 2*STAGE+1)
|
port map (
|
port map (
|
clkin => ClkIn,
|
clkin => ClkIn,
|
wen => wen_in,
|
wen => wen_in,
|
addrin => addrin_in,
|
addrin => addrin_in,
|
dinR => Iin,
|
dinR => Iin,
|
dinI => Qin,
|
dinI => Qin,
|
clkout => ClkIn,
|
clkout => ClkIn,
|
addrout => addrout_in,
|
addrout => addrout_in,
|
doutR => MuxInRa,
|
doutR => MuxInRa,
|
doutI => open);
|
doutI => open);
|
|
|
MuxinIa <= (others => '0');
|
MuxinIa <= (others => '0');
|
|
|
RamOut : ram
|
RamOut : ram
|
generic map (
|
generic map (
|
width => WIDTH+2,
|
width => WIDTH+2,
|
depth => POINT,
|
depth => POINT,
|
Addr_width => 2*STAGE)
|
Addr_width => 2*STAGE)
|
port map (
|
port map (
|
clkin => ClkIn,
|
clkin => ClkIn,
|
wen => wen_out,
|
wen => wen_out,
|
addrin => addrin_out,
|
addrin => addrin_out,
|
dinR => cfft4outR,
|
dinR => cfft4outR,
|
dinI => cfft4outR,
|
dinI => cfft4outR,
|
clkout => ClkIn,
|
clkout => ClkIn,
|
addrout => addrout_out,
|
addrout => addrout_out,
|
doutR => Iout,
|
doutR => Iout,
|
doutI => Qout);
|
doutI => Qout);
|
|
|
end generate;
|
end generate;
|
|
|
|
|
RamProc : ram
|
RamProc : ram
|
generic map (
|
generic map (
|
width => WIDTH,
|
width => WIDTH,
|
depth => POINT,
|
depth => POINT,
|
Addr_width => 2*STAGE)
|
Addr_width => 2*STAGE)
|
port map (
|
port map (
|
clkin => ClkIn,
|
clkin => ClkIn,
|
wen => wen_proc,
|
wen => wen_proc,
|
addrin => addrin_proc,
|
addrin => addrin_proc,
|
dinR => fftR,
|
dinR => fftR,
|
dinI => fftI,
|
dinI => fftI,
|
clkout => ClkIn,
|
clkout => ClkIn,
|
addrout => addrout_proc,
|
addrout => addrout_proc,
|
doutR => MuxInRb,
|
doutR => MuxInRb,
|
doutI => MuxInIb);
|
doutI => MuxInIb);
|
|
|
mux_1 : mux
|
mux_1 : mux
|
generic map (
|
generic map (
|
width => width)
|
width => width)
|
port map (
|
port map (
|
inRa => MuxInRa,
|
inRa => MuxInRa,
|
inIa => MuxInIa,
|
inIa => MuxInIa,
|
inRb => MuxInRb,
|
inRb => MuxInRb,
|
inIb => MuxInIb,
|
inIb => MuxInIb,
|
outR => conjInR,
|
outR => conjInR,
|
outI => conjInI,
|
outI => conjInI,
|
clk => clkin,
|
clk => clkin,
|
sel => sel_mux);
|
sel => sel_mux);
|
|
|
invert <= (inv and conv_std_logic_vector(Tx_nRx,1)(0));
|
invert <= (inv and conv_std_logic_vector(Tx_nRx,1)(0));
|
|
|
conj_1: conj
|
conj_1: conj
|
generic map (
|
generic map (
|
width => width)
|
width => width)
|
port map (
|
port map (
|
|
|
inR => conjInR,
|
inR => conjInR,
|
inI => conjInI,
|
inI => conjInI,
|
outR => cfft4InR,
|
outR => cfft4InR,
|
outI => cfft4InI,
|
outI => cfft4InI,
|
clk => Clkin,
|
clk => Clkin,
|
conj => invert);
|
conj => invert);
|
|
|
acfft4 : cfft4
|
acfft4 : cfft4
|
generic map (
|
generic map (
|
WIDTH => WIDTH
|
WIDTH => WIDTH
|
)
|
)
|
port map (
|
port map (
|
clk => ClkIn,
|
clk => ClkIn,
|
rst => rst,
|
rst => rst,
|
start => cfft4start,
|
start => cfft4start,
|
invert => conv_std_logic_vector(Tx_nRx,1)(0),
|
invert => conv_std_logic_vector(Tx_nRx,1)(0),
|
I => cfft4InR,
|
I => cfft4InR,
|
Q => cfft4InI,
|
Q => cfft4InI,
|
Iout => cfft4outR,
|
Iout => cfft4outR,
|
Qout => cfft4outI
|
Qout => cfft4outI
|
);
|
);
|
|
|
amulfactor : mulfactor
|
amulfactor : mulfactor
|
generic map (
|
generic map (
|
WIDTH => WIDTH,
|
WIDTH => WIDTH,
|
STAGE => STAGE
|
STAGE => STAGE
|
)
|
)
|
port map (
|
port map (
|
clk => ClkIn,
|
clk => ClkIn,
|
rst => rst,
|
rst => rst,
|
angle => signed(angle),
|
angle => signed(angle),
|
I => signed(cfft4outR),
|
I => signed(cfft4outR),
|
Q => signed(cfft4outI),
|
Q => signed(cfft4outI),
|
Iout => MulOutR,
|
Iout => MulOutR,
|
Qout => MulOutI
|
Qout => MulOutI
|
);
|
);
|
|
|
arofactor : rofactor
|
arofactor : rofactor
|
generic map (
|
generic map (
|
POINT => POINT,
|
POINT => POINT,
|
STAGE => STAGE
|
STAGE => STAGE
|
)
|
)
|
port map (
|
port map (
|
clk => ClkIn,
|
clk => ClkIn,
|
rst => rst,
|
rst => rst,
|
start => factorstart,
|
start => factorstart,
|
invert => conv_std_logic_vector(Tx_nRx,1)(0), -- IFFT
|
invert => conv_std_logic_vector(Tx_nRx,1)(0), -- IFFT
|
angle => angle
|
angle => angle
|
);
|
);
|
|
|
Rlimit : div4limit
|
Rlimit : div4limit
|
generic map (
|
generic map (
|
WIDTH => WIDTH
|
WIDTH => WIDTH
|
)
|
)
|
port map (
|
port map (
|
clk => ClkIn,
|
clk => ClkIn,
|
D => std_logic_vector(MulOutR),
|
D => std_logic_vector(MulOutR),
|
Q => fftR
|
Q => fftR
|
);
|
);
|
Ilimit : div4limit
|
Ilimit : div4limit
|
generic map (
|
generic map (
|
WIDTH => WIDTH
|
WIDTH => WIDTH
|
)
|
)
|
port map (
|
port map (
|
clk => ClkIn,
|
clk => ClkIn,
|
D => std_logic_vector(MulOutI),
|
D => std_logic_vector(MulOutI),
|
Q => fftI
|
Q => fftI
|
);
|
);
|
|
|
end cfft;
|
end cfft;
|
|
|
