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---------------------------------------------------------------------------------------------------
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--
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--
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-- Title : cfft4
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-- Title : cfft4
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-- Design : cfft
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-- Design : cfft
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-- Author : ZHAO Ming
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-- Author : ZHAO Ming
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-- email : sradio@opencores.org
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-- email : sradio@opencores.org
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- File : cfft4.vhd
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-- File : cfft4.vhd
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-- Generated : Wed Oct 2 15:49:06 2002
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-- Generated : Wed Oct 2 15:49:06 2002
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Description : 4 point fft
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-- Description : 4 point fft
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Revisions : 0
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-- Revisions : 0
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-- Revision Number : 1
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-- Revision Number : 1
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-- Version : 1.1.0
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-- Version : 1.1.0
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-- Date : Oct 17 2002
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-- Date : Oct 17 2002
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-- Modifier : ZHAO Ming
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-- Modifier : ZHAO Ming
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-- Desccription : Data width configurable
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-- Desccription : Data width configurable
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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entity cfft4 is
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entity cfft4 is
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generic (
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generic (
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WIDTH : Natural
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WIDTH : Natural
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);
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);
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port(
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port(
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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start : in STD_LOGIC;
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start : in STD_LOGIC;
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invert : in std_logic;
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invert : in std_logic;
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I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
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Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
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Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
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Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
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);
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);
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end cfft4;
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end cfft4;
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architecture cfft4 of cfft4 is
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architecture cfft4 of cfft4 is
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type RegAtype is array (3 downto 0) of std_logic_vector(WIDTH-1 downto 0);
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type RegAtype is array (3 downto 0) of std_logic_vector(WIDTH-1 downto 0);
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type RegBtype is array (3 downto 0) of std_logic_vector(WIDTH downto 0);
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type RegBtype is array (3 downto 0) of std_logic_vector(WIDTH downto 0);
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signal counter : std_logic_vector( 1 downto 0 ):="00";
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signal counter : std_logic_vector( 1 downto 0 ):="00";
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signal RegAI,RegAQ : RegAtype;
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signal RegAI,RegAQ : RegAtype;
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signal RegBI,RegBQ : RegBtype;
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signal RegBI,RegBQ : RegBtype;
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begin
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begin
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count:process( clk,rst )
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count:process( clk,rst )
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begin
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begin
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if rst='1' then
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if rst='1' then
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counter<="00";
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counter<="00";
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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if start='1' then
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if start='1' then
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counter<="00";
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counter<="00";
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else
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else
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counter<=counter+1;
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counter<=counter+1;
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end if;
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end if;
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end if;
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end if;
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end process count;
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end process count;
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
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--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
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--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
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--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
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--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
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--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
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--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
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--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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calculate:process( clk )
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calculate:process( clk )
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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case counter is
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case counter is
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--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
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--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)--
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when "00" =>
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when "00" =>
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RegAI(0)<=I;
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RegAI(0)<=I;
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RegAQ(0)<=Q;
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RegAQ(0)<=Q;
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RegBI(1)<=SXT(RegAI(0),WIDTH+1)-SXT(RegAI(2),WIDTH+1);
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RegBI(1)<=SXT(RegAI(0),WIDTH+1)-SXT(RegAI(2),WIDTH+1);
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RegBQ(1)<=SXT(RegAQ(0),WIDTH+1)-SXT(RegAQ(2),WIDTH+1);
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RegBQ(1)<=SXT(RegAQ(0),WIDTH+1)-SXT(RegAQ(2),WIDTH+1);
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RegBI(2)<=SXT(RegAI(1),WIDTH+1)+SXT(RegAI(3),WIDTH+1);
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RegBI(2)<=SXT(RegAI(1),WIDTH+1)+SXT(RegAI(3),WIDTH+1);
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RegBQ(2)<=SXT(RegAQ(1),WIDTH+1)+SXT(RegAQ(3),WIDTH+1);
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RegBQ(2)<=SXT(RegAQ(1),WIDTH+1)+SXT(RegAQ(3),WIDTH+1);
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Iout<=SXT(RegBI(1),WIDTH+2)-SXT(RegBI(3),WIDTH+2);
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Iout<=SXT(RegBI(1),WIDTH+2)-SXT(RegBI(3),WIDTH+2);
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Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2);
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Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2);
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--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
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--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)--
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when "01" =>
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when "01" =>
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RegAI(1)<=I;
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RegAI(1)<=I;
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RegAQ(1)<=Q;
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RegAQ(1)<=Q;
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if invert='0' then
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if invert='0' then
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-- for fft *(-j)
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-- for fft *(-j)
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RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
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RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1);
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RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
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RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1);
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else
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else
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-- for fft *(j)
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-- for fft *(j)
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RegBI(3)<=SXT(RegAQ(3),WIDTH+1)-SXT(RegAQ(1),WIDTH+1);
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RegBI(3)<=SXT(RegAQ(3),WIDTH+1)-SXT(RegAQ(1),WIDTH+1);
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RegBQ(3)<=SXT(RegAI(1),WIDTH+1)-SXT(RegAI(3),WIDTH+1);
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RegBQ(3)<=SXT(RegAI(1),WIDTH+1)-SXT(RegAI(3),WIDTH+1);
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end if;
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end if;
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Iout<=SXT(RegBI(0),WIDTH+2)+SXT(RegBI(2),WIDTH+2);
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Iout<=SXT(RegBI(0),WIDTH+2)+SXT(RegBI(2),WIDTH+2);
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Qout<=SXT(RegBQ(0),WIDTH+2)+SXT(RegBQ(2),WIDTH+2);
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Qout<=SXT(RegBQ(0),WIDTH+2)+SXT(RegBQ(2),WIDTH+2);
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--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
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--2 rA(2)<=A2 B1<=rB(1)+rB(3)--
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when "10" =>
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when "10" =>
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RegAI(2)<=I;
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RegAI(2)<=I;
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RegAQ(2)<=Q;
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RegAQ(2)<=Q;
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Iout<=SXT(RegBI(1),WIDTH+2)+SXT(RegBI(3),WIDTH+2);
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Iout<=SXT(RegBI(1),WIDTH+2)+SXT(RegBI(3),WIDTH+2);
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Qout<=SXT(RegBQ(1),WIDTH+2)+SXT(RegBQ(3),WIDTH+2);
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Qout<=SXT(RegBQ(1),WIDTH+2)+SXT(RegBQ(3),WIDTH+2);
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--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
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--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)--
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when "11" =>
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when "11" =>
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RegAI(3)<=I;
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RegAI(3)<=I;
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RegAQ(3)<=Q;
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RegAQ(3)<=Q;
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RegBI(0)<=SXT(RegAI(0),WIDTH+1)+SXT(RegAI(2),WIDTH+1);
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RegBI(0)<=SXT(RegAI(0),WIDTH+1)+SXT(RegAI(2),WIDTH+1);
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RegBQ(0)<=SXT(RegAQ(0),WIDTH+1)+SXT(RegAQ(2),WIDTH+1);
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RegBQ(0)<=SXT(RegAQ(0),WIDTH+1)+SXT(RegAQ(2),WIDTH+1);
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Iout<=SXT(RegBI(0),WIDTH+2)-SXT(RegBI(2),WIDTH+2);
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Iout<=SXT(RegBI(0),WIDTH+2)-SXT(RegBI(2),WIDTH+2);
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Qout<=SXT(RegBQ(0),WIDTH+2)-SXT(RegBQ(2),WIDTH+2);
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Qout<=SXT(RegBQ(0),WIDTH+2)-SXT(RegBQ(2),WIDTH+2);
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end process calculate;
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end process calculate;
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end cfft4;
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end cfft4;
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