library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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entity cfft_control is
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entity cfft_control is
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generic (
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generic (
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Tx_nRx : natural := 0; -- tx = 1, rx = 0
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Tx_nRx : natural := 0; -- tx = 1, rx = 0
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stage : natural := 3);
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stage : natural := 3);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mem_ready : in std_logic;
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mem_ready : in std_logic;
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sel_mux : out std_logic;
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sel_mux : out std_logic;
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factorstart : out std_logic;
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factorstart : out std_logic;
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cfft4start : out std_logic;
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cfft4start : out std_logic;
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inv : out std_logic;
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inv : out std_logic;
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Output_enable : out std_logic;
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Output_enable : out std_logic;
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bank0_busy : out std_logic;
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bank0_busy : out std_logic;
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bank1_busy : out std_logic;
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bank1_busy : out std_logic;
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mem_block : out std_logic;
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mem_block : out std_logic;
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addrout_in : out std_logic_vector(stage*2-Tx_nRx downto 0);
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addrout_in : out std_logic_vector(stage*2-Tx_nRx downto 0);
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wen_proc : out std_logic;
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wen_proc : out std_logic;
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addrin_proc : out std_logic_vector(stage*2-1 downto 0);
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addrin_proc : out std_logic_vector(stage*2-1 downto 0);
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addrout_proc : out std_logic_vector(stage*2-1 downto 0);
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addrout_proc : out std_logic_vector(stage*2-1 downto 0);
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wen_out : out std_logic;
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wen_out : out std_logic;
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addrin_out : out std_logic_vector(stage*2-1 downto 0));
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addrin_out : out std_logic_vector(stage*2-1 downto 0));
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end cfft_control;
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end cfft_control;
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architecture cfft_control of cfft_control is
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architecture cfft_control of cfft_control is
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component counter
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component counter
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generic (
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generic (
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stage : natural);
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stage : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mem_ready : in std_logic;
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mem_ready : in std_logic;
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mem_bk : out std_logic;
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mem_bk : out std_logic;
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count : out std_logic_vector(2*stage+2 downto 0));
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count : out std_logic_vector(2*stage+2 downto 0));
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end component;
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end component;
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component ram_control
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component ram_control
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generic (
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generic (
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Tx_nRX : natural;
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Tx_nRX : natural;
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stage : natural);
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stage : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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mem_bk : in std_logic;
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mem_bk : in std_logic;
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addrout_in : out std_logic_vector(stage*2-Tx_nRX downto 0);
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addrout_in : out std_logic_vector(stage*2-Tx_nRX downto 0);
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wen_proc : out std_logic;
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wen_proc : out std_logic;
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addrin_proc : out std_logic_vector(stage*2-1 downto 0);
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addrin_proc : out std_logic_vector(stage*2-1 downto 0);
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addrout_proc : out std_logic_vector(stage*2-1 downto 0);
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addrout_proc : out std_logic_vector(stage*2-1 downto 0);
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wen_out : out std_logic;
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wen_out : out std_logic;
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addrin_out : out std_logic_vector(stage*2-1 downto 0));
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addrin_out : out std_logic_vector(stage*2-1 downto 0));
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end component;
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end component;
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component mux_control
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component mux_control
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generic (
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generic (
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stage : natural);
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stage : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Gen_state : in std_logic_vector(8 downto 0);
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Gen_state : in std_logic_vector(8 downto 0);
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sel_mux : out std_logic);
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sel_mux : out std_logic);
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end component;
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end component;
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component starts
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component starts
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generic (
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generic (
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stage : natural);
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stage : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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factorstart : out std_logic;
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factorstart : out std_logic;
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cfft4start : out std_logic);
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cfft4start : out std_logic);
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end component;
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end component;
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component inv_control
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component inv_control
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generic (
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generic (
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stage : natural);
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stage : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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inv : out std_logic);
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inv : out std_logic);
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end component;
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end component;
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component io_control
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component io_control
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generic (
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generic (
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stage : natural);
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stage : natural);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mem_bk : in std_logic;
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mem_bk : in std_logic;
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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bank0_busy : out std_logic;
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bank0_busy : out std_logic;
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bank1_busy : out std_logic;
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bank1_busy : out std_logic;
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Output_enable : out std_logic);
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Output_enable : out std_logic);
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end component;
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end component;
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signal count : std_logic_vector(2*stage+2 downto 0);
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signal count : std_logic_vector(2*stage+2 downto 0);
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signal mem_bk : std_logic;
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signal mem_bk : std_logic;
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begin
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begin
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mem_block <= mem_bk;
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mem_block <= mem_bk;
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counter_1 : counter
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counter_1 : counter
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generic map (
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generic map (
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stage => stage)
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stage => stage)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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mem_ready => mem_ready,
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mem_ready => mem_ready,
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mem_bk => mem_bk,
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mem_bk => mem_bk,
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count => count);
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count => count);
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ram_control_1 : ram_control
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ram_control_1 : ram_control
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generic map (
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generic map (
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Tx_nRX => Tx_nRX,
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Tx_nRX => Tx_nRX,
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stage => stage)
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stage => stage)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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Gen_state => count,
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Gen_state => count,
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mem_bk => mem_bk,
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mem_bk => mem_bk,
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addrout_in => addrout_in,
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addrout_in => addrout_in,
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wen_proc => wen_proc,
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wen_proc => wen_proc,
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addrin_proc => addrin_proc,
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addrin_proc => addrin_proc,
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addrout_proc => addrout_proc,
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addrout_proc => addrout_proc,
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wen_out => wen_out,
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wen_out => wen_out,
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addrin_out => addrin_out);
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addrin_out => addrin_out);
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mux_control_1 : mux_control
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mux_control_1 : mux_control
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generic map (
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generic map (
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stage => stage)
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stage => stage)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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Gen_state => count,
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Gen_state => count,
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sel_mux => sel_mux);
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sel_mux => sel_mux);
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starts_1 : starts
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starts_1 : starts
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generic map (
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generic map (
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stage => stage)
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stage => stage)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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Gen_state => count,
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Gen_state => count,
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factorstart => factorstart,
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factorstart => factorstart,
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cfft4start => cfft4start);
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cfft4start => cfft4start);
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TX_inv : if Tx_nRx = 1 generate
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TX_inv : if Tx_nRx = 1 generate
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inv_control_1 : inv_control
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inv_control_1 : inv_control
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generic map (
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generic map (
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stage => stage)
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stage => stage)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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Gen_state => count,
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Gen_state => count,
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inv => inv);
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inv => inv);
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end generate;
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end generate;
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io_control_1 : io_control
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io_control_1 : io_control
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generic map (
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generic map (
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stage => stage)
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stage => stage)
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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mem_bk => mem_bk,
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mem_bk => mem_bk,
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Gen_state => count,
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Gen_state => count,
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bank0_busy => bank0_busy,
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bank0_busy => bank0_busy,
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bank1_busy => bank1_busy,
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bank1_busy => bank1_busy,
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Output_enable => Output_enable);
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Output_enable => Output_enable);
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end cfft_control;
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end cfft_control;
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