-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Conj.vhd
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-- Title : Conj.vhd
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : invsignal.vhd
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-- File : invsignal.vhd
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-- Author :
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-- Author :
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-- Company :
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-- Company :
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-- Created : 2003-11-28
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-- Created : 2003-11-28
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-- Last update: 2003-12-05
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-- Last update: 2003-12-05
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-- Platform :
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-- Platform :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description: Faz o conjugado do sinal de entrada
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-- Description: Faz o conjugado do sinal de entrada
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (c) 2003
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-- Copyright (c) 2003
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Date Version Author Description
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-- Date Version Author Description
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-- 2003-11-28 1.0 tmsiqueira Created
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-- 2003-11-28 1.0 tmsiqueira Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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use IEEE.STD_LOGIC_SIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity conj is
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entity conj is
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generic (
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generic (
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width : natural);
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width : natural);
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port (
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port (
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inR : in std_logic_vector(WIDTH-1 downto 0);
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inR : in std_logic_vector(WIDTH-1 downto 0);
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inI : in std_logic_vector(WIDTH-1 downto 0);
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inI : in std_logic_vector(WIDTH-1 downto 0);
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outR : out std_logic_vector(WIDTH-1 downto 0);
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outR : out std_logic_vector(WIDTH-1 downto 0);
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outI : out std_logic_vector(WIDTH-1 downto 0);
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outI : out std_logic_vector(WIDTH-1 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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conj : in std_logic);
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conj : in std_logic);
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end conj;
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end conj;
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architecture conj of conj is
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architecture conj of conj is
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begin
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begin
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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case conj is
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case conj is
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when '0' =>
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when '0' =>
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outR <= inR;
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outR <= inR;
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outI <= inI;
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outI <= inI;
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when '1' =>
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when '1' =>
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outR <= inR;
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outR <= inR;
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outI <= 0-inI;
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outI <= 0-inI;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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