library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity io_control is
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entity io_control is
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generic (
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generic (
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stage : natural:=3);
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stage : natural:=3);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mem_bk : in std_logic;
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mem_bk : in std_logic;
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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Gen_state : in std_logic_vector(2*stage+2 downto 0);
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bank0_busy : out std_logic;
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bank0_busy : out std_logic;
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bank1_busy : out std_logic;
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bank1_busy : out std_logic;
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Output_enable: out std_logic);
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Output_enable: out std_logic);
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end io_control;
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end io_control;
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architecture io_control of io_control is
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architecture io_control of io_control is
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alias state: std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
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alias state: std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
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alias counter: std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
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alias counter: std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
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begin
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begin
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Outen:process (clk, rst)
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Outen:process (clk, rst)
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begin -- process
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begin -- process
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if rst = '1' then -- asynchronous reset (active low)
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if rst = '1' then -- asynchronous reset (active low)
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Output_enable <= '0';
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Output_enable <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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elsif clk'event and clk = '1' then -- rising clock edge
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if unsigned(state)=stage-1 and unsigned(counter)=55 then
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if unsigned(state)=stage-1 and unsigned(counter)=55 then
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Output_enable <= '1';
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Output_enable <= '1';
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else
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else
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Output_enable <= '0';
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Output_enable <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Bank_busy:process(clk, rst)
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Bank_busy:process(clk, rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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bank0_busy <= '0';
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bank0_busy <= '0';
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bank1_busy <= '0';
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bank1_busy <= '0';
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elsif clk'event and clk = '1' then
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elsif clk'event and clk = '1' then
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if unsigned(state)=0 then
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if unsigned(state)=0 then
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if mem_bk = '0' then
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if mem_bk = '0' then
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bank0_busy <= '1';
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bank0_busy <= '1';
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else
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else
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bank1_busy <= '1';
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bank1_busy <= '1';
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end if;
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end if;
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else
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else
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bank0_busy <= '0';
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bank0_busy <= '0';
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bank1_busy <= '0';
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bank1_busy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end io_control;
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end io_control;
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