library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity modem is
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entity modem is
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port ( clk : in std_logic;
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port ( clk : in std_logic;
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rsti : in std_logic;
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rsti : in std_logic;
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rxserial : in std_logic;
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rxserial : in std_logic;
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txserial : out std_logic;
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txserial : out std_logic;
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pmem_ready : out std_logic;
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pmem_ready : out std_logic;
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pIin : out std_logic_vector(13 downto 0);
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pIin : out std_logic_vector(13 downto 0);
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pmem_block : out std_logic;
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pmem_block : out std_logic;
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pOutput_enable : out std_logic;
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pOutput_enable : out std_logic;
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pwen : out std_logic;
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pwen : out std_logic;
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paddress_read : out std_logic_vector(5 downto 0);
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paddress_read : out std_logic_vector(5 downto 0);
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paddress_write : out std_logic_vector(6 downto 0);
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paddress_write : out std_logic_vector(6 downto 0);
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Iout_rx : out std_logic_vector(13 downto 0);
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Iout_rx : out std_logic_vector(13 downto 0);
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Qout_rx : out std_logic_vector(13 downto 0);
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Qout_rx : out std_logic_vector(13 downto 0);
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Output_enable_rx : out std_logic;
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Output_enable_rx : out std_logic;
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addrout_out_rx : out std_logic_vector(5 downto 0);
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addrout_out_rx : out std_logic_vector(5 downto 0);
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mem_block_tx : out std_logic;
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mem_block_tx : out std_logic;
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mem_ready_tx : out std_logic;
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mem_ready_tx : out std_logic;
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wen_tx : out std_logic;
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wen_tx : out std_logic;
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address_tx : out std_logic_vector (5 downto 0);
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address_tx : out std_logic_vector (5 downto 0);
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i_tx : out std_logic_vector(11 downto 0);
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i_tx : out std_logic_vector(11 downto 0);
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q_tx : out std_logic_vector(11 downto 0)
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q_tx : out std_logic_vector(11 downto 0)
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);
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);
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end modem;
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end modem;
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architecture modem of modem is
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architecture modem of modem is
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component txmodem
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component txmodem
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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serial : in std_logic;
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serial : in std_logic;
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Iout : out std_logic_vector(13 downto 0);
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Iout : out std_logic_vector(13 downto 0);
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Output_enable : out std_logic;
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Output_enable : out std_logic;
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addrout_out : in std_logic_vector(5 downto 0)
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addrout_out : in std_logic_vector(5 downto 0)
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);
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);
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end component;
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end component;
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component txrx
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component txrx
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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Output_enable : in std_logic;
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Output_enable : in std_logic;
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mem_block : in std_logic;
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mem_block : in std_logic;
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mem_ready : out std_logic;
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mem_ready : out std_logic;
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wen : out std_logic;
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wen : out std_logic;
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address_read : out std_logic_vector(5 downto 0);
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address_read : out std_logic_vector(5 downto 0);
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address_write: out std_logic_vector(6 downto 0)
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address_write: out std_logic_vector(6 downto 0)
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);
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);
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end component;
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end component;
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component rxmodem
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component rxmodem
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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mem_ready : in std_logic;
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mem_ready : in std_logic;
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Iin : in std_logic_vector(11 downto 0);
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Iin : in std_logic_vector(11 downto 0);
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mem_block : out std_logic;
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mem_block : out std_logic;
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wen : in std_logic;
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wen : in std_logic;
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addrin_in : in std_logic_vector(6 downto 0);
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addrin_in : in std_logic_vector(6 downto 0);
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txserial : out std_logic
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txserial : out std_logic
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);
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);
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end component;
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end component;
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component BUFGP
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component BUFGP
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port (I: in std_logic; O: out std_logic);
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port (I: in std_logic; O: out std_logic);
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end component;
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end component;
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signal rst: std_logic;
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signal rst: std_logic;
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signal mem_ready : std_logic;
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signal mem_ready : std_logic;
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signal Iin : std_logic_vector(13 downto 0);
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signal Iin : std_logic_vector(13 downto 0);
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signal mem_block : std_logic;
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signal mem_block : std_logic;
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signal Output_enable : std_logic;
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signal Output_enable : std_logic;
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signal wen : std_logic;
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signal wen : std_logic;
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signal address_read : std_logic_vector(5 downto 0);
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signal address_read : std_logic_vector(5 downto 0);
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signal address_write : std_logic_vector(6 downto 0);
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signal address_write : std_logic_vector(6 downto 0);
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begin
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begin
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U1: BUFGP port map (I => rsti, O => rst);
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U1: BUFGP port map (I => rsti, O => rst);
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txmodem_1 : txmodem
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txmodem_1 : txmodem
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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serial => rxserial,
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serial => rxserial,
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Iout => Iin,
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Iout => Iin,
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Output_enable => Output_enable,
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Output_enable => Output_enable,
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addrout_out => address_read
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addrout_out => address_read
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);
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);
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txrx_1 : txrx
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txrx_1 : txrx
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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Output_enable => Output_enable,
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Output_enable => Output_enable,
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mem_block => mem_block,
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mem_block => mem_block,
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mem_ready => mem_ready,
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mem_ready => mem_ready,
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wen => wen,
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wen => wen,
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address_read => address_read,
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address_read => address_read,
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address_write => address_write);
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address_write => address_write);
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rxmodem_1 : rxmodem
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rxmodem_1 : rxmodem
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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mem_ready => mem_ready,
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mem_ready => mem_ready,
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Iin => Iin(13 downto 2),
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Iin => Iin(13 downto 2),
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mem_block => mem_block,
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mem_block => mem_block,
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wen => wen,
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wen => wen,
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addrin_in => address_write,
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addrin_in => address_write,
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txserial => txserial
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txserial => txserial
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);
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);
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end modem;
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end modem;
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