---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Title : mulfactor
|
-- Title : mulfactor
|
-- Design : cfft
|
-- Design : cfft
|
-- Author : ZHAO Ming
|
-- Author : ZHAO Ming
|
-- email : sradio@opencores.org
|
-- email : sradio@opencores.org
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- File : mulfactor.vhd
|
-- File : mulfactor.vhd
|
-- Generated : Thu Oct 3 00:37:40 2002
|
-- Generated : Thu Oct 3 00:37:40 2002
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Description : 360 degee complex rotation
|
-- Description : 360 degee complex rotation
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Revisions : 0
|
-- Revisions : 0
|
-- Revision Number : 1
|
-- Revision Number : 1
|
-- Version : 1.1.0
|
-- Version : 1.1.0
|
-- Date : Oct 17 2002
|
-- Date : Oct 17 2002
|
-- Modifier : ZHAO Ming
|
-- Modifier : ZHAO Ming
|
-- Desccription : Data width configurable
|
-- Desccription : Data width configurable
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
--
|
--
|
-- Revisions : 0
|
-- Revisions : 0
|
-- Revision Number : 2
|
-- Revision Number : 2
|
-- Version : 1.2.1
|
-- Version : 1.2.1
|
-- Date : Oct 18 2002
|
-- Date : Oct 18 2002
|
-- Modifier : ZHAO Ming
|
-- Modifier : ZHAO Ming
|
-- Desccription : Point configurable
|
-- Desccription : Point configurable
|
--
|
--
|
---------------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.all;
|
use IEEE.STD_LOGIC_1164.all;
|
use IEEE.STD_LOGIC_ARITH.all;
|
use IEEE.STD_LOGIC_ARITH.all;
|
use IEEE.STD_LOGIC_SIGNED.all;
|
use IEEE.STD_LOGIC_SIGNED.all;
|
|
|
entity mulfactor is
|
entity mulfactor is
|
generic (
|
generic (
|
WIDTH : Natural:=12;
|
WIDTH : Natural:=12;
|
STAGE : Natural:=3
|
STAGE : Natural:=3
|
);
|
);
|
port(
|
port(
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
angle : in signed(2*STAGE-1 downto 0);
|
angle : in signed(2*STAGE-1 downto 0);
|
I : in signed(WIDTH+1 downto 0);
|
I : in signed(WIDTH+1 downto 0);
|
Q : in signed(WIDTH+1 downto 0);
|
Q : in signed(WIDTH+1 downto 0);
|
Iout : out signed(WIDTH+3 downto 0);
|
Iout : out signed(WIDTH+3 downto 0);
|
Qout : out signed(WIDTH+3 downto 0)
|
Qout : out signed(WIDTH+3 downto 0)
|
);
|
);
|
end mulfactor;
|
end mulfactor;
|
|
|
|
|
architecture mulfactor of mulfactor is
|
architecture mulfactor of mulfactor is
|
signal phase : signed( 2*STAGE-3 downto 0 );
|
signal phase : signed( 2*STAGE-3 downto 0 );
|
signal Xi,Yi : signed( WIDTH+1 downto 0 );
|
signal Xi,Yi : signed( WIDTH+1 downto 0 );
|
component sc_corproc
|
component sc_corproc
|
generic(
|
generic(
|
WIDTH : Natural;
|
WIDTH : Natural;
|
STAGE : Natural
|
STAGE : Natural
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
ena : in std_logic;
|
ena : in std_logic;
|
Xin : in signed(WIDTH+1 downto 0);
|
Xin : in signed(WIDTH+1 downto 0);
|
Yin : in signed(WIDTH+1 downto 0);
|
Yin : in signed(WIDTH+1 downto 0);
|
Ain : in signed(2*STAGE-3 downto 0 );
|
Ain : in signed(2*STAGE-3 downto 0 );
|
|
|
sin : out signed(WIDTH+3 downto 0);
|
sin : out signed(WIDTH+3 downto 0);
|
cos : out signed(WIDTH+3 downto 0));
|
cos : out signed(WIDTH+3 downto 0));
|
end component;
|
end component;
|
|
|
begin
|
begin
|
|
|
u1: sc_corproc
|
u1: sc_corproc
|
generic map(
|
generic map(
|
WIDTH=>WIDTH,
|
WIDTH=>WIDTH,
|
STAGE=>STAGE
|
STAGE=>STAGE
|
)
|
)
|
port map (
|
port map (
|
clk=>clk,
|
clk=>clk,
|
ena=>'1',
|
ena=>'1',
|
Xin=>Xi,
|
Xin=>Xi,
|
Yin=>Yi,
|
Yin=>Yi,
|
Ain=>phase,
|
Ain=>phase,
|
|
|
sin=>Qout,
|
sin=>Qout,
|
cos=>Iout
|
cos=>Iout
|
);
|
);
|
|
|
process( clk, rst )
|
process( clk, rst )
|
variable temp : std_logic_vector( 1 downto 0 );
|
variable temp : std_logic_vector( 1 downto 0 );
|
begin
|
begin
|
if rst='1' then
|
if rst='1' then
|
phase<=( others=>'0' );
|
phase<=( others=>'0' );
|
Xi<=( others=>'0' );
|
Xi<=( others=>'0' );
|
Yi<=( others=>'0' );
|
Yi<=( others=>'0' );
|
elsif clk'event and clk='1' then
|
elsif clk'event and clk='1' then
|
phase<=angle( 2*STAGE-3 downto 0 );
|
phase<=angle( 2*STAGE-3 downto 0 );
|
temp:=std_logic_vector(angle( 2*STAGE-1 downto 2*STAGE-2 ));
|
temp:=std_logic_vector(angle( 2*STAGE-1 downto 2*STAGE-2 ));
|
case temp is
|
case temp is
|
when "00" =>
|
when "00" =>
|
Xi<=I;
|
Xi<=I;
|
Yi<=Q;
|
Yi<=Q;
|
when "01" =>
|
when "01" =>
|
Xi<=0-Q;
|
Xi<=0-Q;
|
Yi<=I;
|
Yi<=I;
|
when "10" =>
|
when "10" =>
|
Xi<=0-I;
|
Xi<=0-I;
|
Yi<=0-Q;
|
Yi<=0-Q;
|
when "11" =>
|
when "11" =>
|
Xi<=Q;
|
Xi<=Q;
|
Yi<=0-I;
|
Yi<=0-I;
|
when others=>
|
when others=>
|
null;
|
null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end mulfactor;
|
end mulfactor;
|
|
|
