URL
https://opencores.org/ocsvn/ofdm/ofdm/trunk
[/] [ofdm/] [branches/] [avendor/] [ofdm.npl] - Diff between revs 4 and 13
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| Rev 4 |
Rev 13 |
JDF G
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JDF G
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// Created by Project Navigator ver 1.0
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// Created by Project Navigator ver 1.0
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PROJECT ofdm
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PROJECT ofdm
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DESIGN ofdm
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DESIGN ofdm
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DEVFAM spartan2
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DEVFAM spartan2
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DEVFAMTIME 1145426085
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DEVFAMTIME 1145426085
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DEVICE xc2s200
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DEVICE xc2s200
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DEVICETIME 1145426085
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DEVICETIME 1145426085
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DEVPKG pq208
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DEVPKG pq208
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DEVPKGTIME 1145425004
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DEVPKGTIME 1145425004
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DEVSPEED -5
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DEVSPEED -5
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DEVSPEEDTIME 1145426085
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DEVSPEEDTIME 1145426085
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DEVTOPLEVELMODULETYPE HDL
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DEVTOPLEVELMODULETYPE HDL
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TOPLEVELMODULETYPETIME 0
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TOPLEVELMODULETYPETIME 0
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DEVSYNTHESISTOOL XST (VHDL/Verilog)
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DEVSYNTHESISTOOL XST (VHDL/Verilog)
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SYNTHESISTOOLTIME 0
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SYNTHESISTOOLTIME 0
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DEVSIMULATOR Other
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DEVSIMULATOR Other
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SIMULATORTIME 0
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SIMULATORTIME 0
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DEVGENERATEDSIMULATIONMODEL VHDL
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DEVGENERATEDSIMULATIONMODEL VHDL
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GENERATEDSIMULATIONMODELTIME 0
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GENERATEDSIMULATIONMODELTIME 0
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SOURCE modem.vhd
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SOURCE modem.vhd
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SOURCE ram.vhd
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SOURCE ram.vhd
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SOURCE mux.vhd
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SOURCE mux.vhd
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SOURCE rxmodem.vhd
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SOURCE rxmodem.vhd
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SOURCE cfft.vhd
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SOURCE cfft.vhd
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SOURCE input.vhd
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SOURCE input.vhd
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SOURCE p2r_CordicPipe.vhd
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SOURCE p2r_CordicPipe.vhd
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SOURCE txmodem.vhd
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SOURCE txmodem.vhd
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SOURCE blockdram.vhd
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SOURCE blockdram.vhd
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SOURCE conj.vhd
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SOURCE conj.vhd
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SOURCE ofdm.vhd
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SOURCE ofdm.vhd
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SOURCE mulfactor.vhd
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SOURCE mulfactor.vhd
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SOURCE counter.vhd
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SOURCE counter.vhd
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SOURCE div4limit.vhd
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SOURCE div4limit.vhd
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SOURCE cfft4.vhd
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SOURCE cfft4.vhd
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SOURCE inv_control.vhd
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SOURCE inv_control.vhd
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SOURCE ram_control.vhd
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SOURCE ram_control.vhd
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SOURCE rofactor.vhd
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SOURCE rofactor.vhd
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SOURCE mux_control.vhd
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SOURCE mux_control.vhd
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SOURCE starts.vhd
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SOURCE starts.vhd
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SOURCE txrx.vhd
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SOURCE txrx.vhd
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SOURCE cfft_control.vhd
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SOURCE cfft_control.vhd
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SOURCE io_control.vhd
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SOURCE io_control.vhd
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SOURCE output.vhd
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SOURCE output.vhd
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SOURCE p2r_cordic.vhd
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SOURCE p2r_cordic.vhd
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SOURCE sc_corproc.vhd
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SOURCE sc_corproc.vhd
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[Normal]
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[Normal]
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p_xstVerilog2001=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
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p_xstVerilog2001=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
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_SynthOptEffort=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, Normal
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_SynthOptEffort=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, Normal
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_SynthResSharing=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
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_SynthResSharing=xstvhd, spartan2, VHDL.t_synthesize, 1145427464, True
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[STRATEGY-LIST]
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[STRATEGY-LIST]
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Normal=True
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Normal=True
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